Working with Verilog (a hardware-description language) in college was a real struggle for me. Even though it looks kinda like conventional code, it does not execute like conventional code, top-to-bottom. Instead it executes as hardware would, in "time-slices", which made it very difficult for me to reason about. It was really cool when I simulated a MIPS CPU entirely in Verilog, except that I could never get it working properly.
We're a place where coders share, stay up-to-date and grow their careers.
We strive for transparency and don't collect excess data.