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LDO Layout Techniques: Ground, Sensing, and Capacitor Placement

朱常 — Wed, 04 Nov 2026 02:20:28 +0000

LDO Layout Techniques: Ground, Sensing, and Capacitor Placement

A good LDO on paper can still behave badly on a bad printed circuit board. The devices themselves are forgiving, but the currents they carry, the grounds they reference, and the high-frequency paths they rely on are easy to get wrong. Layout choices determine whether the measured PSRR, transient response, and noise match the datasheet, and whether the regulator oscillates or behaves. This article walks through the practical layout rules that separate a clean supply from a noisy one.

The Ground Pin Carries Real Current

The LDO's ground pin is not a quiet reference. The quiescent current, the bias current for the internal circuits, and the return current of the external feedback divider all flow through it. Any resistance in that path appears as a voltage drop, and that drop is subtracted from the regulated output, because the internal reference is measured relative to the ground pin. The practical consequence is that the ground pin must be connected to the board ground with the lowest possible impedance, directly under the package, without sharing a narrow trace with other return currents. Star grounding, where the regulator's ground pin connects to a quiet local ground that then joins the system ground at one point, avoids pulling noisy currents through the sensitive node.

Input and Output Capacitor Placement

The input capacitor must sit as close as possible to the input and ground pins, because it supplies the fast currents that the regulator demands during transients and reduces the high-frequency impedance of the source. A long trace between the capacitor and the pin adds inductance that the capacitor cannot offset. The output capacitor must likewise sit close to the output pin, because it is the local energy reservoir for the load step and the stability element of the loop. Ceramic capacitors are preferred because of their low ESR, but multiple smaller capacitors in parallel can be used when a single large part would be bulky. The loop stability depends on the output capacitor's ESR and capacitance, so substituting parts without checking the datasheet is a common cause of oscillation.

Sense and Kelvin Connections

When the load is far from the regulator, the trace resistance between the device and the load adds a millivolt-scale voltage drop under load. Adjustable LDOs allow remote sensing: the feedback trace is connected directly at the load, so the regulator compensates for the drop in the trace. The sense trace must be a Kelvin connection, taken from the load's output node and routed separately from the power trace, and it must be kept away from switching traces because it is a high-impedance node. Remote sensing is not available on every fixed part, so for long or heavy loads the trace resistance should be calculated and kept below a few tens of milliohms.

Minimizing Parasitic Inductance

Every trace has inductance, and at the fast edges of a load transient even a few nanohenries matter. The input and output loops, formed by the capacitor, the pin, and the ground return, should be as small as possible, with the capacitor ground placed directly under the package ground. Vias placed near the pads reduce inductance, but too many vias under a small part can complicate soldering. The feedback trace should be short and direct, with no unnecessary vias, because any extra series inductance or shunt capacitance shifts the loop poles.

Avoiding Ground Bounce and Coupling

The ground bounce caused by large digital return currents on the same plane as the analog ground can couple into the LDO and appear on the output. The usual remedy is to split the layout into quiet and noisy areas, with the LDO and its load on the quiet side, and to connect the two grounds at a single point under the regulator. Digital return paths should never run under the LDO package. Likewise, the LDO should be kept away from crystal oscillators, switching converters, and high-speed data lines, whose fields can couple into the sensitive feedback node.

The Bypass and Noise-Reduction Pins

Many LDOs include a bypass pin, which connects to the internal reference through an external capacitor. That capacitor filters the reference noise and is one of the most important components for low-noise performance. It must be placed directly at the pin, and its ground must be a quiet local ground, not the noisy digital return. A long trace on the bypass pin turns the capacitor into an antenna rather than a filter, and defeats the purpose of the part.

A Layout Checklist

Before sending a board for fabrication, it is worth running through a short list. The input capacitor is within a few millimeters of the input pin. The output capacitor is close to the output pin and its ground returns to the LDO ground. The feedback trace is short, quiet, and Kelvin if remote sensing is used. The ground pin connects directly to a quiet local ground. The thermal pad, if present, has multiple vias to a ground plane. The LDO is kept away from switching and clocking circuits. Following these rules does not guarantee success, but violating them is a common way to turn a good regulator into an unstable one.

Summary

The LDO ground pin carries real bias current and must be connected to a low-impedance quiet ground.
Input and output capacitors must be placed close to their pins to keep loop inductance low.
Remote sensing uses a Kelvin feedback connection to compensate for trace drops at distant loads.
The bypass pin capacitor must be local and referenced to quiet ground to actually reduce output noise.
Keeping the LDO away from noisy digital circuits and using a clean ground plan is as important as the schematic.

Testing Load and Line Transient Response on the Bench

朱常 — Wed, 04 Nov 2026 02:19:58 +0000

Testing Load and Line Transient Response on the Bench

ersaelectronics.com

A regulator's steady-state accuracy is only half the story. The real test is how the output behaves when the load current changes suddenly, or when the input voltage jumps. Load and line transient response is what determines whether a downstream chip sees a clean supply during bursts of activity, and it is one of the most frequently mis-measured parameters on a lab bench. This article explains how to set up a transient test, how to probe it without corrupting the result, and how to interpret the droop, overshoot, and recovery time that the scope shows.

What the Transient Test Measures

The load transient test forces the output current to jump between two levels, often from 10 percent to 100 percent of the rated load, and records the output voltage as it dips and recovers. The line transient test does the same on the input: the input voltage is stepped, and the output deviation is measured. The three numbers that matter are the maximum droop below nominal, the overshoot above nominal, and the time taken to settle back within a band around the nominal value. A regulator that looks perfect at DC can fail a real system if its droop is large or its recovery is slow.

The Electronic Load

A fast, programmable electronic load is the heart of the test. The load must be able to switch between two current levels in a small fraction of a microsecond, because a slow load step hides the regulator's true response. The load's slew rate and its pulse generation are specified in the datasheet, and the designer should pick a load whose transition is at least as fast as the real load being emulated. The load should be set to constant-current mode, and the edges should be verified on a scope by measuring the voltage across a small sense resistor in series with the load.

Input and Output Capacitors

The test must be run with the exact input and output capacitors recommended by the LDO datasheet, because the output capacitor is the main energy reservoir that holds up the rail during a fast load step. Using a different capacitor, especially one with higher equivalent series resistance, changes both the droop amplitude and the loop stability. Ceramic capacitors are preferred because of their low ESR, but their DC-bias derating must be accounted for, since a 10 uF ceramic may behave like a few microfarads at the operating bias.

Probing the Output Voltage

Probing is where most transient measurements go wrong. The scope ground lead, with its long clip, forms a large loop antenna that picks up the fast currents and produces a false ringing on the trace. The correct technique is to use a short ground spring on an active probe, with the probe tip placed directly at the output capacitor or at the load, and the ground return connected at the same local ground. The probe bandwidth should be at least ten times the frequency of interest, and the scope should be set to single-shot capture so the first transient is not missed. The input voltage should also be monitored, because an input sag caused by a weak supply is often mistaken for a regulator problem.

Interpreting the Droop

When the load current steps up, the output voltage briefly falls. The initial droop is set by the output capacitor and its ESR: the faster the current step, the larger the instantaneous drop. The control loop then reacts, and the voltage recovers. A well-designed LDO recovers within a few microseconds, with no more than a few percent deviation. A large, slow droop indicates a low-bandwidth loop, insufficient output capacitance, or an unstable loop. A droop that oscillates before settling suggests loop instability and a loop-compensation problem that must be fixed before production.

Interpreting the Overshoot

When the load current steps down, the output briefly rises. The overshoot comes from the inductor-like inductance of the board and from the loop's delay in reducing the pass-element current. Again, a small, fast overshoot is fine; a large overshoot can trip the downstream chip's absolute maximum ratings. Overshoot is often worse than droop, because the loop must now oppose a current that has already stopped flowing, and the only way to absorb the excess energy is the output capacitor. Larger output capacitance reduces overshoot but slows the loop, so there is a trade-off.

Line Transient Testing

The line transient test is set up similarly, but the input supply is stepped instead of the load. A fast electronic supply or a signal generator coupled through a capacitor produces the input step. The output deviation measures the regulator's line transient response, which is related to but not identical with PSRR at DC. A regulator with good DC PSRR can still show a large output glitch for a fast input step, because the loop cannot react faster than its bandwidth. This test is particularly important when the LDO post-regulates a switching converter whose output has fast edges.

Reporting the Results

When documenting the transient response, record the load step size, the slew rate, the input voltage, the output current levels, the capacitor values, and the probe setup. Without these details, the numbers cannot be reproduced or compared. The datasheet's typical curves are measured on a specific demo board, and a different board layout will give different results, so the designer's own bench data is the one that matters.

Summary

Load and line transient tests measure how the output reacts to sudden changes in current or input voltage.
Use a fast electronic load in constant-current mode, the datasheet capacitors, and a short ground-spring probe.
Droop is set mainly by the output capacitor and loop bandwidth; overshoot by the loop delay and board inductance.
Oscillation during recovery indicates loop instability and must be fixed before the design is accepted.
The test setup, not just the numbers, must be documented so the result can be reproduced and trusted.

LDO Packages and Thermal Management: Keeping the Pass Element Cool

朱常 — Wed, 04 Nov 2026 02:19:32 +0000

LDO Packages and Thermal Management: Keeping the Pass Element Cool

ersaelectronics.com

An LDO is, by design, a device that converts unwanted voltage difference into heat. At low current and small headroom the heat is negligible, but as the load current or the input-to-output difference grows, the package and the printed circuit board become active parts of the power design. A regulator rated for 1 A on paper can deliver far less if its package cannot shed the heat, and the difference between parts with similar silicon often comes down to how well they are packaged. This article reviews the common LDO packages, the thermal resistance parameters, and the board-level design choices that actually limit the heat.

Where the Heat Comes From

The power dissipated by an LDO is approximately the input-to-output voltage difference multiplied by the load current, plus the small quiescent power. At 5 V input to 3.3 V output at 500 mA, the dissipation is about 0.85 W. At 12 V to 3.3 V at the same current, it is nearly 4.5 W, which is impossible to handle in a tiny SOT-23. The designer must first choose whether the LDO is even a viable option for the expected dissipation, and then choose a package and board layout that keep the junction temperature within the rated limit, typically in the range of 125 to 150 degrees Celsius.

Common Package Types

Small signal LDOs come in packages such as SOT-23, SC-70, and XDFN-style wafer-level packages, which are ideal for low-current applications where heat is not a concern. Higher-current parts move to SOT-223, DPAK, TO-252, and SOIC with an exposed thermal pad. The through-hole TO-220 family is still used in industrial and bench supplies where a heatsink can be attached. The package size is set by thermal needs more than by silicon needs: the die itself is small, but the package must spread the heat into the board.

Theta-JA and What It Really Means

The junction-to-ambient thermal resistance, written theta-JA, is the number most often quoted on datasheets, but it is also the most misleading. It is measured on a standardized test board with a specific amount of copper, and a part quoted at 100 degrees Celsius per watt on the test board may run at 200 degrees Celsius per watt on a real two-layer board. Theta-JC, junction-to-case, is more useful when a heatsink is attached, and theta-JP, junction-to-pad, is relevant for exposed-pad packages. The practical lesson is to treat the datasheet thermal numbers as a starting point, not a guarantee, and to design in enough copper that the real thermal resistance comes out well below the quoted maximum.

PCB Copper and Thermal Pads

The board is the main heatsink for most surface-mount LDOs. Several square centimeters of copper on the top layer, connected to the thermal pad with multiple vias to an inner plane or a bottom-layer copper area, can drop the effective thermal resistance by a factor of two or three compared with a small pad. The vias should be small, plentiful, and capped or filled to prevent solder wicking into them. For high-power parts, a dedicated ground plane under the package is the single most effective layout choice. The thermal pad must be soldered, not just tented, because the solder joint is the primary thermal path.

Heatsinks and Forced Air

When the dissipation exceeds what the board can handle, a surface-mount heatsink can be attached to the package, or the part can be moved to a through-hole package with a bolt-on heatsink. Forced air further improves the cooling by lowering the effective ambient temperature. In sealed enclosures, the internal ambient can be much higher than the room, and the designer must derate the thermal resistance accordingly. A useful rule is to assume an internal ambient 20 to 40 degrees above the outside air in a sealed box, and to size the heatsink for that worst case.

Protecting Against Thermal Overstress

Most modern LDOs include thermal shutdown, which disables the pass element when the junction exceeds a threshold, typically around 150 to 170 degrees Celsius, and re-enables it when the part cools. This prevents destruction but is not a substitute for good design: a part that cycles through thermal shutdown is unstable, noisy, and unpleasant for the user. The correct approach is to keep the normal operating junction temperature well below the shutdown threshold, with margin for hot days and blocked vents.

Practical Heat Budget

A quick thermal check should be done before the part is chosen. Estimate the worst-case dissipation, estimate the effective theta-JA of the chosen package on the planned board, multiply to get the temperature rise above ambient, and add the worst-case internal ambient. If the result exceeds the rated maximum junction temperature, either reduce the headroom by lowering the upstream voltage, spread the dissipation across multiple regulators, move to a switching converter, or upgrade the package and copper. Heat budgets that look fine on paper often fail in the field because the real board has less copper than the datasheet test board.

Summary

An LDO dissipates the product of input-to-output differential and load current as heat.
Package size is mostly about heat spreading, not silicon size; SOT-23 parts are for low current, DPAK and exposed-pad SOIC for higher current.
Theta-JA is measured on an idealized board, so real values are usually worse; design extra copper accordingly.
A ground plane under the thermal pad, with multiple vias, is the most effective board-level cooling technique.
Thermal shutdown protects the part but is not a design strategy; the normal operating temperature must stay well below the limit.

Multi-Output LDOs and Rail Sequencing in Mixed-Signal Systems

朱常 — Wed, 04 Nov 2026 02:19:03 +0000

Multi-Output LDOs and Rail Sequencing in Mixed-Signal Systems

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Modern mixed-signal systems rarely have a single supply rail. A typical chipset may need a core voltage, an input-output voltage, an analog supply, a clock supply, and a memory rail, each at a different voltage and each with its own noise and transient requirements. These rails are often produced by several LDOs, either on separate chips or integrated into a multi-output device, and the order and timing in which they come up at power-on can affect reliability, signal integrity, and even silicon survival. This article explains why rail sequencing matters, how multi-output LDOs implement it, and what a designer must control at the board level.

Why Sequencing Is Needed

Digital and mixed-signal integrated circuits have internal structures that assume the supplies appear in a particular order. If an input-output rail comes up before the core rail, parasitic diodes on the chip can conduct and latch up; if the analog rail comes up before the digital rail, the reference circuits may not settle cleanly; if one rail rises much faster than another, current can flow through unintended paths. The result can range from a soft start-up glitch to permanent damage. Semiconductor datasheets therefore specify power-up sequences, maximum voltage differences between adjacent rails, and the allowed ramp rates. Multi-output LDOs and dedicated sequencers exist specifically to enforce these requirements.

Enable-Pin Control

The simplest way to sequence rails is to daisy-chain the enable pins. When the first LDO reaches its rated output, its power-good or output-ready signal enables the next LDO, which in turn enables the one after that. This produces a strictly sequential start-up with the order fixed by the wiring. It is inexpensive, robust, and easy to understand, but it is slow because each rail must fully settle before the next starts, and it does not tolerate overlapping or ramping rails. Most LDOs include an enable pin with a defined threshold, and many include a power-good open-drain output that is perfect for chaining.

Tracking and Simultaneous Ramping

Some systems require the rails to ramp up together rather than one after another. In tracking mode, multiple LDOs are tied to a common slow-start signal, and their outputs rise in parallel at a controlled rate. This keeps the voltage differences between rails small during start-up, which is important for devices that cannot tolerate large mismatches. Tracking is also useful when the rails feed a single chip whose I/O levels must remain proportional to its core voltage. Multi-output LDOs often include a tracking input or a shared slow-start capacitor that implements this behavior in silicon.

Multi-Output LDO Devices

A multi-output LDO integrates two or more regulators in one package, sharing the input supply, the reference, and the control logic. The benefits are smaller board area, simpler inventory, and coordinated sequencing built in. The trade-off is that all the outputs share the same input and the same package thermal budget, so a fault on one output can affect the others. Multi-output parts are commonly used for processor I/O and core supplies, for camera modules, and for portable devices where board area is at a premium. The designer still has to verify that the total package dissipation stays within limits when all outputs are loaded simultaneously.

Timing and Ramp-Rate Control

The ramp rate of each rail matters as much as the order. A rail that rises too quickly can overshoot, injecting charge into the downstream chip and causing latch-up or ESD stress. A rail that rises too slowly delays the system start-up and may leave downstream circuits in an undefined state for too long. Most LDOs offer a slow-start or soft-start pin, where an external capacitor sets the ramp time in the range of a few hundred microseconds to several milliseconds. Choosing the right capacitor is a trade-off between clean start-up and fast turn-on, and it should be checked against the silicon's specified ramp tolerance.

Shutdown Sequencing

Power-down sequencing is as important as power-up. When the supply is removed, the rails can collapse in unpredictable order, and again the parasitic paths inside the chips must be protected. Controlled shutdown, achieved by turning off the enables in the reverse order of start-up, ensures that each rail is discharged gracefully and that no rail lingers while its neighbors have already fallen. In battery-powered systems the shutdown sequence also affects battery drain, because any rail that stays alive continues to draw current.

Practical Design Tips

Several practical points help. First, read the silicon's power-up specification carefully: it usually states not only the required order but also the allowed overlap and the maximum delay between rails. Second, add a power-good or reset supervisor that holds the downstream chip in reset until all rails have settled. Third, decouple each rail locally so that transient currents on one output do not perturb another. Fourth, test the sequencing on the bench with a scope capturing all the enable signals and the rail voltages, because the wiring and capacitor choices can shift the timing in ways that simulation does not predict.

Summary

Mixed-signal systems require multiple supply rails, and the order and timing in which they appear can affect reliability.
Sequencing is implemented by enable-pin chaining, by shared slow-start tracking, or by integrated multi-output LDOs.
Ramp rate control and power-good signals are essential to prevent overshoot, latch-up, and undefined states.
Power-down sequencing is the reverse of power-up and is equally important for protecting downstream chips.
The bench verification of sequencing, not just the schematic, is what catches timing errors before production.

Generating Negative Rails: Negative LDOs and Floating-Ground Tricks

朱常 — Wed, 04 Nov 2026 02:18:35 +0000

Generating Negative Rails: Negative LDOs and Floating-Ground Tricks

ersaelectronics.com

Many analog systems need both positive and negative supply rails. Audio amplifiers, bipolar op-amps, instrumentation front ends, precision references, and RS-232 line drivers all expect a symmetric supply, and a single positive battery or wall adapter is rarely enough. Linear regulators are normally associated with positive rails, but the same principle can be extended to negative voltages. This article explains how negative rails are produced, compares dedicated negative LDOs with the floating-ground trick, and outlines the practical limitations of each approach.

Why Negative Rails Are Needed

A single-supply op-amp can work with input voltages swinging close to ground, but it cannot drive its output below ground. AC-coupled audio circuits, precision sensor interfaces, and instrumentation amplifiers often require the output to swing symmetrically around zero, which means the device must be powered between a positive rail and a negative rail, commonly plus and minus 5 V, 12 V, or 15 V. Without a negative rail, the output is clipped or offset, and the dynamic range shrinks. In battery-powered portable gear, the positive rail may come straight from the cell, so the negative rail has to be generated from the positive supply.

Dedicated Negative LDOs

A negative LDO is conceptually the same device as a positive LDO, but with the pass element and the control loop arranged for current sinking rather than sourcing. The input is typically the most positive node, the ground reference sits at the middle, and the regulated output sits below ground. Parts are commonly available for outputs such as minus 5 V, minus 12 V, or adjustable negative voltages, and they share the same advantages as positive LDOs: quiet output, fast response, and small external parts. The main caveat is that they need a negative input supply already present, which usually comes from an inverting switching converter, a charge pump, or a transformer winding. The negative LDO then cleans up the rail produced by that noisy source.

The Floating-Ground Trick

A positive LDO can be made to produce a negative rail without any dedicated negative silicon, by floating its ground pin below system ground. In this arrangement, the input of the LDO is tied to the system ground, the output is the desired negative voltage, and the LDO's own ground pin is lifted up to the output voltage by a small current source or a resistor. The part now regulates the voltage between its output and its own ground pin, which from the system's perspective appears as a negative output relative to the system ground. The trick uses any positive LDO as a negative regulator, but the part's internal ground pin current now flows through the external element that sets the floating node, and that current becomes a source of error and noise. This approach is most common in low-current audio and analog circuits where simplicity matters more than absolute accuracy.

Efficiency and Power

Whether a negative rail is produced by a dedicated negative LDO or by a floating positive LDO, the linear stage dissipates the same power: the magnitude of the input-to-output differential times the load current. If the negative LDO is fed from minus 15 V and produces minus 5 V at 100 mA, it dissipates 1 W, exactly as a positive LDO would under the equivalent conditions. The upstream inverting converter, not the LDO, sets the overall efficiency, and the LDO exists primarily to clean up the switching ripple. For high-current negative rails, the heat of the linear stage becomes a real constraint, and a switching regulator alone may be preferred.

Noise and PSRR Considerations

The same noise and PSRR advantages that make LDOs attractive on positive rails apply to negative rails. A negative LDO post-regulating an inverting buck or charge pump removes the switching ripple that would otherwise pollute an audio or measurement circuit. The floating-ground trick preserves the LDO's inherent quietness but adds the noise of the current source that floats the ground pin, so that source must itself be quiet. In audio circuits the choice often comes down to which approach produces the lower residual output noise.

Limitations and Gotchas

Several practical limits apply. First, the input voltage range of the negative LDO must cover the worst-case upstream output, including ripple and load steps. Second, the output must be able to tolerate reverse currents during start-up, because loads on a negative rail can pull current back toward ground. Third, the enable and control signals referenced to system ground must be level-shifted to the floating ground when the floating trick is used. Fourth, the power dissipation in the linear stage is easily underestimated because the designer is used to thinking about positive voltages; the differential on a minus 12 V to minus 5 V LDO is 7 V, which is far more than a typical positive LDO sees.

Typical Applications

Negative LDOs are ubiquitous in audio interfaces, where a low-noise negative rail for the op-amp stage is essential for low distortion. They are also found in precision data acquisition, in bipolar analog-to-digital converters, in RS-232 and other legacy line drivers, and in laboratory instrumentation. The floating-ground variant appears in low-cost audio accessories, battery-powered measurement probes, and small analog modules where adding a dedicated negative regulator would be overkill.

Summary

Negative rails are needed by audio, instrumentation, and bipolar op-amp circuits that must swing symmetrically around ground.
Dedicated negative LDOs regulate a negative output from a negative input and share the quiet, fast behavior of positive LDOs.
A positive LDO can be converted into a negative regulator by floating its ground pin, but this adds error and noise from the floating element.
The linear stage dissipates the product of the input-to-output differential and the load current, so heat is a real concern at high current or large differentials.
In practice the negative LDO is used as a clean post-regulator behind an inverting switching converter or charge pump.

Fixed versus Adjustable Output LDOs: Flexibility Versus Precision

朱常 — Wed, 04 Nov 2026 02:18:08 +0000

Fixed versus Adjustable Output LDOs: Flexibility Versus Precision

ersaelectronics.com

LDO regulators come in two broad flavors: fixed-output parts, with the feedback divider integrated on the die and trimmed at manufacture, and adjustable parts, which expose the feedback node so the designer sets the output voltage with an external resistor divider. The choice looks like a small detail, but it affects output accuracy, noise, component count, board space, and the engineering effort required to get the rail right. This article compares the two approaches and explains when each is the better choice.

How Each One Works

A fixed-output LDO has an internal precision reference and an internal divider that is factory-trimmed to set a standard output such as 1.8 V, 2.5 V, 3.3 V, or 5 V. The user connects only the input and output capacitors. An adjustable LDO brings the feedback node out to a pin, and the designer picks two external resistors whose ratio sets the output according to the reference voltage, commonly around 0.6 to 1.2 V. The output voltage is then the reference multiplied by one plus the ratio of the upper to the lower divider resistor. The internal reference is the same in both cases; the difference is where the divider lives.

Output Accuracy

A fixed-output part is usually more accurate. The internal divider is trimmed at the factory together with the reference, so the total output tolerance, including reference accuracy, divider ratio tolerance, and temperature drift, can be held to a percent or better over temperature. An adjustable part inherits the reference accuracy and the internal offset, but the external divider resistors add their own tolerances and temperature coefficients. A pair of ordinary resistors with one percent tolerance and a hundred parts-per-million per degree drift can easily add two percent of output error, which is unacceptable in many precision supplies. Using high-grade resistors helps but adds cost and board space. For rails that feed precision ADC references or clocking circuits, the fixed part is usually the safer choice.

The Noise Penalty of the External Divider

The feedback node is a high-impedance point inside the control loop, and the external divider resistors act as a noise source and a noise antenna. Resistor thermal noise scales with resistance, and the divider injects that noise directly into the error amplifier. High-value dividers, chosen to keep standby current low, produce more noise and are also more susceptible to board leakage and pickup from nearby signals. Many adjustable parts include a bypass pin that allows a capacitor across the upper divider resistor to filter reference noise, but that capacitor also adds a pole that must be compensated. A fixed part, with its low internal divider, avoids most of this and generally achieves lower output noise, typically by a factor of two or more compared with the same silicon used in adjustable form.

Quiescent and Divider Current

The external divider draws a small current from the output continuously. To keep that current negligible, designers typically choose divider resistors in the range of tens to hundreds of kiloohms, which still drains a few microamperes from the rail. In battery-operated systems that are always on, this added current can matter at the margins, and it is one more thing to budget. The fixed part has no external divider current because its internal divider is sized by the manufacturer for the best tradeoff between accuracy and power.

Flexibility and Inventory

The adjustable part's strength is flexibility. One device can generate any output within its range simply by changing two resistors, which is valuable during prototyping, in multi-project systems, or when the output voltage may change late in design. From an inventory perspective, a single adjustable part can cover several rails that would otherwise require several fixed part numbers. For a production product with a stable bill of materials, that flexibility is worth less, and the simplicity and accuracy of the fixed part usually win.

Layout and Stability Considerations

The feedback trace on an adjustable LDO is a sensitive node. It must be kept short, away from switching traces, and connected directly at the load if remote sensing is used. Any stray capacitance on the feedback pin shifts the loop poles and can cause instability or excess noise. The fixed part hides this node inside the package, which makes layout easier and more forgiving. Designers who use adjustable parts must also verify loop stability with the chosen divider values and output capacitor, because the feedback network is now part of the compensation.

When to Choose Which

Choose a fixed part when the rail voltage is a standard value, accuracy and low noise matter, and the design is in production. Choose an adjustable part when the required voltage is non-standard, when the same part will be reused across multiple rails or products, when prototyping speed matters, or when remote sensing and tracking are needed. In audio, precision measurement, and clocking supplies, the fixed part is usually preferred; in general-purpose power trees and development boards, the adjustable part is often the pragmatic choice.

Summary

Fixed-output LDOs integrate and trim the feedback divider on die, giving better accuracy and lower noise.
Adjustable LDOs use an external resistor divider, trading some accuracy and noise for voltage flexibility.
The external divider adds resistor tolerance, drift, thermal noise, and a small continuous drain current.
Adjustable parts simplify inventory across multiple rails but demand more careful layout and stability work.
The choice comes down to whether precision and simplicity matter more than voltage flexibility.

LDO or Charge Pump? Choosing Between Linear and Switched-Capacitor Regulation

朱常 — Wed, 04 Nov 2026 02:17:41 +0000

LDO or Charge Pump? Choosing Between Linear and Switched-Capacitor Regulation

ersaelectronics.com

When a design needs a small, low-power regulated rail, the choice often narrows to two candidates: a low-dropout linear regulator or a switched-capacitor converter, commonly called a charge pump. Both use no inductor, both are available in small packages, and both are inexpensive, but they behave very differently under the hood. A charge pump can step up, step down, or even invert the input voltage, while an LDO can only step down, so the two are not direct competitors in every application. This article compares them on efficiency, noise, size, and flexibility, and explains when one is clearly the better choice.

How a Charge Pump Works

A charge pump uses flying capacitors and switches to move charge between rails. In its simplest voltage-doubling form, a flying capacitor is first connected across the input, charged to the input voltage, and then reconnected in series with the input to deliver roughly twice the voltage at the output. More advanced configurations can divide the input by two, generate a negative rail from a positive one, or produce an adjustable output through fractional conversion ratios. The switches operate at a fixed or variable switching frequency, typically in the range of a few hundred kilohertz to a few megahertz, and the output is smoothed by an output capacitor. Because no inductor is used, the solution can be small and cheap, but the output is inherently choppy.

Efficiency

An LDO operating on a small input-to-output differential can be very efficient, approaching Vout/Vin, which may be 90 percent or better. A charge pump's efficiency depends on its conversion ratio. In a perfect voltage doubler, the output current is half the input current and the theoretical efficiency approaches 100 percent when the output voltage is exactly twice the input, but real parts lose energy in the switches and capacitors, and efficiency falls off when the output moves away from the ideal ratio. A step-down charge pump with a 2:1 ratio can also be efficient, but for ratios that do not match the flying-capacitor configuration, the pump must regulate by linear control or by skipping cycles, and efficiency degrades sharply. An LDO is usually more efficient than a charge pump when the input is already close to the desired output.

Ripple and Noise

This is the most important practical difference. An LDO output is quiet: it contains no switching ripple, only broadband noise from the reference and amplifier, typically in the range of tens of microvolts. A charge pump output contains periodic ripple at the switching frequency, with amplitude set by the output capacitor, the load current, and the switch resistance. Even with large output capacitors, ripple of several millivolts is common, and the fast edges of the switching waveform generate high-frequency spikes. For analog, audio, RF, or precision measurement rails, a charge pump is almost never acceptable on its own, although it is sometimes followed by a small LDO to clean up the rail.

Voltage Range and Function

An LDO can only produce a lower voltage than its input. A charge pump can step up, step down, or invert, which makes it uniquely useful in several situations: generating a negative supply for an op-amp or audio stage from a single positive rail; producing a boosted gate-drive voltage; or creating a higher voltage for an LCD bias or LED string. In these applications there is no linear alternative that can do the job without an inductor, and the charge pump wins by default. For simple step-down rails near the input voltage, the LDO is the more natural choice.

Size, Cost, and External Components

Both technologies avoid inductors. An LDO typically needs only two small ceramic capacitors and costs very little. A charge pump needs the input and output capacitors plus one or two flying capacitors, which adds board area and bill-of-materials cost, although the components are still small and cheap. The integrated circuit itself is slightly more complex because of the switch matrix and clock generation. For a single small step-down rail, the LDO solution is usually the smaller and cheaper of the two.

Load Current and Power Level

Charge pumps are typically used at low to moderate currents, up to a few hundred milliamperes, because the switch and capacitor losses grow with current. At higher currents, inductor-based switching converters take over, and LDOs remain competitive only when the voltage difference is tiny. For loads below about 100 mA, both are practical, and the decision comes down to noise and function rather than power handling.

When Each One Wins

A charge pump wins when the required rail is higher than the input, inverted, or otherwise outside the reach of a linear regulator, and the ripple can be tolerated or filtered. An LDO wins when the rail must be quiet, the input is close to the output, and the current is small to moderate. A common compromise is to use a charge pump to create an intermediate rail and then follow it with an LDO that cleans up the ripple, combining the voltage flexibility of the pump with the cleanliness of the linear stage.

Summary

A charge pump can step up, step down, or invert the input, while an LDO can only step down.
LDOs deliver far lower output noise and ripple; charge pumps inherently produce switching ripple.
LDOs are more efficient when the input is close to the desired output; charge pumps are efficient only near their ideal conversion ratio.
Charge pumps are the default choice when a negative or boosted rail is needed without an inductor.
For quiet step-down rails at low current, the LDO is usually the simpler, smaller, and cheaper solution.

Measuring Dropout Voltage: Definitions, Test Setups, and Curves

朱常 — Wed, 04 Nov 2026 02:17:02 +0000

Measuring Dropout Voltage: Definitions, Test Setups, and Curves

ersaelectronics.com

Dropout voltage is the headline parameter of any LDO datasheet, but the number printed on the front page means little unless the designer knows exactly how the manufacturer measured it. Different vendors use slightly different definitions, different load conditions, and different temperature points, and a value taken out of context can lead to headroom mistakes in battery-powered or post-converter designs. This article walks through how dropout is actually measured in the lab, why the definitions differ between manufacturers, how load and temperature change the result, and how to extract and interpret dropout curves for a real design.

Why Definitions Differ

At first glance dropout seems simple: it is the input-to-output differential at which the regulator stops regulating. In practice, manufacturers must choose what "stops regulating" means. A common definition is the differential at which the output voltage has fallen by a fixed percentage, typically two to three percent, below its nominal regulated value. Another common definition is the point at which the internal control loop runs out of headroom and the pass element is fully turned on, even though the output has not yet dropped by a fixed amount. A third definition uses a fixed absolute drop, such as 100 mV below nominal, regardless of the output voltage. Each of these choices produces a slightly different number for the same silicon, which is why comparing two vendors on a single front-page number can be misleading. Always read the fine print on the test conditions.

The Basic Test Setup

Measuring dropout is conceptually straightforward. The regulator is loaded with a constant current source or an electronic load set to the test current. A precision voltmeter measures the output voltage, and another measures the input. The input voltage is then slowly ramped down while both channels are recorded. The dropout point is found where the output begins to deviate from its regulated value. In a production-grade setup the input source is a programmable DC supply with remote sense, the load is an electronic load programmed for constant-current mode, and the measurements are logged on a data acquisition unit or captured on a scope. The input and output capacitors must be the exact values recommended by the datasheet, because changing them can alter loop behavior near dropout and shift the measured point.

Probing and Grounding Details

Dropout measurements are easily corrupted by parasitic voltage drops. The load current flows through the supply wires and the ground return, and any resistance in those paths adds a millivolt-scale error to the measured differential. For this reason the output voltage must be sensed directly at the device pins using Kelvin sense connections, with the force and sense paths kept separate. The ground reference for the voltmeter should be the regulator's own ground pin, not a distant point on the bench. Input ripple from the bench supply should be kept low, because the regulator's PSRR is already degrading as it approaches dropout, and a noisy input can mask the true onset.

Load Dependence

Dropout rises almost linearly with load current in a PMOS or NMOS LDO, because it is dominated by the on-resistance of the pass element. At light load the measured dropout may be only tens of millivolts, while at the rated maximum current it can reach several hundred millivolts. A regulator specified at 300 mV dropout at 1 A may need less than 50 mV at 10 mA, and a design that spends most of its time at light load can safely use much less headroom than the full-load specification suggests. For dynamic loads, the worst case is the peak current, not the average, because the instantaneous dropout must still be met when the load surges.

Temperature Dependence

Silicon on-resistance increases with temperature, typically by a factor of roughly 1.5 to 2 between room temperature and the maximum rated junction temperature. Dropout therefore worsens as the die heats up, and the datasheet's room-temperature number is optimistic. Manufacturers usually specify dropout at both room temperature and at the maximum operating temperature, and the hot number is the one that should drive the design. Self-heating is particularly important in high-current parts: at 500 mA with 300 mV headroom, the part dissipates 150 mW, which by itself can raise the junction temperature by tens of degrees in a small package and push the actual dropout above the cold datasheet value.

Extracting and Using Dropout Curves

The most useful dropout information on a datasheet is the family of curves showing dropout voltage versus load current at several temperatures. To use them, the designer identifies the maximum load current in the application, looks up the dropout at that current and at the maximum expected junction temperature, and adds a design margin, commonly 100 to 300 mV. This gives the minimum input voltage the design can tolerate. For battery-powered systems this minimum input directly sets the cutoff point of the battery and the achievable runtime. For post-converter designs it sets the minimum output of the upstream buck and therefore the system efficiency. When the curves are not supplied, the designer must measure them on the bench, sweeping load current and temperature, because the front-page number alone is not enough.

Summary

Dropout is defined differently across manufacturers, so always read the test conditions before comparing parts.
Measure dropout with a constant-current load, Kelvin sensing, and the datasheet-recommended input and output capacitors.
Dropout rises approximately linearly with load current and increases with temperature because of rising on-resistance.
Use the hot, full-load number for worst-case design, and add a practical margin of a few hundred millivolts.
Dropout curves versus current and temperature are far more useful than a single front-page value, and should be measured if they are not provided.

Reverse Current, the Body Diode, and Output Discharge Features in LDOs

朱常 — Wed, 04 Nov 2026 02:12:24 +0000

Reverse Current, the Body Diode, and Output Discharge Features in LDOs

ersaelectronics.com

Most LDOs are built around a pass transistor that is inherently vulnerable to current flowing in the wrong direction. When the input voltage collapses but the output is held up by a large capacitor, by another regulator, or by a battery, current can flow backward from output to input through the pass element or its parasitic body diode. This reverse current can discharge the output unnecessarily, stress the pass element, back-feed downstream circuits, and even damage the part or the upstream supply. A related set of features concerns what happens to the output when the regulator is disabled: a charged output capacitor must be discharged cleanly before the next startup. This article explains reverse-current paths, protection strategies, OR-ing outputs, and active output discharge.

Where Reverse Current Comes From

In a typical LDO the pass element is a PMOS or NMOS transistor fabricated on the die. A MOSFET has an intrinsic parasitic diode, the body diode, between its source and drain. In normal operation this diode is reverse biased and does not conduct. But if the output voltage rises above the input voltage by more than one diode drop, the body diode becomes forward biased and current flows from output to input regardless of the control loop. This situation arises in several common cases. The input source may be disconnected while the output capacitor remains charged. Another regulator sharing the output may keep the rail up. A battery on the output side may feed back through the rail. An input capacitor may discharge through the regulator into the output. In each case the body diode is the first path, and the loop cannot stop it because it controls the gate, not the diode.

The Consequences of Reverse Current

A small reverse current through the body diode is not always destructive, but it causes problems. It discharges the output capacitor faster than expected, which can matter in systems that rely on the rail to stay up briefly after input loss. It back-feeds the input rail, potentially powering circuits that were supposed to be off, which is a safety issue in medical or industrial equipment. It can lift the input voltage above its rated maximum if the output is held at a higher voltage. In OR-ing applications, reverse current from one output to another fights the other regulator and causes oscillation or excess dissipation. Over time, repeated reverse conduction can stress the pass element and shorten life.

Reverse-Current Protection Structures

Many modern LDOs include internal reverse-current protection. The common approach is to place a second MOSFET in series with the pass element, oriented so that its body diode is in the opposite direction, and to turn it off whenever the output exceeds the input. Some parts use an ideal-diode-like structure that blocks reverse conduction until the loop detects the fault. The datasheet specifies the reverse-current blocking capability, often as a maximum current that can be blocked without damage. Parts without this feature require external protection, typically a Schottky diode in series with the input or output, or an external ideal-diode controller. The tradeoff is that an external protection diode adds its own forward voltage drop, which erodes dropout margin, so a low-forward-voltage Schottky or an active ideal diode is preferred.

OR-ing LDO Outputs

OR-ing two regulator outputs to drive one load is sometimes used for redundancy or for combining different sources. Because each regulator sees the other's output through the load, reverse-current blocking is essential. A simple OR of two LDO outputs with external Schottky diodes works, but the diodes drop voltage and reduce efficiency. Active OR-ing with ideal-diode controllers avoids the drop but adds complexity. The important design rule is that each LDO must either include internal reverse-current blocking or be protected externally, and the ground returns must be arranged so that current cannot circulate between the two regulators through the ground path.

Output Discharge When Disabled

When an LDO is disabled, its output usually falls slowly because the output capacitor must discharge through the load or through a high internal leakage path. In many systems a slow output fall is harmless, but in others it is not. If a processor requires its core supply to fall quickly to a defined state before the next startup, a slow decay can cause a false power-up or violate sequencing. If the output drives a sensor or a switch that must be off within a defined time, a slow decay leaves the circuit partially energized. To address these cases, many LDOs include an internal active discharge switch: a small MOSFET from output to ground that turns on when the regulator is disabled, pulling the output down rapidly. The discharge current is limited, typically to tens or hundreds of milliamps, sized to discharge the recommended output capacitor within a specified time.

Choosing Between Active Discharge and Floating Output

Active discharge is useful, but it is not always desirable. If the output must remain held up by a backup source when the regulator is disabled, an active discharge switch would fight that source and discharge the backup. In such applications the designer selects a part without active discharge, or one where the discharge function can be disabled, so that the output floats when the regulator is off. The choice depends on the system: sequencing and fault-clearing applications benefit from active discharge, battery-hold and backup applications require a floating output.

Practical Checks

When designing with reverse-current and discharge behavior in mind, several checks prevent surprises. First, identify every way the output can be held above the input: large capacitors, backup batteries, other regulators, and charged upstream nodes. Second, confirm whether the chosen LDO blocks reverse current internally, or add external protection. Third, decide whether the output must fall quickly when disabled, and select active discharge accordingly. Fourth, calculate the discharge time with the actual output capacitor and the rated discharge current, and confirm it meets the system requirement. Fifth, check the ground return path, because reverse current can also flow through shared ground traces even when the pass element is blocked.

Summary

The intrinsic body diode of the pass transistor conducts reverse current when the output rises above the input, regardless of the control loop.
Reverse current discharges output capacitors, back-feeds inputs, and can stress the pass element; it must be blocked in many systems.
Choose an LDO with internal reverse-current protection, or add an external ideal diode or low-forward-voltage Schottky.
OR-ing LDO outputs requires reverse-current blocking on each regulator and careful ground-return design.
Active discharge switches pull the output down quickly when the regulator is disabled, which is useful for sequencing and fault clearing.
If the output must be held up by a backup source when disabled, choose a part without active discharge or with the function disabled.
Identify all reverse-current paths, including through ground, before finalizing the design.

Protection Features in LDO Regulators

朱常 — Tue, 03 Nov 2026 07:06:12 +0000

Protection Features in LDO Regulators

ersaelectronics.com

A regulator that works perfectly under normal conditions can be destroyed in an instant by a short circuit, an input surge, or a stalled load. Modern LDOs therefore include a family of built-in protection functions that turn a fragile power device into one that survives faults. Understanding how these protections behave, and how the device recovers after a fault, is important for designing systems that stay up and safe rather than simply failing. This article covers overcurrent, short-circuit, and over-temperature protection, the difference between constant-current limiting and foldback, and the recovery behavior a designer should expect.

Why Protection Is Needed

The pass element in an LDO carries the full load current. If the output is shorted to ground, the entire input voltage appears across that single transistor, and the resulting power can destroy it in milliseconds unless the loop or a dedicated circuit intervenes. Similarly, an input voltage spike or an overheated die can damage the reference and the amplifier. Protection circuits exist to cap the stress the silicon sees, even under abnormal conditions, so that the device survives the fault without external fuses or sensing components. These features are nearly free in an integrated part, and they are expected in any industrial or automotive-grade design.

Overcurrent and Current Limiting

The most basic protection is current limiting. When the load current exceeds a threshold, the regulator stops regulating voltage and instead holds the current at a fixed ceiling. The output voltage collapses under the short, but the current, and therefore the stress on the pass element, is bounded. In a simple constant-current limiter, the current stays at the limit even while the output is shorted, which means the power dissipated during a sustained short is Vin multiplied by the current limit. With a high input voltage this can still be large, which is where foldback limiting comes in.

Foldback Current Limiting

Foldback, or current-foldback, limiting reduces the short-circuit current below the current-limit level as the output voltage approaches zero. The idea is that once the output is shorted, the regulator does not need to supply the full current limit, and backing the current down cuts the power dissipated in the fault. This allows smaller packages to survive a continuous short to a high-voltage input. The tradeoff is a minimum load requirement: because the limit folds down at low output voltage, a foldback part may struggle to start a heavy capacitive load, and the design must ensure the output can latch out of the foldback region. Datasheets specify both the current limit at nominal output and the lower short-circuit current.

Over-Temperature Protection

Over-temperature, or thermal, protection monitors the die temperature. If the junction exceeds a threshold, commonly in the range of 150 to 170 degrees C, the device shuts down the pass element to prevent damage. It then restarts automatically once the die cools by a hysteresis band, often 10 to 20 degrees. This protection triggers during overloads, shorts, or simply when the ambient is too hot for the dissipation. It is the safety net that catches conditions the designer did not anticipate, but a system that repeatedly cycles through thermal shutdown is over-stressed and should be redesigned with more copper or lower dissipation.

Input Reverse-Voltage and Other Protection

Beyond current and temperature, many parts include additional fault handling. Reverse-voltage protection prevents damage if the input polarity is reversed, either internally or with an external diode. Input overvoltage protection clamps or blocks transients above the rating. Some parts include reverse-current blocking, so that current cannot flow backward from the output capacitor into the input when the input is removed. Enable-logic protection ensures the part stays off until the supply is valid. Which of these are present depends on the part and its grade; consumer parts may omit them, while industrial and automotive parts usually specify them in detail.

Fault Behavior and Recovery

It is important to understand what the circuit looks like to the rest of the system during a fault. Under a current-limited short, the output sits near zero while the regulator heats up; if the dissipation is high, thermal shutdown may cycle the part on and off. When the short is removed, the output recovers and the loop returns to regulation, though the output capacitor must recharge, which can produce a brief overshoot. The designer should confirm that the rest of the system tolerates this recovered state without a reset. For critical loads, a power-good flag, where available, lets the downstream logic know that the rail has dropped out and recovered, and that a controlled restart may be needed.

Summary

LDOs include internal protection so that shorts, overloads, and over-temperature do not destroy the pass element.
Constant-current limiting caps the fault current; foldback limiting reduces it further at shorted output to cut power dissipation.
Thermal shutdown turns the device off if the junction overheats and restarts automatically after cooling.
Additional protections may include reverse-voltage, input-overvoltage, and reverse-current blocking.
Recovery after a fault returns the output to regulation, but the behavior should be understood, and power-good flags used where the system requires controlled restart.

Thermal Design and Junction Temperature in LDOs

朱常 — Tue, 03 Nov 2026 07:05:41 +0000

Thermal Design and Junction Temperature in LDOs

ersaelectronics.com

An LDO turns the voltage difference between its input and output into heat inside the package. That heat raises the die temperature, and if the die gets too hot the device either shuts down to protect itself or, in the worst case, suffers accelerated aging. Thermal design is therefore not an afterthought for a linear regulator; it is the calculation that determines whether the part can deliver the rated current at all. This article explains how power dissipation becomes heat, how to read thermal resistance, how to estimate junction temperature, and how the PCB and package spread the heat.

Where the Heat Comes From

The power dissipated by an LDO is, to a first approximation, the input-to-output voltage difference multiplied by the load current, plus a small term from its own quiescent current. For example, dropping 5 V to 3.3 V at 500 mA dissipates about 0.85 W, and dropping 12 V to 3.3 V at 500 mA dissipates over 4 W. Unlike a switching converter, which stores and transfers energy efficiently, a linear regulator burns this power continuously as long as the load is on. This is why LDOs are chosen for small voltage differences: the smaller Vin minus Vout, the less heat. The quiescent term is usually negligible at moderate loads, but at light load it becomes part of the total dissipation.

Thermal Resistance: The Path From Die to Ambient

Heat flows from the silicon junction, through the die attach, the package, and the board, to the surrounding air. This path has an effective thermal resistance, expressed in degrees Celsius per watt. The two parameters on a datasheet are theta-JA, the resistance from junction to ambient, and theta-JC, the resistance from junction to the outside of the package case. Theta-JA is the number a board designer usually uses, because the part sits on a PCB rather than on a perfect heatsink. Theta-JC is relevant only when a real heatsink or a well-coupled metal surface is attached. Small SOT-23 or DFN packages have relatively high theta-JA, on the order of 100 to 200 degrees C per watt, while larger packages or those with an exposed pad can be several times lower.

Calculating Junction Temperature

The calculation is a direct analogy to Ohm's law. The junction temperature equals the ambient temperature plus the power dissipation multiplied by the thermal resistance: Tj equals Ta plus P times theta-JA. For example, a part dissipating 0.8 W with a theta-JA of 120 degrees C per watt, in a 50 degrees C ambient, reaches about 146 degrees C. Most silicon is rated for a maximum junction temperature of 125 or 150 degrees C, so this example is already above the safe limit and would need either a lower dissipation, a better package, or more copper on the board. The designer should always perform this calculation at worst case: maximum input voltage, maximum load current, and maximum ambient temperature, including internal enclosure heating.

Why the PCB Matters

The theta-JA quoted on a datasheet is almost always measured on a standard test board with a defined amount of copper. In a real product, the copper area connected to the thermal pad, the ground plane underneath, and the number of vias all change the actual resistance. A package with an exposed thermal pad relies entirely on the PCB copper to drain heat; with no copper it behaves like a tiny package. Practically, enlarging the copper area around the device, tying it to a ground plane, and adding multiple vias can halve the effective thermal resistance. This is why package choice and layout go together: a small DFN with a good board can outperform a larger package on a poor one.

Heatsinking and Derating

When the dissipation exceeds what the PCB can handle, the options are to reduce the dissipation or to add thermal help. Reducing the voltage difference, for example by using a lower input rail or a switching pre-regulator, is usually the most effective step. If the difference cannot be reduced, a larger package with lower theta-JA, an exposed pad, or a bolted heatsink may be needed. At high ambient temperatures, the allowable dissipation shrinks linearly: as the ambient approaches the maximum allowed junction temperature, the part must be derated. Datasheets provide a derating curve that plots maximum allowable dissipation against ambient temperature, and that curve is the practical limit.

Thermal Protection Behavior

Nearly all LDOs include internal thermal shutdown: if the junction exceeds a threshold, typically around 150 to 170 degrees C, the part turns off to protect itself, and it restarts when the die cools by some hysteresis, often tens of degrees. This prevents destructive failure during a fault, but repeated thermal cycling is not healthy for the system. A design that relies on thermal shutdown during normal operation is a design that is too hot, and it should be reworked. Thermal shutdown is a fault backstop, not an operating mode.

Summary

An LDO dissipates roughly the input-to-output voltage difference times the load current as heat.
Junction temperature is estimated as ambient temperature plus dissipation times the thermal resistance theta-JA.
The PCB copper, ground plane, and vias are major parts of the heat path, especially for exposed-pad packages.
Design worst case: maximum Vin, maximum load, and maximum ambient, and respect the derating curve.
Thermal shutdown protects the device but signals an over-heated design; reducing Vin minus Vout is usually the best cure.

Stability and the Output Capacitor ESR in LDOs

朱常 — Tue, 03 Nov 2026 07:05:12 +0000

Stability and the Output Capacitor ESR in LDOs

ersaelectronics.com

A regulator that is stable on the bench can oscillate in production, and the most common reason is the output capacitor. Unlike switching converters, which are compensated internally, many LDOs rely on the equivalent series resistance, or ESR, of the output capacitor to provide a phase boost that stabilizes the control loop. Choose the wrong capacitor and the loop can ring, oscillate, or drift out of regulation. This article explains the stability theory behind LDOs, the ESR zero, why modern ceramic capacitors can destabilize older parts, and the compensation approaches used today.

Why an LDO Needs Compensation

An LDO is a feedback loop: the output is sensed, compared to a reference, amplified, and used to drive the pass element. Any feedback loop with gain must have enough phase margin to remain stable rather than ringing or oscillating. The internal error amplifier and the output stage introduce poles, and the output capacitor and its ESR add more. If the total phase lag at the frequency where the loop gain crosses unity reaches 360 degrees, the loop turns into an oscillator. Phase margin, the number of degrees by which the phase lag stays short of that point, is the figure of merit; a comfortable design targets on the order of 45 to 60 degrees.

The Poles and the ESR Zero

The loop of a typical LDO contains two internal poles plus one pole set externally by the output capacitor. The output capacitor forms a pole with the output resistance of the regulator, which tends to roll off the loop gain and add phase lag. The capacitor's ESR, however, creates a zero. At frequencies above the point set by the capacitance and its ESR, the capacitor's impedance stops falling and flattens to the value of the ESR, effectively adding phase lead. This ESR zero is a deliberate stabilizing element: it injects phase boost right where the loop needs it, keeping the phase margin healthy. The catch is that the zero only lands in the useful frequency band if the ESR is neither too high nor too low.

The ESR Window

Traditional LDOs therefore specify a range of allowed output-capacitor ESR, often from roughly 10 milliohms to a few ohms. Inside that window, the ESR zero sits where it helps. If the ESR is too high, the zero moves to low frequency, the loop becomes sluggish and may oscillate. If the ESR is too low, the zero moves to high frequency, out of the band where it is needed, and the loop can become unstable or ring on transients. This is the root of the classic ceramic-capacitor problem.

Why Ceramic Capacitors Can Cause Trouble

Modern multilayer ceramic capacitors have very low ESR, often well under 10 milliohms. On an older LDO designed to need the ESR zero, such a capacitor pushes the stabilizing zero to a very high frequency where it does the loop no good, leaving insufficient phase margin. The symptom is usually high-frequency oscillation on the output, audible noise, or excessive ringing after a load transient, even though the DC output looks fine. The fix historically was to use a capacitor with a controlled ESR, such as a tantalum or aluminum-polymer part, or to add a small resistor in series with the ceramic. This is why datasheets from that era give detailed ESR ranges and warn against straight ceramics.

Modern Compensation Approaches

Designers responded by eliminating the dependence on external ESR. Several internal approaches are common:

Internal compensation adds an internal zero-pair network inside the die, so the loop remains stable regardless of the output capacitor's ESR.
Feedforward compensation uses a small feedforward capacitor around the feedback divider to inject phase lead.
Very-low-ESR-stable parts are specified specifically to work with ceramic capacitors over a wide range, typically 1 uF to 22 uF.
Some parts are stable with no output capacitor at all, though at the cost of transient performance.

The result is that most contemporary LDOs are designed for ceramic capacitors and no longer impose an ESR window, but older parts and high-current parts still do, and the datasheet must be checked.

Practical Stability Checks

To avoid stability problems in a design:

Read the recommended output-capacitor range and any ESR window on the datasheet, and stay inside it across temperature and tolerance.
Check the capacitor's ESR over the temperature range, because ceramic ESR rises at cold temperature and can move in or out of the window.
Verify the dielectric and value, because ceramic capacitance drops with DC bias; a 10 uF rated capacitor may act like 3 uF at operating voltage.
Examine the output on an oscilloscope during a load transient; clean recovery without ringing is the practical sign of adequate margin.
If oscillation appears, move within the allowed ESR range rather than changing the capacitor value blindly.

Summary

An LDO is a feedback loop that needs enough phase margin, typically 45 to 60 degrees, to avoid oscillation.
The output capacitor's ESR creates a stabilizing zero; too high or too low an ESR moves that zero out of the useful band.
Very-low-ESR ceramic capacitors can destabilize older LDOs that were designed to rely on a minimum ESR.
Modern internally compensated or ESR-stable LDOs remove this dependence and work directly with ceramics.
Always follow the datasheet's recommended capacitor range and verify transient recovery on the bench.