DEV Community: AtlasPCBEngineering

EV Group Demonstrates 450nm Pitch Hybrid Bonding at ECTC 2026: 98% Yield Across 20M Interconnects

AtlasPCBEngineering — Wed, 27 May 2026 06:17:30 +0000

EV Group Showcases 450nm Pitch Hybrid Bonding and Layer Transfer at ECTC 2026

EV Group (EVG), the Austrian semiconductor equipment manufacturer, has demonstrated a breakthrough at ECTC 2026: 450nm pitch Cu-Cu hybrid bonding with 98% yield across 20 million interconnects — a critical milestone for ultra-dense 3D chip integration powering next-generation AI processors.

Key Technologies Demonstrated

Ultra-Fine Pitch Hybrid Bonding (450nm)

Co-authored with Applied Materials:

450nm Cu-Cu interconnect pitch — among the finest demonstrated at production scale
98% yield across 20 million interconnects — proving manufacturing viability
Wafer-to-wafer process using EVG GEMINI® FB production bonding systems

This pitch density enables significantly higher bandwidth die-to-die interfaces than current 2-3μm pitch used in today's HBM stacks.

300nm Pitch Process Integration

A separate paper presents:

300nm pitch hybrid bonding with SiCN passivation
50nm overlay accuracy
Fine-grain Cu metallurgy with comprehensive reliability assessment
Demonstrates readiness for upcoming HBM5/6 generations

IR Layer Transfer (LayerRelease™)

Fabrication and transfer of fine-pitch RDL using Si temporary carriers
IR laser release enabling non-destructive layer separation
Application: heterogeneous integration of pre-fabricated redistribution layers

Maskless Lithography (LITHOSCALE® XT)

Digital lithography on 310×310mm² panel substrates
High aspect ratio Cu pillar applications
Eliminates mask tooling cost for advanced substrate manufacturing

Seven Technical Sessions

EVG's conference program spans the full range of heterogeneous integration — from professional development courses on hybrid bonding fundamentals to frontier research on epitaxial ruthenium layer transfer for single-crystal interconnects.

Why This Matters for PCB Engineers

As chips integrate more dies through hybrid bonding, PCB substrates must support:

Higher I/O density → finer pitch BGA arrays
Higher power density → improved thermal via arrays
Higher signal frequency → ultra-low-loss materials
Tighter warpage control → precision lamination

Originally published at AtlasPCB

Source: EV Group Press Release, May 19, 2026; IEEE ECTC 2026 Technical Program

ECTC 2026 Opens: Record Papers on AI Chip Packaging Drive Substrate Technology Forward

AtlasPCBEngineering — Wed, 27 May 2026 06:17:09 +0000

ECTC 2026 Opens in Orlando: Record Papers on AI Chip Packaging Drive Substrate Technology Forward

The 76th annual IEEE Electronic Components and Technology Conference (ECTC 2026) opened on May 26, 2026 in Orlando, Florida, bringing together more than 2,000 scientists and engineers. This year features approximately 450 technical papers — with an unprecedented concentration on technologies enabling AI accelerator packaging.

AI Packaging Dominates the Technical Program

The influence of AI hardware demand is unmistakable:

Hybrid bonding sessions: Multiple papers on sub-micron pitch Cu-Cu bonding for die stacking — the critical technology for HBM4/5 memory
Advanced substrate materials: PFAS-free dielectrics, glass core substrates, and low-loss organics
Chiplet integration: Heterogeneous integration papers outnumber traditional monolithic packaging for the first time
Thermal solutions: Novel TIM materials and 3D cooling for 700W+ AI accelerator TDPs

Breakthrough Result: 450nm Pitch Hybrid Bonding

Applied Materials and EV Group demonstrated 450nm pitch Cu-Cu hybrid bonding achieving 98% yield across 20 million interconnects — roughly 4× finer than current HBM production bonding. This enables:

Multi-terabyte/second die-to-die bandwidth
Dramatically reduced interposer size
New 3D stacking architectures for next-gen AI chips

Key Industry Implications

As AI chip packages integrate more dies through fine-pitch bonding, organic PCB substrates must support:

BGA pitch migration: Moving from 1.0mm toward 0.5mm pitch
Trace/space requirements: ≤ 30/30μm on substrate surface layers
Layer count escalation: 14-20 layer substrates for AI accelerator sockets
Thermal management: Copper coins and high-density thermal via arrays for 700W+ packages

The AI Packaging Arms Race

ECTC 2026 occurs against unprecedented investment in AI hardware:

TSMC CoWoS capacity expanded 11× year-over-year
Global substrate market projected to reach $22B by 2027
Every major OSAT investing in hybrid bonding capability

Originally published at AtlasPCB

Sources: IEEE ECTC 2026 Program, EV Group Press Release, Fujifilm Announcement, May 2026

Solder TIMs for AI Chip Thermal Management: 86 W/mK Indium Solutions at ECTC 2026

AtlasPCBEngineering — Tue, 26 May 2026 06:18:32 +0000

The AI Thermal Crisis and Why Polymer TIMs Are Failing

Every generation of AI accelerators pushes thermal design power (TDP) higher. NVIDIA's B200 at 1000W, AMD's MI400 series approaching 800W, and Intel's Gaudi 3 at 600W — all concentrated in die areas under 900mm². The resulting heat flux exceeds 100 W/cm², pushing junction temperatures dangerously close to silicon's reliability ceiling.

At the 76th IEEE Electronic Components and Technology Conference (ECTC 2026, May 26-29, Orlando), Indium Corporation presented breakthrough research on solder thermal interface materials (sTIMs) that may reshape how the industry approaches AI chip packaging.

From Grease to Metallurgical Bonds: The sTIM Advantage

TIM Type	Conductivity (W/mK)	Typical Resistance
Thermal grease	2-8	0.03-0.25 °C·cm²/W
Phase change	3-6	0.025-0.10 °C·cm²/W
Indium sTIM	86	0.003-0.009 °C·cm²/W

The 86 W/mK conductivity of indium sTIMs provides a 10-40× improvement in thermal resistance versus polymer alternatives. For an 800mm² die at 1000W:

Polymer TIM (5 W/mK): ΔT ≈ 12.5°C across the interface
Indium sTIM (86 W/mK): ΔT ≈ 0.7°C across the interface

That 11.8°C difference translates directly to either lower junction temperature (longer chip life) or higher allowable TDP (more compute performance).

Why Indium?

Indium has unique properties ideal for TIM applications:

Low melting point: 156.6°C (compatible with multi-reflow assembly)
High thermal conductivity: 86 W/mK
Exceptional ductility: Absorbs CTE mismatch strain without cracking
Self-healing: Indium cold-welds under compression
Low elastic modulus: 11 GPa (soft, doesn't stress the die)

ECTC 2026 Innovation: Vacuum Formic Acid Reflow

The research presented solves three problems simultaneously:

1. Oxide Removal Without Flux

Formic acid vapor reduces copper and indium surface oxides at >150°C, eliminating flux residue trapped under the die.

2. Vacuum Void Elimination

Reflowing under vacuum (<100 Pa) prevents gas entrapment. The research demonstrates consistent voiding below 2% across the full 800mm² bond area.

3. Multi-Reflow Compatibility

AI packages undergo 3+ reflow cycles during assembly. The process maintains void levels through multiple thermal cycles.

Results

Voiding: <2% consistently across 20+ samples
Thermal resistance: 0.004 °C·cm²/W
Reliability: Survived 1000 thermal cycles (-40 to +125°C)
Scalability: Validated for packages up to 2500mm²

PCB Substrate Design Implications

Increased Thermal Cycling Stress

Traditional polymer TIMs absorb CTE mismatch as a compliant layer. Solder TIMs create rigid metallurgical connections, transferring more stress to:

BGA solder joints
Package substrate vias
PCB power delivery structures

Substrate designers must respond with:

Low-CTE core materials (2-4 ppm/°C)
Increased BGA pad sizes
Enhanced underfill coverage
Redundant via connections

Power Delivery for 700W+ Processors

AI accelerators draw 500-800A at sub-1V core voltage. PCB substrates must provide:

2oz+ copper power planes
Hundreds of parallel power vias
Embedded decoupling capacitors
Copper-filled microvias (not hollow barrels)

Via Reliability Requirements

Data center servers operate 5+ years with 1000+ thermal cycles:

Maximum aspect ratio 6:1 for power vias
Copper-filled vias for minimum resistance
Stacked microvia structures for shorter segments
No single via carrying more than 5A

Industry Trajectory

Near-Term (2026-2027): sTIMs adopted for highest-performance AI accelerators (>800W)

Mid-Term (2028-2029): Glass core substrates provide 3.2 ppm/°C CTE match; 2000W+ multi-chip modules

Long-Term (2030+): Silicon/glass interposers replace organic substrates for top-tier AI

Practical Takeaways for Hardware Engineers

If designing AI accelerator boards: Specify substrates with z-axis CTE below 15 ppm/°C
If specifying thermal solutions: Evaluate sTIMs for any component exceeding 50 W/cm²
If manufacturing PCBs for AI packages: Prepare for tighter flatness requirements (<15µm warpage)
If selecting assembly processes: Vacuum reflow capabilities will become differentiating

Source: IEEE ECTC 2026 Technical Program; Indium Corporation research presentation (May 27, 2026)

🔗 More on AI hardware PCB design: AtlasPCB Blog | AI Hardware Thermal Management Guide | Get a Quote

U.S. Senate Introduces PCB Reshoring Bill: 25% Tax Credit for Domestic Manufacturing

AtlasPCBEngineering — Tue, 26 May 2026 06:17:53 +0000

Senate Bill S.4569 Targets PCB Industry Revival

The Printed Circuit Board Association of America (PCBAA) announced on May 25, 2026, the introduction of a bipartisan Senate bill focused on reshoring America's printed circuit board manufacturing capability. Senators Ruben Gallego (D-AZ) and Jim Justice (R-WV) introduced S.4569, the Protecting Circuit Boards and Substrates Act, which provides a 25% tax credit for the purchase or acquisition of American-made PCBs.

The legislation is a companion to H.R. 3597 in the House, which includes both the tax credit and a $3 billion grant program to directly support U.S. PCB manufacturers with capital expenditure and capacity expansion.

Three Decades of Decline

The numbers tell a stark story: over the past 30 years, the U.S. share of global PCB production has collapsed from 30% to just 4%. This offshoring accelerated in the 2000s as heavily subsidized Asian manufacturers — particularly in China, Taiwan, Japan, and South Korea — made domestic U.S. production economically noncompetitive.

"These two bills impact both national and economic security. Every semiconductor needs a PCB to function." — David Schild, Executive Director of PCBAA

The legislation follows the model of semiconductor industry policy (CHIPS Act) that successfully incentivized over $200 billion in private investment for U.S. fab construction. PCBAA argues that PCBs represent the next critical link in the electronics supply chain requiring similar intervention.

What the Bill Means for the Industry

For U.S. PCB Manufacturers

25% tax credit on revenues from domestically manufactured PCBs
$3 billion in grants for facility upgrades, equipment, and expansion
Potential to attract private investment similar to CHIPS Act multiplier effect

For OEMs and Defense Primes

Reduced dependency on vulnerable trans-Pacific supply chains
Compliance pathway for ITAR and security-clearance projects requiring U.S.-origin PCBs
Potential cost equalization between domestic and offshore sources

For the Global Supply Chain

Signal that PCB manufacturing is joining semiconductors as strategic infrastructure
May prompt allied nations (EU, Japan, South Korea) to develop similar programs
Could accelerate high-complexity PCB technology development on U.S. soil

Defense and National Security Context

The bill's bipartisan sponsorship reflects growing concern about electronics supply chain vulnerabilities. Current U.S. defense systems rely heavily on Asian-manufactured PCBs — a dependency that the Department of Defense has flagged as a critical vulnerability.

The U.S. currently lacks domestic capability for the most advanced PCB technologies:

HDI microvias: Limited U.S. manufacturers capable of 3+N+3 structures
IC substrates: Zero domestic production of ABF substrate for advanced packaging
Ultra-high layer count: Few facilities capable of 40+ layer military-grade boards

The $3 billion grant program could fund equipment upgrades to close these capability gaps.

What This Means for PCB Buyers

For companies currently sourcing PCBs from Asia, the legislation creates several strategic considerations:

Dual-sourcing: Qualifying domestic suppliers now may provide advantage when tax credits activate
Lead time resilience: U.S. manufacturing eliminates 3-4 week shipping transit for urgent orders
IP protection: Domestic manufacturing reduces exposure to technology transfer risks
Compliance: Government and defense contracts increasingly require domestic origin documentation

Whether the bill passes in its current form or evolves through committee, the direction is clear: U.S. policy is moving toward incentivizing domestic PCB production.

Source: PCB Directory (May 25, 2026), PCBAA, Congress.gov

📋 For more PCB industry analysis and engineering guides, visit AtlasPCB Blog | Need complex PCBs manufactured? Get a quote

Advanced Packaging Revolution: How Chiplets and 2.5D Integration Are Reshaping PCB Substrates

AtlasPCBEngineering — Mon, 25 May 2026 10:56:01 +0000

The monolithic die is dead. Long live the chiplet.

If you've been tracking semiconductor roadmaps in 2026, you've noticed something fundamental: AMD, Intel, NVIDIA, Apple, and Qualcomm have all committed to disaggregated chiplet architectures. But here's what most coverage misses—the revolution isn't just happening inside the package. It's completely transforming the PCB substrates these packages mount to.

As someone who works at the intersection of PCB manufacturing and advanced packaging, I've watched this transition accelerate dramatically. Let me break down why this matters for hardware engineers.

Why Chiplets Change Everything Below the Package

Chiplet packages aren't just bigger—they're fundamentally more demanding. When you disaggregate a monolithic SoC into multiple functional tiles (compute, I/O, memory controller, etc.), the package needs to route signals between chiplets AND between the package and the PCB. The result? Ball pitches dropping to 0.4mm and below, with significantly higher pin counts.

This cascades directly into the PCB:

Escape routing complexity explodes: HDI substrates with stacked microvias become mandatory, not optional
Thermal budgets get insane: Chiplet packages regularly exceed 500W TDP. Your PCB needs thermal via arrays (0.3mm vias on 1.0mm pitch), dedicated copper spreading planes, and low-CTE materials to manage thermomechanical stress
Signal integrity demands tighten: While UCIe stays inside the package, the I/O signals hitting the PCB (PCIe Gen 6, CXL 3.0, DDR5/6) require controlled impedance (85–100Ω ±7%), via stub elimination, and ultra-low-loss dielectrics (Df <0.003)

The Emerging "Bridge" Substrate Category

Here's where it gets really interesting. A new substrate category is emerging that sits between traditional PCBs and IC substrates:

Attribute	Traditional PCB	Bridge Substrate	IC Substrate
Line/space	≥50/50µm	15–50µm	2–15µm
Via diameter	≥75µm	30–75µm	10–30µm
Process	Subtractive	SAP/mSAP	SAP
Panel size	18"×24"	12"×18"	6"×8"

PCB manufacturers capable of mSAP (modified Semi-Additive Process) are positioning themselves in this sweet spot. It's essentially semiconductor-class precision on PCB-class panel sizes.

2.5D Packaging: The Interposer Challenge

2.5D packaging uses silicon or organic interposers between chiplets and the PCB. The organic interposer alone requires 2/2µm to 10/10µm line/space with 20–50µm via diameters—specs that would have been unthinkable for PCB fabs five years ago.

But it still connects to a conventional PCB through BGA, and that PCB must handle all the routing to memory, power regulators, and board-level components. The complexity doesn't disappear—it redistributes.

Industry Is Betting Big

The investment numbers tell the story:

Japan (Ibiden, Shinko): $2B+ in high-density substrate capacity
Taiwan (Unimicron, AT&S): Expanding mSAP-capable production lines
South Korea (Samsung Electro-Mechanics): Scaling substrate production
China: Aggressive domestic capability development for chiplet substrates

What This Means for Your Next Design

If you're designing boards that host chiplet packages, plan for:

More routing layers — even if your overall system complexity hasn't changed, escape routing from high-density BGA requires additional layers
Stricter material specs — low-loss, dimensionally stable laminates are now mandatory
Earlier DFM engagement — tight tolerances demand collaboration between IC package designers, PCB designers, and fabricators from day one
Hybrid manufacturing zones — some boards may need both traditional PCB areas and mSAP fine-line areas on the same panel

The chiplet revolution isn't just a semiconductor story. It's fundamentally reshaping what we expect from PCB substrates—and the manufacturers who invest in fine-line imaging and mSAP capabilities now will be the ones serving the next generation of AI and HPC hardware.

The advanced packaging transition is one of the most significant shifts in electronics manufacturing in decades. The boundary between "PCB" and "package substrate" is blurring fast.

Glass Core Substrates for AI Packaging: How Intel's Clearwater Forest Changes the PCB Substrate Roadmap

AtlasPCBEngineering — Mon, 25 May 2026 06:21:58 +0000

The Organic Substrate Wall

For two decades, Ajinomoto Build-up Film (ABF) substrates have been the foundation of advanced semiconductor packaging. The laminate-based approach — layer upon layer of resin-coated copper foil, mechanically drilled and chemically etched — scaled elegantly from flip-chip packages to today's complex multi-die architectures.

But organic substrates have hit a physics wall. As AI accelerators grew larger and more power-dense, three fundamental limitations emerged:

Warpage: Organic materials (CTE 12-17 ppm/°C) expand and contract differently than silicon (CTE 3.1 ppm/°C). At package sizes above 70×70mm, this CTE mismatch creates warpage that prevents reliable flip-chip bonding.
Interconnect density: Standard ABF processes achieve minimum line/space of 8/8 µm in production. AI chiplet architectures require 2/2 µm for die-to-die communication — a 4× density gap.
Signal integrity: At 224G PAM4 signaling speeds emerging in next-generation AI networks, organic dielectric loss tangent (Df 0.003-0.008) becomes a bandwidth limiter. Glass offers Df <0.001 across relevant frequencies.

Intel's decision to bring glass substrates into high-volume manufacturing for Clearwater Forest wasn't incremental improvement — it was an acknowledgment that organic substrates cannot support the AI hardware roadmap beyond current generation.

Intel Clearwater Forest: First HVM Glass Substrate Product

Announced at CES 2026 and entering production in January 2026, Intel's Xeon 6+ "Clearwater Forest" processor represents the first commercial IC product fabricated on glass core substrates at high volume.

Technical Specifications

Die: Multiple chiplets on Intel 18A process
Package size: >80mm × 80mm (beyond organic warpage limit)
Substrate: Glass core with build-up redistribution layers
Interconnect: Through-Glass Vias (TGV) at 50µm pitch
Line/space: 2/2 µm (vs. 8/8 µm on latest organic ABF)
Layers: 10+ redistribution layers on glass core
CTE match: Glass core 3.2 ppm/°C vs. silicon 3.1 ppm/°C

Performance Benefits Demonstrated

Parameter	Organic ABF (Sapphire Rapids)	Glass Core (Clearwater Forest)
Maximum package size	70×70mm (warpage-limited)	>100×100mm (no practical limit)
I/O density	500 bump/mm²	2,500+ bump/mm²
Power delivery resistance	1.0 mΩ typical	0.4 mΩ typical
Signal loss at 56 GHz	-2.5 dB/cm	-0.8 dB/cm
Warpage at reflow	100-300 µm	<30 µm
Die-to-die bandwidth	16 Tbps (limited by pitch)	40+ Tbps

How Glass Substrates Are Made

Glass substrate manufacturing is fundamentally different from organic PCB fabrication:

Step 1: Glass Panel Preparation

Starting material: High-purity glass panels (Gen 3.5 display glass or specialty borosilicate)
Thickness: 300-500 µm (vs. 60-100 µm for ABF core)
CTE engineered via composition: adjustable from 3-8 ppm/°C
Surface preparation: Chemical mechanical polish (CMP) to <1nm roughness

Step 2: Through-Glass Via (TGV) Formation

Laser-induced deep etching: Ultrafast laser creates modification tracks
Chemical etch: HF-based wet etch selectively removes laser-modified glass
Result: Vias at 30-50 µm pitch (vs. 200-300 µm for organic PTH)
Aspect ratio: Up to 20:1 achievable

Step 3: Metallization

Seed layer: PVD sputtered TiW/Cu (vs. electroless Cu for organic)
Pattern plating: Semi-additive process (SAP) at 2/2 µm L/S
Via fill: Electroplated copper fills TGVs from bottom-up
Planarization: CMP produces atomically flat surface for next layer

Step 4: Build-Up Layers

Dielectric: Photo-definable polyimide or inorganic SiO₂ (vs. ABF resin)
Layer count: 6-12 redistribution layers built on each side of glass core
Registration: Lithographic alignment <±1 µm (vs. ±10 µm for organic lamination)

Step 5: Bumping and Singulation

UBM (Under-Bump Metallurgy): Sputtered multi-layer for flip-chip or micro-bump
Singulation: Laser or mechanical dicing of glass panel into individual substrates
Final test: Electrical probing of all interconnects

Why Glass Matters for AI Specifically

The connection between glass substrates and AI hardware is direct and structural:

Power Delivery

AI accelerators consume 500-1000W per package. Power must be delivered through the substrate with minimal resistance to avoid voltage droop during transient workloads. Glass substrates enable:

Thicker, wider redistribution layer traces (lower resistance)
More power/ground via columns (lower inductance)
Better planarity = more uniform bump contact = lower contact resistance

The cumulative effect: 40-60% reduction in package-level power delivery impedance, which translates directly to higher clock frequencies and wider voltage margins.

Chiplet Architecture Support

Modern AI processors (NVIDIA Blackwell, AMD MI400, Intel Clearwater Forest) use multi-chiplet designs where 4-12 compute dies communicate on a shared substrate. These die-to-die links require:

Extremely fine pitch (36-55µm bump pitch between chiplets)
Very flat substrate (warpage <30µm for reliable thermocompression bonding)
Low-loss interconnect (die-to-die links at 16-32 Gbps per lane)

Organic substrates cannot maintain flatness at the package sizes these multi-chiplet designs require. Glass solves this geometrically — matching silicon's thermal expansion eliminates the warpage that prevents scaling.

Bandwidth Density

AI training workloads are memory-bandwidth-limited. HBM4 memory stacks communicate with the processor through thousands of parallel lanes at 8-16 Gbps each. The substrate interconnect density directly limits how much memory bandwidth can reach the compute die:

Organic: ~500 connections/mm² → limited to 4-6 HBM stacks
Glass: ~2,500 connections/mm² → supports 8-12+ HBM stacks per package

More HBM stacks per package = more memory bandwidth = faster training. Glass substrates are literally a prerequisite for next-generation AI training hardware performance scaling.

The Competitive Landscape

Intel: First Mover Advantage

Intel's glass substrate program (announced 2023, HVM 2026) gives them a 2-3 year lead over competitors:

Proprietary TGV formation process
Integrated panel-level manufacturing in their Advanced Packaging facility
Clearwater Forest proves production viability — no longer a research project

Chinese Players Racing to Catch Up

As reported by ETNews and IC&PCB Union, Chinese companies are accelerating glass substrate investment:

Visionox: Display maker pivoting to glass substrates, leveraging existing glass handling and lithography expertise. RMB 5 billion investment program announced for 2026, targeting both display and semiconductor substrate applications.

AKM Meadville: Leading Chinese HDI substrate supplier has established a prototype glass substrate pilot line. Their existing dominance in organic IC substrates provides the customer relationships needed to transition designs to glass.

WG Tech / TGV Tech: Subsidiary focused exclusively on Through-Glass Via technology. Already delivering small-batch glass substrates for 1.6T optical modules — an early commercial application outside of compute.

Korean Push

South Korea is racing to close the packaging gap with Taiwan and China. Samsung's foundry division and Korean substrate makers (Samsung Electro-Mechanics, LG Innotek) are investing in glass substrate R&D to support Samsung's own AI accelerator packaging roadmap.

Impact on the PCB Industry

What Changes for PCB Fabricators

Glass substrates don't replace PCBs — they replace the IC substrate layer between the chip and the PCB. The implications:

Motherboard design changes: Glass substrate packages have different ball patterns, power delivery requirements, and thermal interfaces. PCB motherboards must be redesigned for each glass-substrate processor generation.
Signal integrity requirements increase: With the package-level interconnect no longer the bottleneck, the PCB motherboard traces become the limiting factor. Expect tighter impedance tolerances (±5% standard) and ultra-low-loss material adoption on PCB motherboards.
Power delivery copper weight: Glass substrates enable higher processor power (>600W TDP). PCB power planes must scale proportionally — 4-8 oz copper, embedded bus bars.
IC substrate market disruption: Traditional ABF substrate fabricators (Ibiden, Shinko, Unimicron) must either invest in glass capabilities or risk market share erosion to glass-native manufacturers.

What Stays the Same

PCBs still connect everything at the system level
Increasing PCB complexity supports glass substrate packages
High-layer-count, controlled-impedance PCB demand actually increases
Fabricators serving AI server markets see demand growth regardless of substrate technology choice

Timeline: Glass Substrate Adoption Roadmap

Timeframe	Application	Volume
2026 (now)	Intel Xeon 6+ server CPUs	Thousands/month
2027	NVIDIA AI accelerators (rumored)	Tens of thousands/month
2028	AMD data center CPUs + AI GPUs	Hundreds of thousands/month
2029	High-end networking ASICs (800G+)	Millions/year
2030+	5G/6G RF modules, automotive radar	Mass market penetration

The transition from organic to glass substrates will take a decade to fully play out — but for AI hardware designers, it's happening now.

What Hardware Engineers Should Do Today

Monitor package ball maps: Next-generation processors will have different substrate ball pitches — plan PCB footprint libraries accordingly
Specify ultra-low-loss PCB materials: Megtron 6/7, Tachyon, or equivalent for signals interfacing with glass-substrate processors
Design for higher power: Plan thermal solutions for >600W packages
Engage your PCB fabricator early: Discuss advanced material availability and controlled impedance capabilities for AI server boards

LEO Satellite Boom Reshapes Global PCB Supply Chains as Starlink Fleet Exceeds 7,000

AtlasPCBEngineering — Mon, 25 May 2026 06:21:47 +0000

Constellation Scale Creates New PCB Market Tier

The global satellite communications industry has reached an inflection point that is fundamentally altering PCB supply chain dynamics. According to Digitimes reporting on May 20, 2026, the deployment of low-Earth orbit (LEO) networks — led by SpaceX's Starlink, Amazon's Project Kuiper, and Europe's OneWeb — has created what industry analysts now classify as a distinct "NewSpace PCB" market segment.

Starlink's active constellation now exceeds 7,000 satellites, with SpaceX maintaining a launch cadence of 40-60 satellites per Falcon 9 mission, roughly twice per week. Each satellite contains an estimated 8-15 PCB assemblies spanning power management, digital processing, phased-array antenna feed networks, and inter-satellite laser link controllers.

At this scale, the constellation requires 56,000-105,000 individual PCBs per year just for new deployments — before accounting for the ground station infrastructure serving 5+ million subscribers globally.

The Manufacturing Challenge: Space Reliability at Commercial Speed

Traditional space-grade PCB manufacturing operates on 12-20 week lead times with per-board costs of $500-5,000. Every board undergoes 100% screening including thermal shock, microsection, and ionic contamination testing. This model cannot support constellation production rates.

The NewSpace approach redefines the cost-reliability trade-off:

Material selection: High-Tg polyimide substrates with ASTM E595 outgassing compliance, but procured through standard distribution rather than custom mill runs
Testing regime: Sample-based qualification rather than 100% screening — statistical process control replaces individual board verification
Lead times: 4-8 weeks, enabled by dedicated production lines rather than shared capacity with terrestrial orders
Design standardization: Common board formats across satellite variants reduce NRE and allow panel optimization

Mike Carano of the Global Electronics Association noted in a May 21, 2026 iConnect007 analysis that "the strongest momentum is concentrated in higher-value, higher-complexity applications" — with space hardware representing a prime example of demand pulling fabricators toward advanced process capabilities.

Supply Chain Implications

PCB Material Demand

LEO satellites require materials with specific space-qualified properties:

Polyimide laminates: Demand for Arlon 85N, Isola P96, and equivalent space-grade materials has driven 6-8 week lead time extensions since late 2025
Low-loss PTFE: Phased-array antenna boards use Rogers/Taconic materials — competing with 5G terrestrial infrastructure for the same capacity
HTE copper foil: High-temperature elongation copper needed for thermal cycling survival is now allocation-constrained

Fabricator Capacity

A growing number of Asian PCB fabricators are investing in IPC-6012ES-capable production lines specifically targeting constellation volumes. Taiwan's Nan Ya PCB and Zhen Ding Technology have both announced capacity expansions supporting advanced substrate work that serves both semiconductor packaging and space applications.

The convergence of space-grade materials with high-volume production processes has created a new fabricator capability tier — facilities that maintain cleanroom environments and space-qualified process controls while operating at throughput levels previously reserved for consumer electronics.

AtlasPCB's Position in the Space Supply Chain

The LEO constellation market aligns with AtlasPCB's core strengths in high-reliability PCB manufacturing:

Material expertise: We process polyimide, Rogers PTFE, and hybrid stackups routinely used in satellite RF assemblies
Controlled impedance: Tight-tolerance impedance control (±5% available) critical for satellite communication boards operating at K-band and above
Thermal cycling qualification: Our IPC-6012 Class 3 processes already meet the baseline thermal shock requirements; ES addendum capabilities in development
Volume scalability: Production capacity supports the recurring monthly volumes that constellation replenishment demands

For engineering teams designing constellation hardware, early engagement with the fabricator on material availability and process qualification prevents the 3-6 month delays common when space-grade material goes on allocation. Our RF microwave PCB capabilities and controlled impedance expertise directly serve the phased-array and high-speed digital boards that constellation hardware demands.

Looking Ahead

Industry analysts project the LEO satellite market will maintain 25-30% annual PCB demand growth through 2030, driven by:

Constellation replenishment: 5-7 year satellite life means continuous manufacturing demand
V2 and V3 designs: Next-generation satellites are more complex (more PCBs per unit)
New entrants: Dozens of IoT, Earth observation, and navigation constellations entering deployment
Ground infrastructure: Each new generation of user terminals and ground stations multiplies board demand

The companies that successfully bridge space-grade reliability with commercial manufacturing economics will capture a market segment worth an estimated $2-4 billion in bare PCB revenue by 2030.

Sources: Digitimes (May 20, 2026), iConnect007/Global Electronics Association (May 21, 2026), SpaceX public deployment data

Image: SpaceX via Unsplash

Designing PCBs for satellite applications? Request a consultation with our aerospace manufacturing team. We'll help you balance reliability requirements with production economics for your constellation program.

Originally published on AtlasPCB

TSMC Projects 11 AI Wafer Demand Growth, Accelerates CoWoS Packaging Expansion

AtlasPCBEngineering — Sun, 24 May 2026 06:34:39 +0000

Originally published at AtlasPCB

TSMC Raises AI Demand Forecast at Technology Symposium

At its North America Technology Symposium held in May 2026, TSMC significantly elevated its long-term outlook for AI-related semiconductor demand, projecting an eleven-fold increase in AI accelerator wafer shipments between 2022 and 2026. The foundry giant also raised its estimate for the total addressable semiconductor market to exceed $1.5 trillion by 2030.

The announcement came alongside detailed roadmaps for expanding CoWoS (Chip on Wafer on Substrate) advanced packaging capacity, SoIC 3D stacking technologies, and silicon photonics integration—all critical enabling technologies for next-generation AI training and inference hardware.

CoWoS Capacity Expansion: What It Means for PCB Substrates

TSMC's CoWoS packaging platform is the enabling technology behind NVIDIA's H100, B200, and GB200/300 accelerators, as well as AMD's MI300 and MI400 series. Each CoWoS package requires:

High-layer-count PCB substrates (20+ layers with 50μm line/space)
Ultra-low-loss dielectric materials to support 112Gbps+ SerDes signaling
Large-format panels (up to 100mm × 100mm substrate size for GB300)
Precise impedance control across all signal layers (±5% tolerance)

The 11× growth projection means substrate manufacturers must dramatically scale output. Industry reports indicate CoWoS substrate supply remains the primary bottleneck—not wafer fabrication capacity—for AI chip delivery timelines through at least late 2027.

Five 2nm Fabs Ramping Simultaneously

TSMC disclosed that five 2nm wafer fabrication facilities are simultaneously entering ramp-up in 2026—an unprecedented parallel production introduction. First-year 2nm output is projected approximately 45% higher than 3nm production at the equivalent milestone, reflecting the massive pre-orders from AI chip designers.

The Arizona expansion continues as well, with the third Phoenix fab topped out and targeting sub-2nm process technologies with production before 2030. TSMC's board approved up to $20 billion in additional capital investment for its Arizona subsidiary.

For PCB substrate suppliers, this acceleration means:

Higher demand for ABF (Ajinomoto Build-up Film) substrates
Increased orders for high-layer-count test boards and interposer carriers
Growing need for glass-core substrates as silicon interposers exceed current organic substrate capabilities

Market Impact on PCB Supply Chain

TSMC's record 2026 capital expenditure budget of $52-56 billion signals sustained demand growth that cascades through the entire electronics supply chain:

Substrate manufacturers (Ibiden, Shinko, AT&S) are adding capacity but remain supply-constrained
CCL/laminate suppliers face pricing pressure as high-end material demand outpaces supply
PCB fabricators serving AI server OEMs report lead time extensions from 8 to 14 weeks
Testing capacity for high-speed substrates (>56 Gbps channel verification) remains scarce

The foundry also highlighted that future performance improvements will increasingly rely on advanced packaging, interconnect architectures, and system-level optimization rather than transistor scaling alone—further elevating the importance of PCB substrate technology in the overall chip performance equation.

Technical Implications: What 11× Means for PCB Substrates

The exponential scaling of CoWoS packaging creates specific technical demands on PCB substrate technology:

Larger interposer substrates: Next-generation AI packages use die-stitched silicon interposers exceeding two reticle fields in area. The organic package substrates beneath these interposers must grow correspondingly—from ~55×55mm for current designs to ~100×100mm for GB300-class packages. This pushes organic substrate fabrication panels to their physical limits.

Higher HBM memory integration: Future CoWoS packages will integrate 8-12 HBM stacks per device (up from 4-6 today). Each stack requires precise microbump connections and thermal management paths through the substrate, demanding more redistribution layers with finer features.

Signal integrity at 224 Gbps: Next-generation AI interconnects target 224 Gbps PAM4 signaling between chiplets and to external SerDes. The package substrate and system board must support <15 dB insertion loss at 56 GHz Nyquist frequency—requiring ultra-low-loss dielectrics and precise impedance control throughout the signal path.

Power delivery scaling: AI accelerators dissipating 700-1000W require hundreds of amps delivered through the package substrate. This necessitates thick copper layers (20-35μm), extensive power/ground plane allocation, and low-resistance via structures that compete for routing resources.

Industry Capacity Response

Substrate manufacturers are responding with massive capital investments:

Ibiden: Expanding Ogaki facility with new clean rooms targeting 2027 full production
Shinko Electric: Investing ¥130 billion in new Nagano substrate factory
AT&S: Kulim, Malaysia facility Phase 2 targeting CoWoS-equivalent substrates
Samsung Electro-Mechanics: Sejong campus expansion for AI substrate production

Despite these investments, industry analysts project substrate supply will lag demand through at least 2027, creating continued allocation pressure for PCB-grade ultra-low-loss materials that share similar resin systems with substrate build-up layers.

AtlasPCB's Position in AI Hardware

As AI hardware continues its exponential growth trajectory, AtlasPCB serves the ecosystem through:

High-layer-count prototype boards (up to 32 layers) for AI accelerator evaluation platforms
Advanced HDI fabrication with sequential lamination for substrate-like density
Ultra-low-loss material processing (Megtron 7, Panasonic R-5775K) for 112G+ SerDes channels
Rapid-turn prototyping enabling AI chip designers to validate packaging concepts quickly

The growing complexity of AI server PCBs—20+ layers, 50μm features, controlled impedance on every signal layer—demands fabrication partners with deep process expertise and advanced material handling capabilities.

Source: FTC Electronics Weekly News, TSMC North America Technology Symposium presentations, May 2026.

Image: Alexandre Debiève via Unsplash

Related Reading:

Quilter and Siemens Push AI-Driven PCB Design: Autonomous Layout Moves from Demo to Production

AtlasPCBEngineering — Sun, 24 May 2026 06:34:31 +0000

Originally published at AtlasPCB

AI PCB Design Tools Achieve Production Readiness

The electronic design automation (EDA) market for PCB design reached $4.2 billion in Q1 2026 revenue, marking 20 consecutive quarters of growth driven predominantly by AI feature integration. Two developments this month signal that AI-driven PCB layout is transitioning from experimental demonstrations to production-ready tooling.

Quilter's Project Speedrun demonstrated autonomous layout of a complete computer system—from schematic upload through DRC-clean layout to fabricated, validated hardware—showcasing what fully autonomous PCB design looks like in practice. The company claims 10× faster time-to-layout compared to manual processes.

Siemens' Xpedition Standard launched with comprehensive AI integration spanning front-end design entry, automated implementation, design reuse, and connected manufacturing release documentation powered by Valor intelligence.

EDA Market Context: 20 Quarters of Consecutive Growth

The $4.2 billion Q1 2026 EDA revenue for PCB design represents a structural shift in how the industry values design automation. AI-native features now command significant premium pricing:

Machine learning-powered DFM checks catching manufacturing issues during layout, not after fabrication
AI routing optimization producing results that match experienced layout specialists in fewer iterations
Predictive signal integrity analysis running continuously during placement/routing rather than as a post-layout verification step
Automated constraint extraction from reference designs and datasheets, reducing setup time from days to hours

The growth trajectory shows no signs of plateauing—AI hardware demand drives more complex boards, which drives more demand for AI design tools, creating a positive feedback loop.

Quilter: From Concept to Validated Hardware

Quilter's approach represents the most aggressive vision of AI PCB design: treating layout as a physics-driven optimization problem rather than a human-guided manual process.

Their "Project Speedrun" demonstration walked through a complete workflow:

Design compilation: Upload schematic, AI interprets circuit intent and constraints
Autonomous layout: Physics-based solver generates complete placement and routing
Design cleanup: Brief precision pass to finalize fabrication-ready output
Hardware validation: Power-on testing confirming electrical correctness

The significance isn't just speed—it's the elimination of the layout-specialist bottleneck. Traditional PCB layout requires specialized engineers with years of experience in a specific tool. Quilter's system compresses this expertise into software, potentially democratizing complex PCB design.

Siemens Xpedition: AI Within the Traditional Workflow

While Quilter pursues fully autonomous layout, Siemens takes an integration approach—embedding AI capabilities within Xpedition Standard's existing professional workflow:

AI-powered front-end design entry: Intelligent component suggestion, schematic error detection
Advanced automation for implementation: ML-optimized placement and routing suggestions
Reuse-driven productivity: AI identifies reusable circuit blocks from past designs
Connected release documentation: Automated manufacturing output with Valor DFM intelligence

As David Haboud from Siemens Electronic Systems Design noted: "Modern PCB design teams are being asked to do more with less. The problem is not complexity alone—it is the growing amount of manual effort required to manage that complexity across the design process."

This pragmatic approach appeals to organizations that need productivity gains without abandoning proven workflows and established design libraries.

Market Implications for PCB Fabricators

AI design tools create several downstream effects for PCB manufacturers:

Faster Design Cycles, More Prototypes

When layout takes days instead of weeks, designers iterate more aggressively. This means:

Higher prototype order frequency (more spins, faster)
Shorter gaps between revision orders
Increased demand for quick-turn fabrication (24-48 hour turns)
More adventurous designs as the cost of iteration drops

Improved DFM Compliance

AI tools incorporate manufacturing constraints during layout rather than as post-facto checks:

Fewer DFM violations requiring manual ECOs
Better yield rates due to constraint-aware routing
More consistent design quality across engineering teams
Reduced fabrication rejects and re-spins

New Design Complexity

Paradoxically, easier design tools enable more complex boards:

Engineers attempt higher layer counts knowing AI handles routing complexity
Tighter pitch components (0.4mm BGA) become feasible for less experienced teams
More controlled impedance pairs as AI optimally manages signal routing
Increased thermal and power delivery optimization requiring fabrication precision

AtlasPCB's Role in the AI Design Era

As AI tools accelerate design cycles, fabrication partners must keep pace:

Rapid-turn prototyping (48-72 hour standard, 24-hour expedite) matches AI-enabled design iteration speed
Advanced DFM review catches issues that AI layout tools may not fully optimize for manufacturing reality
Engineering consultation helps designers validate AI-generated layouts against real fabrication constraints
Production scaling when AI-designed boards move from prototype to volume

The best outcomes emerge when AI-optimized designs meet fabrication partners who understand both the tool outputs and the manufacturing physics.

Sources: Quilter.ai Blog; Siemens EDA Blog, May 2026; EDA market data from industry reports.

Image: Igor Omilaev via Unsplash

Related Reading:

Samsung Averts Semiconductor Worker Strike as AI Chip Profits Reshape Labor Relations

AtlasPCBEngineering — Sat, 23 May 2026 06:17:04 +0000

Strike Averted, But Tensions Reveal Industry Pressure Points

Samsung Electronics narrowly avoided a semiconductor worker strike this week after reaching a bonus agreement with the National Samsung Electronics Union (NSEU). The deal ties worker compensation directly to profits from AI-driven memory chips—particularly High Bandwidth Memory (HBM) products that have seen explosive demand growth.

The near-miss highlights how the AI hardware boom is creating labor pressures across the semiconductor supply chain, with implications that extend from chip fabrication down to the PCB substrates that connect these advanced memory packages.

What Happened

Samsung's semiconductor division workers demanded a greater share of profits generated by the company's HBM3E memory chips—products selling at 5–8× the price-per-bit of conventional DRAM. The union argued that while Samsung's memory division reported record operating profits driven by AI server demand, worker bonuses hadn't kept pace.

The agreement, reached just hours before a planned walkout, reportedly includes:

Performance bonuses tied to AI chip division profitability
Expanded profit-sharing for HBM production lines
Commitment to maintain workforce levels despite increased automation

Had the strike proceeded, analysts estimated potential disruption to:

HBM3E production for NVIDIA and AMD AI accelerators
LPDDR5X supply for smartphone and laptop OEMs
DDR5 server memory during already-tight supply

Why Hardware Engineers Should Pay Attention

The Samsung situation illuminates a broader reality: every disruption in semiconductor manufacturing creates downstream PCB demand volatility.

HBM and Advanced Packaging Drive Substrate Demand

HBM chips don't connect directly to a motherboard—they sit on advanced organic substrates (interposers and redistribution layers) that are essentially high-density PCBs manufactured with IC substrate processes:

2-2-2 µm line/space (vs 75/75 µm for standard PCBs)
ABF (Ajinomoto Build-up Film) dielectric layers
10+ redistribution layers with microvias
Panel-level packaging at substrate manufacturers

Samsung's HBM production volume directly correlates with substrate demand at companies like Ibiden, Shinko Electric, and Samsung Electro-Mechanics.

Supply Chain Ripple Effects

A Samsung production disruption—even brief—would cascade:

Memory pricing spikes → AI server OEMs delay orders → reduced demand for server motherboard PCBs
HBM substrate orders pause → substrate fabricators redirect capacity
Inventory building → customers double-order creating artificial demand spikes later

The Bigger Picture: AI Profits Reshaping Electronics Labor

Samsung's deal reflects a pattern across the electronics manufacturing ecosystem:

TSMC increased worker bonuses 20% in 2025, linked to AI chip revenue
SK Hynix restructured compensation to share HBM profits with production staff
European semiconductor incentives (EU Chips Act) include workforce development mandates

As AI hardware generates outsized profits concentrated in specific product lines, workers across the value chain—from chip fabrication to PCB assembly—are demanding a larger share. This structural shift will likely increase manufacturing costs industry-wide over the next 2–3 years.

Implications for PCB Procurement

For hardware engineers and procurement managers:

Diversify memory sourcing: Don't rely 100% on a single DRAM/NAND vendor
Monitor labor relations at key suppliers: Union negotiations at Samsung, SK Hynix, and TSMC signal upcoming supply disruptions
Build substrate lead time into schedules: Advanced packaging substrates already have 16–20 week lead times
Consider PCB fabrication geography: Manufacturing in regions with stable labor relations reduces schedule risk

Originally published at AtlasPCB Engineering Blog

For consistent PCB supply without semiconductor-market volatility affecting your deliveries, explore AtlasPCB's capabilities — we maintain buffer material inventory to ensure on-time delivery. Get a quote →

UK Startup siliXon Raises $1.5M to Build AI That Generates PCB Designs from Text Prompts

AtlasPCBEngineering — Sat, 23 May 2026 06:16:34 +0000

From Text Prompt to Circuit Board: siliXon's Vision

UK-based startup siliXon has raised $1.5 million in a seed round led by German early-stage investor System.One, with participation from Antler, to build AI tools that generate complete printed circuit board designs from text prompts. The company aims to make hardware design as accessible as writing a software specification.

How Text-to-PCB Works

siliXon's approach treats circuit board design as a generation problem—similar to how large language models generate text or image models generate pictures from descriptions:

Input example: "Design a Bluetooth Low Energy sensor board with BME280 temperature/humidity sensor, LSM6DSO accelerometer, nRF52840 MCU, CR2032 coin cell power, 25mm circular form factor, I2C debug header"

Output: Complete schematic, component selection, PCB layout, BOM, and Gerber files ready for fabrication.

The system is trained on databases of existing PCB designs, component datasheets, and manufacturing design rules. For well-characterized patterns (IoT sensor nodes, motor controllers, LED drivers, USB hubs), the generation can produce reasonable first-pass designs.

The European Manufacturing Angle

siliXon explicitly frames its mission beyond just design automation. The company wants to "help Europe reclaim its technology supply chain" by:

Lowering barriers to entry: If designing a PCB requires only describing what you want, more European companies can develop custom hardware without outsourcing design
Enabling local manufacturing: Simpler, standard-geometry designs generated by AI are well-suited to European PCB fabricators
Reducing prototype cycles: When iteration is cheap and fast, companies keep manufacturing closer to R&D

Where This Fits in the AI EDA Landscape

The AI-powered EDA market has rapidly segmented into three tiers:

Tier	Company	Approach	Best For
Generative	siliXon	Text-to-complete-design	Beginners, rapid prototyping
Autonomous	Quilter	Schematic-to-layout	Professional engineers, complex boards
Augmented	Siemens Fuse, Cadence Cerebrus	AI copilot in existing tools	Enterprise design teams

siliXon targets the most ambitious tier—generating designs without requiring the user to create a schematic first.

Technical Challenges Ahead

Despite the impressive demo potential, text-to-PCB faces real engineering challenges:

Design rule complexity: A simple text prompt doesn't capture the hundreds of constraints needed for a manufacturable board (impedance requirements, thermal considerations, EMC compliance, testability).

Safety validation: For anything beyond hobby electronics, generated designs need simulation verification (SI/PI analysis, thermal modeling) that current AI tools don't fully automate.

Manufacturing awareness: Without knowing the specific fabricator's capabilities (minimum trace width, layer count limits, material availability), AI may generate designs that are theoretically correct but practically unfabricatable.

Liability: When an AI-generated design fails in the field, the responsibility chain is unclear—this limits adoption in safety-critical markets.

Market Opportunity

The PCB design services market was valued at approximately $4.8 billion in 2025. siliXon's bet is that text-to-PCB can capture the long tail of simple designs that currently go to freelance designers.

If the technology works as promised, it could:

Reduce simple PCB design costs from $500–$5,000 to near-zero for tool subscribers
Compress prototype timelines from 2–4 weeks to hours
Enable non-specialists (mechanical engineers, software developers) to create functional hardware prototypes

The Bigger Picture: EDA's AI Moment

EDA tool revenue for PCB design reached $4.2 billion in Q1 2026, marking 20 consecutive quarters of growth. The acceleration isn't from incremental improvements—it's driven by AI-native features that command premium pricing because they demonstrably reduce design time.

Whether text-to-PCB becomes as transformative as text-to-code remains to be seen. But the investment is flowing, the demos are improving, and hardware engineers should be paying attention.

Originally published at AtlasPCB Engineering Blog

For engineers looking to turn AI-generated or traditional designs into production-quality PCBs, check out AtlasPCB's manufacturing capabilities — free DFM review included with every order.

SEMICON SEA 2026: Chinese PCB Companies Pivot to Advanced Packaging — What This Means for Hardware Engineers

AtlasPCBEngineering — Fri, 22 May 2026 06:17:33 +0000

SEMICON Southeast Asia 2026 (May 5-7, Kuala Lumpur) marked a significant inflection point for the PCB industry. Over 95 mainland Chinese companies exhibited — and the dominant theme wasn't traditional PCB fabrication. It was advanced semiconductor packaging.

The Great Pivot: From PCB to Semiconductor

The most notable trend was a wholesale repositioning away from "PCB manufacturer" branding toward semiconductor-oriented positioning. Companies from Shenzhen, Dongguan, Suzhou, and Shanghai dominated the exhibitor list, spanning semiconductor equipment, advanced packaging materials, IC substrates, cleanroom solutions, and precision automation.

As IC&PCB Union noted in their analysis: "Semiconductor has become a core keyword in many Chinese company names, reflecting the industry's transition from traditional electronics manufacturing toward advanced packaging and wafer-level technologies."

Why This Matters for PCB Engineers

The convergence of PCB and semiconductor packaging creates both challenges and opportunities:

1. Substrate Requirements Are Blurring

IC substrates use PCB manufacturing techniques (SAP/mSAP processes) at semiconductor tolerances. The line between a "PCB" and a "substrate" is increasingly artificial.

2. Equipment Is Crossing Over

Laser drill, plating, and inspection equipment designed for PCB is being adapted for packaging substrates. Companies like Dongguan Allmerit, Wuxi KINGWIN, and Shenzhen Tensun — traditionally PCB equipment suppliers — were actively exhibiting at SEMICON.

3. Materials Overlap

ABF build-up films, low-CTE glass cloth, and ultra-thin copper foils serve both markets. The same material science drives innovation in both directions.

4. Engineering Talent Is Shared

PCB design skills translate directly to substrate design. If you understand HDI via structures, impedance control, and thin dielectric processing, you're already halfway to substrate engineering.

Delta Electronics: AI in Packaging Manufacturing

Delta Electronics presented AI-integrated smart manufacturing solutions, demonstrating how artificial intelligence enables "smarter, more connected, advanced semiconductor packaging production featuring greater speed, precision, and scalability."

Their focus on power management and thermal solutions for packaging equipment highlights how similar thermal challenges exist across both PCB fabrication and semiconductor assembly.

ASMPT: Full-Spectrum Solutions

ASMPT exhibited under the theme "Empower the Intelligence Revolution," covering semiconductor packaging, SMT assembly, and intelligent factory technologies. Their booth demonstrated the full continuum from die bonding to PCB assembly — reinforcing how these disciplines are converging.

Practical Implications

For hardware engineers sourcing advanced substrates and HDI boards:

More fabricators are developing capabilities that bridge traditional multilayer PCBs and semiconductor-grade substrates
mSAP processing (≤30 μm trace/space) is becoming available from more suppliers
Any-layer microvia technology is moving from premium to standard offering
Ultra-thin core handling (<0.1mm cores) is expanding beyond substrate specialists

The Future

The traditional boundary between "PCB fabricator" and "substrate manufacturer" is dissolving. For engineers, this means:

More sourcing options for advanced interconnects
Better pricing competition as more players enter the advanced space
Faster technology adoption as PCB-origin companies bring volume manufacturing expertise to substrates

🔗 AtlasPCB Advanced HDI & Substrate Capabilities

🔗 Get a Quote for HDI/Advanced PCB

Sources: IC&PCB Union SEMICON SEA 2026 coverage, ASMPT Press Release, Delta Electronics/PRNewswire

DEV Community: AtlasPCBEngineering

EV Group Demonstrates 450nm Pitch Hybrid Bonding at ECTC 2026: 98% Yield Across 20M Interconnects

EV Group Showcases 450nm Pitch Hybrid Bonding and Layer Transfer at ECTC 2026

Key Technologies Demonstrated

Ultra-Fine Pitch Hybrid Bonding (450nm)

300nm Pitch Process Integration

IR Layer Transfer (LayerRelease™)

Maskless Lithography (LITHOSCALE® XT)

Seven Technical Sessions

Why This Matters for PCB Engineers

ECTC 2026 Opens: Record Papers on AI Chip Packaging Drive Substrate Technology Forward

ECTC 2026 Opens in Orlando: Record Papers on AI Chip Packaging Drive Substrate Technology Forward

AI Packaging Dominates the Technical Program

Breakthrough Result: 450nm Pitch Hybrid Bonding

Key Industry Implications

The AI Packaging Arms Race

Solder TIMs for AI Chip Thermal Management: 86 W/mK Indium Solutions at ECTC 2026

The AI Thermal Crisis and Why Polymer TIMs Are Failing

From Grease to Metallurgical Bonds: The sTIM Advantage

Why Indium?

ECTC 2026 Innovation: Vacuum Formic Acid Reflow

1. Oxide Removal Without Flux

2. Vacuum Void Elimination

3. Multi-Reflow Compatibility

Results

PCB Substrate Design Implications

Increased Thermal Cycling Stress

Power Delivery for 700W+ Processors

Via Reliability Requirements

Industry Trajectory

Practical Takeaways for Hardware Engineers

U.S. Senate Introduces PCB Reshoring Bill: 25% Tax Credit for Domestic Manufacturing

Senate Bill S.4569 Targets PCB Industry Revival

Three Decades of Decline

What the Bill Means for the Industry

For U.S. PCB Manufacturers

For OEMs and Defense Primes

For the Global Supply Chain

Defense and National Security Context

What This Means for PCB Buyers

Advanced Packaging Revolution: How Chiplets and 2.5D Integration Are Reshaping PCB Substrates

Why Chiplets Change Everything Below the Package

The Emerging "Bridge" Substrate Category

2.5D Packaging: The Interposer Challenge

Industry Is Betting Big

What This Means for Your Next Design

Glass Core Substrates for AI Packaging: How Intel's Clearwater Forest Changes the PCB Substrate Roadmap

The Organic Substrate Wall

Intel Clearwater Forest: First HVM Glass Substrate Product

Technical Specifications

Performance Benefits Demonstrated

How Glass Substrates Are Made

Step 1: Glass Panel Preparation

Step 2: Through-Glass Via (TGV) Formation

Step 3: Metallization

Step 4: Build-Up Layers

Step 5: Bumping and Singulation

Why Glass Matters for AI Specifically

Power Delivery

Chiplet Architecture Support

Bandwidth Density

The Competitive Landscape

Intel: First Mover Advantage

Chinese Players Racing to Catch Up

Korean Push

Impact on the PCB Industry

What Changes for PCB Fabricators

What Stays the Same

Timeline: Glass Substrate Adoption Roadmap

What Hardware Engineers Should Do Today

Further Reading

LEO Satellite Boom Reshapes Global PCB Supply Chains as Starlink Fleet Exceeds 7,000

Constellation Scale Creates New PCB Market Tier

The Manufacturing Challenge: Space Reliability at Commercial Speed

Supply Chain Implications

PCB Material Demand

Fabricator Capacity

AtlasPCB's Position in the Space Supply Chain

Looking Ahead

TSMC Projects 11 AI Wafer Demand Growth, Accelerates CoWoS Packaging Expansion