DEV Community: AtlasPCBEngineering

What Your PCB Quote Is Actually Telling You (From a Manufacturer's Perspective)

AtlasPCBEngineering — Sat, 12 Sep 2026 00:38:45 +0000

You send the same Gerber files to five PCB manufacturers. The quotes come back: $12, $19, $25, $31, and $48 per board. Same board, same quantity, same specs on paper.

What's going on?

Having reviewed thousands of competitor quotes over the years (engineers send them to us regularly), I can tell you: these numbers aren't directly comparable. They almost never include the same things.

The Hidden Structure of PCB Pricing

Every PCB quote covers five categories of cost — whether the manufacturer shows them separately or buries them in the unit price:

Materials (25-35% of cost for standard FR-4, up to 50%+ for Rogers/specialty)

Processing — every step from cutting through routing. A 2-layer board goes through ~12 major steps. A 10-layer board with blind vias? Twenty-five or more.

Quality assurance — AOI, electrical testing, impedance verification, final inspection. This is 10-15% of cost in a well-run factory. Some manufacturers include it. Some list it separately. Some... don't mention it at all.

Engineering overhead — CAM processing, panelization, drill programs, DFM review. Takes 1-4 hours per new design.

Logistics — packaging, documentation, shipping, customs.

The key insight: a manufacturer quoting $12.40/board isn't necessarily cheaper than one quoting $18.90 if the first excludes testing, charges tooling separately, and adds packaging fees that the second already bundled in.

The Specification Multipliers Nobody Talks About

Certain design choices have outsized effects on fabrication cost. From our production data:

Layer count: 2L → 4L = 1.6-1.8x. 4L → 6L = another 1.4-1.6x. 8L = 2.0-2.5x the 4L cost. 10L+ = 3x or more.
Trace/space: Standard (4-6 mil) = baseline. 3 mil = +10-20%. Below 3 mil = +30-50%. Below 2 mil (mSAP territory) = +60-100%.
Surface finish: HASL = baseline. ENIG = +30-50%. ENEPIG = +50-70%.
Impedance control: ±10% = +10-15%. ±5% = +40%+ (yield impact is non-linear).
Heavy copper: +15-30% per additional ounce above 2oz.

When four manufacturers quote between $15-25 and one quotes $8, that low quote should raise questions, not celebrations.

How to Actually Compare: Total Landed Cost

The only meaningful comparison metric is total landed cost per delivered board:

(one-time costs) + (unit price × quantity) + (separate line items × quantity) + shipping + duties
────────────────────────────────────────────────────────────────────────────────────────────────
                                delivered quantity

Example: Quote A says $14.50/board + $300 tooling + $150 test setup + $85 shipping for 100 boards = $19.85 per delivered board. Quote B says $19.00/board all-inclusive with shipping = $19.00 per delivered board. B is actually cheaper despite the higher unit price.

Red Flags From the Factory Floor

After reviewing thousands of quotes, these patterns reliably predict problems:

Price dramatically below market — four quotes at $15-25, one at $8? That $8 means corners are being cut, or fees will appear later.
No mention of electrical testing — if a manufacturer doesn't test every board for opens, shorts, and isolation, that's disqualifying for professional applications.
"High-quality FR-4" without specifics — there's a measurable difference between a Shengyi S1000-2 and generic FR-4 from an unnamed supplier. If your material properties matter, the quote should name the material.
Unrealistic lead times — a 10-layer impedance-controlled board with blind vias and ENIG cannot ship in 5 days, period. A manufacturer promising this is either lying or cutting quality controls.
Zero DFM feedback — a competent fabricator seeing your design for the first time will almost always have questions. If they accept everything without comment, they're not reviewing your files.

When the Cheapest Quote Costs the Most

Consider: 500 boards at $15 each (low-cost) vs. $20 each (quality-focused). Savings = $2,500.

If the low-cost supplier delivers 3% defect rate caught during assembly — you scrap 15 boards ($225 in PCB cost, potentially $1,500+ in assembled board value with components already placed), delay production, and spend engineering time diagnosing whether failures are design or fabrication issues.

That $2,500 "savings" evaporates immediately. And 3% isn't even unusual for the cheapest tier.

The Questions That Reveal Everything

When evaluating manufacturers, these questions tell you more than any price sheet:

"What material will you use, specifically?" → Naming brand, grade, and Tg = they've reviewed your spec.
"What's your standard test coverage?" → Should be 100% net testing on every board.
"Can you share process capability data for my critical features?" → Cpk data = they monitor statistically.
"What happens if delivered boards don't meet spec?" → Strong manufacturers offer replacement at no charge with expedited delivery.

The Bottom Line

Comparing PCB quotes isn't about finding the lowest number. It's about normalizing every quote to total landed cost, verifying all essential services are included, and factoring in the quality track record and engineering support that determine whether the quoted price translates into a successful product.

The manufacturers worth working with are the ones whose quotes you can read clearly, whose pricing reflects genuine capability, and whose engineering teams engage with your design before the first panel hits the line.

I lead the engineering team at AtlasPCB, where we review PCB designs and provide transparent quoting for RF, HDI, and multilayer boards. We wrote a more detailed version of this guide with specific cost tables and a normalization checklist on our blog.

mSAP vs Subtractive PCB Manufacturing: When Fine Lines Demand a Different Process

AtlasPCBEngineering — Fri, 11 Sep 2026 00:31:34 +0000

Reviewed by AtlasPCB Engineering Team

Every PCB design eventually confronts a fundamental manufacturing question: can the fabricator hold your trace geometry with conventional etching, or does the design require a fundamentally different process? For decades that question rarely came up, because most designs stayed comfortably within the capability window of subtractive etching. That is changing. As package densities increase, as 5G mmWave antenna arrays demand tighter pitch, and as system-in-package architectures push interconnect density toward IC substrate territory, the line between "subtractive can handle it" and "you need mSAP" has become one of the most consequential decisions in PCB engineering.

We manufacture both ways. Our subtractive lines run hundreds of panels a day across the full range of standard and HDI constructions, and our mSAP-capable lines handle the designs that have moved beyond what etching can reliably produce. This article shares what we have learned from operating both processes side by side — where each one excels, where each one fails, and exactly where the crossover point falls in real production.

How Subtractive Etching Defines Most PCBs Made Today

The subtractive process is the foundation of modern PCB manufacturing, and for good reason. The concept is straightforward: start with a copper-clad laminate where a full sheet of copper foil has been bonded to the dielectric substrate during lamination. Apply a photosensitive resist layer, expose it through a phototool or with a laser direct imaging system to define the circuit pattern, develop away the unexposed resist to reveal the copper that needs to be removed, etch the exposed copper in a chemical bath, and finally strip the remaining resist to leave behind the finished traces.

This process has been refined over more than fifty years of industrial production. The chemistry is well understood, the equipment is mature, and the supply chain for materials — standard FR-4 laminates, copper foils in standard thicknesses from half-ounce to two-ounce, alkaline and acidic etchant systems — is deep and globally distributed. A competent fabricator can run subtractive etching with high yield, tight process control, and predictable costs. When we quote a standard 4-layer or 6-layer board with 100-micron (4 mil) trace and space, we know exactly what the panel yield will be, how long the etch cycle takes, and what the per-unit cost looks like at any volume from prototype to mass production.

The dominance of subtractive etching is not just about tradition. It is genuinely the most cost-effective way to produce the vast majority of PCB designs. If your traces are 75 microns (3 mil) or wider, if your copper weight is half-ounce or one-ounce on outer layers, and if your impedance tolerances are within the standard plus-or-minus ten percent window, subtractive etching delivers exactly what you need at a price point that no other process can match. For a deeper look at what fabricators need in your design package to run subtractive production smoothly, see our guide on PCB manufacturing files and the complete package your manufacturer needs.

Where Subtractive Hits Its Limits — The Etch Factor Problem

The physics of chemical etching impose a hard constraint that no amount of process optimization can fully overcome. When etchant dissolves copper, it attacks the metal isotropically — meaning it etches laterally underneath the resist mask at the same rate it etches downward through the copper thickness. This lateral undercut is described by the etch factor, which is the ratio of etch depth to lateral etch distance. In a well-controlled production environment, typical etch factors range from 2.5 to 3.5 for alkaline cupric chloride etchants, with the best acidic systems reaching etch factors of 3.5 to 4.0 under ideal conditions.

The practical consequence is that every trace produced by subtractive etching has a trapezoidal cross-section. The top of the trace, protected by the resist, is narrower than the base where the etchant first contacts the copper. For a standard half-ounce copper foil (approximately 17 microns thick) with an etch factor of 3.0, the lateral undercut on each side is roughly 5.7 microns. On a trace with a 75-micron design width, that undercut reduces the top width to approximately 63.6 microns — a manageable deviation that impedance modeling can accommodate.

Now consider what happens as you push toward finer geometries. On a 50-micron (2 mil) trace with the same half-ounce copper, the same 5.7-micron undercut per side reduces the top width to about 38.6 microns. The trace now has a top-to-bottom width ratio of roughly 0.77, producing a noticeably trapezoidal profile. Impedance modeling can still handle this, but the tolerance band narrows considerably, and any variation in etch uniformity across the panel directly impacts impedance consistency.

Push further to 38 microns (1.5 mil) and the situation becomes critical. The top width drops to approximately 26.6 microns, a top-to-bottom ratio of 0.70, and the copper cross-sectional area has been reduced so significantly that current-carrying capacity and conductor loss both suffer. At 30 microns, assuming you could even resolve and develop the resist pattern at that pitch, the top width would be around 18.6 microns — less than two-thirds of the designed width, with a cross-section so far from rectangular that impedance prediction becomes unreliable.

We see this play out in production every week. Boards designed at 50-micron trace and space on standard half-ounce copper run with acceptable yield in our subtractive lines, though they require tighter process monitoring than designs at 75 microns. Boards at 38 microns require ultra-thin foils and modified chemistry, which we will discuss later. Below 30 microns, we do not attempt subtractive etching — the physics simply do not support it.

How mSAP Works — Building Traces Up Instead of Etching Them Down

The modified semi-additive process inverts the logic of subtractive etching. Instead of starting with a thick copper layer and removing everything you do not need, mSAP starts with a very thin copper seed layer — typically 2 to 5 microns — and adds copper only where the traces are supposed to be.

The process begins with a dielectric substrate that already has a thin copper foil laminated to its surface. This seed layer is far thinner than the half-ounce (17-micron) or quarter-ounce (9-micron) foils used in subtractive processing. A layer of photoresist is applied and patterned using the circuit artwork, but here the resist acts as a negative image: it covers the areas where copper should not be deposited, leaving the trace locations exposed. The panel then goes through an electroplating bath where copper is built up in the exposed areas to the desired final thickness, typically 15 to 25 microns depending on the design requirements.

After plating, the photoresist is stripped away, revealing the thin seed copper between the plated traces. This seed layer is then removed by a brief flash etch — a short, carefully controlled etching step that dissolves the 2-to-5-micron seed layer without significantly attacking the much thicker plated traces. Because the flash etch only needs to remove a few microns of copper, the lateral undercut is minimal — on the order of 1 to 2 microns — preserving the near-vertical sidewall profile that electroplating naturally produces.

The result is a trace with a substantially rectangular cross-section. The sidewall angle in mSAP traces typically measures 85 to 88 degrees from horizontal, compared to 65 to 75 degrees in subtractive traces. This near-vertical profile means the designed trace width and the actual trace width are nearly identical, impedance prediction is highly accurate, copper cross-sectional area matches design intent, and conductor loss is minimized.

It is worth distinguishing mSAP from full SAP, the fully additive semi-additive process used in IC substrate manufacturing. In full SAP, there is no pre-laminated copper foil at all. Instead, a catalytic seed layer — typically electroless copper deposited on a roughened or chemically activated dielectric surface — serves as the plating base. Full SAP can achieve the finest features, down to sub-10-micron trace and space, but it demands extremely smooth dielectric surfaces and a much more sensitive electroless copper adhesion mechanism. mSAP trades a small amount of resolution capability for substantially better process robustness and adhesion reliability, making it the practical choice for most fine-line PCB applications above 15 microns. For more on how flash copper plating supports both HDI microvias and mSAP seed layer processing, see our technical article on flash copper plating for HDI microvias and mSAP seed layers.

Line and Space Capabilities — The Real Numbers

Understanding where each process sits on the resolution spectrum is essential for making the right manufacturing decision. The capabilities are not theoretical maximums from laboratory demonstrations — they reflect what volume production can sustain with acceptable yield.

Standard subtractive etching with half-ounce copper foil and conventional etch chemistry handles trace and space down to approximately 50 microns (2 mil) in reliable production. Below 50 microns, yield drops and impedance variation increases to the point where many fabricators either refuse the job or quote significant premiums for the tighter process control required.

Advanced subtractive techniques — using ultra-thin copper foils of 5 to 9 microns, modified etch chemistry, and laser direct imaging — can push subtractive capability down to approximately 38 microns (1.5 mil) trace and space with acceptable production yield. Some fabricators claim 30-micron capability with advanced subtractive, but in our experience, the yield and impedance consistency at that geometry do not support volume production.

mSAP reliably produces trace and space geometries down to 15 to 20 microns in production. The finest features we run in volume are 20-micron trace and space for substrate-like PCB constructions, with 25-micron being a more common and higher-yield target for most fine-line applications.

Full SAP pushes into sub-10-micron territory, but this is IC substrate manufacturing — a different class of facility, equipment, and cost structure. For PCB-level applications, mSAP covers the range between 15 and 30 microns that subtractive cannot reach.

The zones, in practical terms, break down clearly. Above 50 microns, standard subtractive is the obvious choice. Between 38 and 50 microns, advanced subtractive techniques are the most cost-effective approach. Between 20 and 38 microns, the decision depends on your exact geometry, impedance requirements, and volume — but mSAP becomes increasingly attractive as you move toward the lower end of this range. Below 20 microns, mSAP or full SAP are the only viable options.

When to Choose mSAP Over Subtractive — The Decision Framework

The crossover point where mSAP becomes necessary rather than optional falls at approximately 30 microns (1.2 mil) trace and space. This is not an arbitrary number. It reflects the geometry at which subtractive etch factor limitations make it physically impossible to maintain an adequate copper cross-section for reliable impedance control, acceptable conductor loss, and consistent yield.

Above 30 microns, advanced subtractive techniques can still deliver acceptable results at significantly lower cost than mSAP. The engineering rationale is straightforward: with a 5-micron ultra-thin foil and an etch factor of 3.5, the lateral undercut per side is only about 1.4 microns, which preserves trace geometry well enough for impedance control at 35-to-50-micron features. The cost of ultra-thin foil processing is substantially less than the full mSAP process with its specialized materials and additional plating steps.

Below 30 microns, no amount of subtractive process optimization can compensate. Even with the thinnest available foils and the most selective etch chemistry, the remaining copper cross-section after etching is too small to deliver the designed impedance with acceptable tolerance, and the trapezoidal profile introduces enough geometric uncertainty to make impedance prediction unreliable.

Several application categories reliably require mSAP today. Smartphone-like PCBs (SLP, or substrate-like PCBs) are perhaps the most prominent, where the combination of thin form factor and high interconnect density demands trace geometries of 25 to 30 microns. System-in-package modules integrate multiple die on a common substrate and frequently require fine-pitch redistribution routing that only mSAP or SAP can produce. 5G antenna-in-package designs, where mmWave antenna elements must be precisely positioned with controlled-impedance feed structures at tight pitch, are another growing application. Advanced wearable devices and medical implant electronics also increasingly push into mSAP territory as their form factors shrink.

Conversely, many high-performance applications still belong on subtractive lines. High-layer-count server boards at 50-micron trace and space, automotive radar modules at 75-micron features on specialized low-loss laminates, aerospace avionics boards with conservative design rules — all of these are better served by the mature subtractive process with its lower cost, shorter lead times, and broader material selection.

Volume and cost also play a role in the decision. For prototype and low-volume production, the NRE costs of mSAP tooling and process qualification can add several thousand dollars to a project. At high volume, the per-unit premium narrows because material costs amortize and process yield stabilizes, but it never disappears entirely.

Material Considerations — ABF, Low-Dk Prepreg, and Copper Foil Selection

The material requirements for mSAP are fundamentally different from subtractive processing, and this difference is one of the primary cost drivers. The critical factor is dielectric surface roughness. In subtractive processing, moderate surface roughness is actually desirable because it promotes copper adhesion through mechanical interlocking between the copper foil and the resin surface. Standard FR-4 laminates have surface roughness values (Rz) in the range of 3 to 8 microns, which provides excellent adhesion for conventional foils.

In mSAP, that roughness becomes a liability. The thin seed copper layer of 2 to 5 microns cannot conformally cover a surface with roughness features approaching or exceeding the seed layer thickness itself. Incomplete coverage leads to adhesion failures, open circuits during flash etching, and unreliable plating nucleation. mSAP therefore requires dielectric surfaces with Rz roughness below 2 microns, and preferably below 1.5 microns.

Ajinomoto Build-up Film (ABF) is the dominant dielectric material for mSAP processing. Originally developed for IC substrate manufacturing, ABF provides an extremely smooth surface after lamination and curing, with Rz values typically below 1 micron. It also offers good dielectric properties (Dk around 3.3 to 3.5 at 1 GHz) and is well-characterized for fine-line processing. The drawback is cost — ABF is substantially more expensive than standard FR-4 prepreg, and it requires vacuum lamination equipment rather than standard hydraulic presses.

Modified prepreg systems from major laminate suppliers have expanded the material options for mSAP. Panasonic Megtron series and Mitsubishi BT resin systems both offer low-roughness variants engineered for mSAP compatibility. These materials can be processed on modified conventional lamination equipment, reducing the capital investment required compared to ABF-only facilities. Their dielectric properties are competitive with ABF, and some formulations offer lower loss tangent for applications where signal integrity at high frequency is critical.

Standard FR-4 remains unsuitable for mSAP. Its relatively rough copper-dielectric interface, which is an advantage for adhesion in subtractive processing, prevents reliable seed layer deposition and adhesion in the mSAP flow. We occasionally receive inquiries from designers who want mSAP resolution on FR-4 substrates, and the answer is always the same: the material system and the process are inseparable in fine-line manufacturing.

DFM Guidelines for mSAP Designs

Designing for mSAP fabrication requires several adjustments to the DFM practices that engineers have developed around subtractive processing. The differences are not dramatic, but ignoring them leads to yield issues, unnecessary cost, and sometimes outright manufacturing failures.

Pad design is the first area where mSAP diverges from subtractive conventions. In subtractive processing, annular ring specifications account for the etch factor by designing pads larger than the minimum needed for via capture. In mSAP, where the trace geometry is more faithful to the design intent, pad sizes can be reduced — but they must account for the alignment tolerance of the plating resist pattern to the drilled or laser-ablated via. We recommend maintaining at least 25 microns of annular ring on mSAP designs, compared to the 50-to-75-micron annular rings typical in subtractive HDI.

Via structures in mSAP designs need careful attention. Laser-drilled microvias are the standard interconnect in mSAP constructions, and the via diameter, capture pad, and plating aspect ratio must be coordinated with the mSAP process flow. Microvias are typically laser-drilled before seed layer deposition, and the via fill plating occurs simultaneously with trace plating. This means the via aspect ratio must be compatible with the plating bath chemistry and current density used for trace formation. We generally recommend via diameters of 50 to 75 microns for mSAP layers, with aspect ratios below 1:1 for reliable fill.

Copper balance across the panel is more critical in mSAP than in subtractive processing. In subtractive etching, large copper areas and fine traces are processed simultaneously — the etchant removes copper everywhere at roughly the same rate (with some loading effects). In mSAP, the electroplating step is sensitive to current density distribution. Large open areas adjacent to fine traces will plate faster, potentially producing over-thick copper in wide areas and under-thick traces in dense regions. Designing with uniform copper distribution, using hatched fills instead of solid pours in non-critical areas, and avoiding large disparities in feature density across the panel all improve plating uniformity and yield.

The most common mistake we see from designers new to mSAP is treating it as a drop-in replacement for subtractive processing with smaller numbers. It is not. The design rules, stackup construction, material selection, and via structures all interact with the mSAP process in ways that require intentional design choices. For guidance on HDI stackup design practices that complement mSAP fabrication, see our article on HDI PCB stackup design for advanced applications.

Cost and Lead Time Implications

mSAP carries a cost premium that designers and procurement teams need to understand in concrete terms. At comparable layer counts and board complexity, mSAP fabrication typically costs 40 to 80 percent more than conventional subtractive fabrication. The premium is not a single line item but rather the accumulation of several cost drivers.

Materials account for a significant portion. ABF or modified low-roughness prepreg systems cost two to three times more per panel than standard FR-4. The ultra-thin copper foils used as seed layers are also more expensive than standard foils, and they require more careful handling throughout the lamination and processing steps, which increases labor and scrap costs.

The additional process steps in mSAP — seed layer preparation, precise photoresist application and patterning for the plating mask, electroplating with tight thickness control, resist stripping, and flash etching with narrow process windows — each add cycle time and require specialized equipment. The flash etch step in particular demands precise timing and chemistry control, because over-etching the seed layer will damage the trace edges while under-etching leaves conductive residue that causes shorts.

Process yield is another factor. mSAP process windows are tighter than subtractive, meaning a higher percentage of panels may require rework or scrap, particularly during initial production ramp-up. As production volume increases and the process stabilizes for a given design, yield improves and the per-unit cost premium decreases — but it remains meaningfully above subtractive costs at any volume.

Lead times for mSAP are typically one to two weeks longer than equivalent subtractive constructions, reflecting the additional process steps and the more limited availability of mSAP-capable production capacity. Prototype quantities may see even longer lead times if the design requires material procurement or process qualification.

The Middle Ground — Advanced Subtractive Techniques

Before committing to the cost and complexity of mSAP, it is worth understanding how far advanced subtractive techniques can push conventional processing. In many cases, the design requirements fall in a gray zone between standard subtractive capability and mSAP territory, and advanced subtractive provides a cost-effective solution.

Ultra-thin copper foils are the single most impactful change. Replacing standard half-ounce (17-micron) foil with 5-micron or 9-micron foil dramatically reduces the etch depth and therefore the lateral undercut. With a 5-micron foil and an etch factor of 3.5, the undercut per side is only 1.4 microns — compared to 4.9 microns with half-ounce foil under the same conditions. This transforms the achievable trace geometry. A 38-micron trace on 5-micron foil retains a top width of approximately 35.2 microns, a top-to-bottom ratio of 0.93 that produces a nearly rectangular cross-section with predictable impedance behavior.

Modified etch chemistry further improves the picture. Formulations with enhanced vertical-to-lateral selectivity, sometimes described as anisotropic etch enhancers, can push the effective etch factor from the standard 3.0-3.5 range up to 4.0-4.5 under optimized conditions. These chemistries typically involve additives that preferentially inhibit lateral etching at the copper-resist interface. Combined with ultra-thin foils, modified chemistry extends reliable subtractive capability into the 35-to-40-micron range with production-worthy yield.

Laser direct imaging replaces traditional phototool-based exposure with a focused laser that writes the pattern directly onto the resist. LDI eliminates the dimensional errors introduced by phototool film instability and off-contact exposure, improving feature resolution and registration accuracy. For fine-line subtractive work, LDI is effectively mandatory — the registration and resolution requirements below 50 microns exceed what conventional phototool exposure can reliably deliver.

The combination of ultra-thin foils, modified etch chemistry, and LDI represents the practical frontier of subtractive processing. In our production experience, this combination can reliably produce 38-micron (1.5 mil) trace and space with good yield and impedance control. At 35 microns, yield begins to drop. At 30 microns, we see unacceptable variation in trace geometry and impedance, confirming the crossover point where mSAP becomes necessary.

For designs that fall in the 35-to-50-micron range, advanced subtractive is almost always the right answer. The materials are less expensive, the process is more forgiving, lead times are shorter, and the number of qualified fabricators is larger. Only when the design genuinely requires sub-30-micron features — or when the near-vertical sidewall profile of mSAP is needed for signal integrity reasons even at wider geometries — does the premium for mSAP become justified.

The choice between mSAP and subtractive is ultimately an engineering and economic decision, not a technology preference. Both processes produce excellent PCBs within their capability windows. The key is understanding exactly where those windows overlap, where they diverge, and what your specific design demands. We have run both processes long enough to know that the right answer is always the one that meets your electrical, mechanical, and cost requirements with the best balance of margin and value.

Originally published on AtlasPCB. AtlasPCB manufactures advanced PCBs using both subtractive and mSAP processes for HDI, SiP, and fine-line applications.

PCB Impedance Control Tolerances: A Manufacturer's Guide to plus-or-minus 5%, 7%, and 10% Specifications

AtlasPCBEngineering — Thu, 10 Sep 2026 04:33:29 +0000

Reviewed by AtlasPCB Engineering Team

When engineers specify controlled impedance on their PCB fabrication drawings, the conversation almost always starts with the target value: 50 ohms single-ended, 100 ohms differential, sometimes 75 ohms for video or coaxial interfaces. But after manufacturing thousands of controlled impedance boards every month, we can tell you with certainty that the tolerance you specify around that target matters far more than the target itself. A board designed for 50 ohms that consistently delivers 48 to 52 ohms will outperform a board that averages exactly 50 ohms but swings anywhere from 44 to 56 ohms across a production lot. Understanding what drives those swings, how manufacturing variations compound, and what it actually costs to tighten them is the difference between over-specifying your board and paying a premium for nothing, or under-specifying and chasing signal integrity failures in production.

This guide is written from the factory floor. We are sharing real process data, actual tolerance stack-ups, and the engineering trade-offs we navigate with customers every week.

Why Impedance Tolerances Matter More Than Impedance Values

Most signal integrity problems we trace back to impedance control are not caused by a fabricator missing the target. They are caused by inconsistency within a panel, between panels, or across production lots. The distinction is critical. A design with a 50-ohm target and a measured average of 52.3 ohms is, in almost every practical sense, perfectly fine. The transmission line equations that govern signal behavior care about abrupt changes in impedance along a trace far more than they care about a uniform offset from the design target. A 50-ohm trace that suddenly becomes 55 ohms at a via transition or where a reference plane changes creates a reflection point. That reflection sends energy back toward the source, degrades the eye diagram, and at high data rates can push timing margins into failure. Our internal data from over 6,000 controlled impedance lots in the past year shows that the boards customers reject or RMA for signal integrity reasons almost never have impedance coupon failures. The coupons pass. The problem is that localized impedance variations within the board, driven by trace width changes near pads, dielectric thickness shifts over copper pour areas, or solder mask thickness inconsistencies on outer layers, create reflection points that the coupon cannot capture.

This is why we encourage customers to think about tolerance not as a pass/fail gate on the test coupon, but as a measure of how tightly controlled the manufacturing process is across every inch of copper on the board. A fabricator quoting you ±10% tolerance is telling you something about their process capability on trace width, dielectric thickness, material consistency, and lamination control. A fabricator quoting ±5% is telling you something very different. For a deeper exploration of how stackup design interacts with impedance targeting, see our guide on controlled impedance PCB design and stackup calculations.

The Five Variables That Control Your Impedance and Their Manufacturing Tolerances

Characteristic impedance is a function of geometry and materials. For a microstrip trace, it depends on the trace width, the dielectric thickness between the trace and the reference plane, the dielectric constant of the laminate, and the copper thickness. For outer layers, the solder mask adds a sixth variable by acting as a secondary dielectric layer over the trace. Each of these parameters has an associated manufacturing tolerance, and the aggregate of those tolerances determines the impedance tolerance we can guarantee.

Trace width is the parameter most sensitive to process variation. When we image and etch a trace, the final width depends on the phototool accuracy, the exposure and development process, the etch chemistry and dwell time, and the starting copper weight. For standard production at ±10% impedance tolerance, we hold trace widths to approximately ±0.8 mil on inner layers and ±1.0 mil on outer layers where plating adds variability. Moving to ±7% tolerance, we tighten inner layer trace width control to ±0.5 mil by implementing etch compensation algorithms that adjust phototool dimensions based on measured etch rates for each lot of chemistry. At ±5% tolerance, we add inline optical width measurement after etching with automatic feedback to the etch line, holding trace widths to ±0.3 mil on inner layers.

Dielectric thickness is controlled during lamination. Standard FR-4 prepreg and core materials have a published thickness tolerance from the laminate supplier, typically ±10% for commodity grades. When we laminate a multilayer board, the final dielectric thickness depends on the prepreg resin content, the press cycle temperature and pressure profile, and the copper pattern density on adjacent layers (which affects resin flow). For ±10% impedance work, standard lamination profiles with lot-sampled thickness verification are sufficient. At ±7%, we move to controlled-profile lamination with per-recipe press programs tailored to the specific stackup, and we cross-section every lot to verify dielectric thickness. At ±5%, we source controlled-thickness prepreg from the laminate supplier with a ±5% thickness guarantee and run dedicated press programs with tighter pressure and temperature ramp control.

The dielectric constant, or Dk, of FR-4 varies with resin content, glass style, and frequency. Standard FR-4 has a published Dk of approximately 4.2 to 4.6 at 1 GHz, but the actual value for a given lot can shift by ±3 to 5% from the nominal. For ±10% impedance work, this variation is absorbed into the overall tolerance budget. For ±7% and tighter, we specify controlled-Dk laminates such as Isola FR408HR, Panasonic Megtron 4, or similar materials where the supplier certifies Dk to within ±2% and provides lot-specific Dk data that we feed into our impedance modeling software.

Copper thickness after plating on outer layers can vary by ±10 to 15%, adding impedance variation particularly for microstrip geometries where the copper cross-section directly affects the impedance calculation. At tighter tolerance tiers, we control plating thickness through anode configuration, plating current density regulation, and coupon-based thickness verification.

Solder mask on outer layers is often the forgotten variable. A typical liquid photoimageable solder mask adds 0.5 to 1.5 mil over a trace, with a dielectric constant around 3.3 to 3.8. Because the mask thickness varies with trace height and density, it can shift outer layer impedance by 2 to 5 ohms. At tighter tolerance levels, we either account for solder mask in the impedance model explicitly or specify mask thickness ranges on the production traveler.

Tolerance Stack-Up -- How Small Variations Compound Into Big Problems

This is where most impedance discussions fall apart, and where we spend a significant portion of our DFM review time educating customers. Individual parameter variations do not add linearly to produce the total impedance variation. They compound through the sensitivity coefficients of the impedance equation, and they combine statistically. Understanding this stack-up is essential to specifying a tolerance that your fabricator can actually achieve.

Consider a 50-ohm microstrip trace with the following nominal parameters: 5.0 mil trace width, 4.0 mil dielectric thickness, Dk of 4.2, and 1.4 mil copper thickness (1 oz after plating). Using the standard microstrip impedance sensitivity relationships, the impedance depends on trace width with approximately -1.0 sensitivity (a 1% increase in width produces roughly a 1% decrease in impedance), on dielectric thickness with approximately +0.5 sensitivity, on Dk with approximately -0.5 sensitivity, and on copper thickness with approximately -0.2 sensitivity.

Now let us walk through a real stack-up. Suppose each parameter varies by ±2% from nominal. The impedance contributions from each variable are: trace width contributes ±2.0% to impedance variation (2% times the 1.0 sensitivity), dielectric thickness contributes ±1.0%, Dk contributes ±1.0%, and copper thickness contributes ±0.4%. Under worst-case arithmetic addition, where every variable simultaneously hits its worst extreme, the total impedance variation would be ±4.4%. Under root-sum-square (RSS) analysis, which assumes the variations are independent and randomly distributed, the total is the square root of (2.0 squared plus 1.0 squared plus 1.0 squared plus 0.4 squared), which equals approximately ±2.5%.

In practice, the actual variation falls between these two bounds. Some parameters are correlated: thicker copper tends to produce narrower traces after etching because thicker copper requires more etch time and the etchant undercuts further. Other parameters are genuinely independent, like Dk lot variation versus dielectric thickness from a different supplier lot. Our production data suggests the real-world multiplier is approximately 1.3 to 1.5 times the RSS value, putting the actual impedance variation for ±2% individual parameters at roughly ±3.3 to 3.8%.

The implication is stark. To guarantee ±5% total impedance tolerance, you cannot simply hold each variable to ±5%. You need each individual parameter controlled to approximately ±2% or tighter, because the compounding effect will push the total beyond your tolerance window. This is exactly why ±5% impedance tolerance costs significantly more than ±10%. It is not just "tighter specs on paper." It requires fundamentally different process controls at every step from material procurement through final test.

What Changes When You Tighten From ±10% to ±5%

The jump from ±10% to ±7% and then to ±5% impedance tolerance is not a linear tightening of the same process. Each step involves discrete changes in materials, equipment, process flow, and testing methodology.

At ±10% tolerance, which is the standard for most production impedance work, we use commodity FR-4 laminates with published Dk values, standard etch processes with periodic width checks, standard lamination press programs, and batch-sampled impedance coupon testing where we test coupons from a representative subset of panels in the lot. Trace width is controlled to ±0.8 mil on inner layers. Dielectric thickness is verified by cross-section on the first and last panels of a press load. This level of control is sufficient for the vast majority of digital designs operating below 10 Gbps, and it represents the most cost-effective impedance control tier.

At ±7% tolerance, the process changes meaningfully. We switch to controlled-Dk laminates and require lot-specific Dk certification from the laminate supplier. Our impedance modeling uses the actual measured Dk rather than a handbook value. Etch compensation is applied, where we pre-adjust the phototool trace widths based on the measured etch rate of the current chemistry bath, copper weight, and panel thickness. Lamination uses dedicated press programs with controlled ramp rates and dwell times specific to the stackup. Impedance coupon testing moves from batch sampling to per-panel testing, where every production panel has its coupons measured and recorded. Cross-sectioning is performed on every lot, not just sampled lots.

At ±5% tolerance, we layer on additional controls. Inline optical trace width measurement after etching provides real-time feedback, allowing the process engineering team to adjust etch parameters before width drift propagates through an entire lot. Controlled-thickness prepreg with tighter supplier specifications is mandatory. Lamination press programs include thermocouple monitoring of actual board temperature during the cycle, not just platen temperature. Copper plating thickness is verified by coupon measurement on every panel. Solder mask thickness is measured and factored into the impedance model for outer layer traces. The net result is a process where every panel is individually characterized and verified, rather than statistically sampled.

The yield impact is also significant. At ±10%, our typical first-pass yield on impedance coupon testing exceeds 98%. At ±7%, it drops to approximately 94 to 96%, depending on the stackup complexity. At ±5%, first-pass yield ranges from 88 to 93%. Panels that fail coupon testing are scrapped, and that yield loss is built into the pricing. It is not waste or inefficiency; it is the statistical reality of holding tighter windows on interconnected physical parameters.

Common Impedance Failures in Customer Designs

After reviewing thousands of controlled impedance designs, certain failure patterns recur with remarkable consistency. These are the DFM issues that cause impedance problems regardless of how tightly the fabricator controls its processes, because they originate in the design itself.

The most common failure is specifying impedance on outer microstrip layers without accounting for solder mask. A designer calculates a 50-ohm microstrip using an air-dielectric model or a bare-copper model, sends us the fabrication drawing with a 50-ohm requirement, and the board comes back measuring 46 to 48 ohms because the solder mask loading was never included in the calculation. The solder mask effectively increases the capacitance per unit length of the trace, lowering the impedance by 2 to 5 ohms depending on mask thickness and the trace geometry. When we catch this in DFM review, we can adjust the trace width to compensate, but when it slips through, the result is boards that measure low on every single coupon.

The second pattern is inconsistent reference plane distance caused by copper pour density variation. Impedance depends on the distance between the signal trace and its reference plane. In a multilayer stackup, that distance is the dielectric thickness between the signal layer and the adjacent ground or power plane. But if the copper density on the reference plane varies significantly, for example a large void in a ground plane for a connector cutout or a split plane for power isolation, the effective dielectric thickness changes locally because resin fill varies with copper pattern density during lamination. We regularly see designs where the impedance coupon passes perfectly but TDR measurement on the actual board trace shows a 3 to 5 ohm bump where the trace crosses a plane void. The fix is straightforward: maintain continuous reference planes under impedance-controlled traces, and if a plane split is unavoidable, add stitching vias and ensure the stackup provides an alternate reference path.

The third pattern involves trace width changes at pad entries. Many designers allow their EDA tool to neck down an impedance-controlled trace as it approaches a BGA pad or a via pad, creating a short section of narrower (and therefore higher impedance) trace. While a single transition of 0.5 to 1.0 mil width reduction over a 10-mil length seems insignificant at low frequencies, at 16 Gbps and above, these micro-reflections accumulate across dozens of nets and degrade the composite eye opening. We advise designers to maintain controlled impedance trace widths as close to the pad as physically possible and to use teardrop pad entries to create a gradual geometric transition rather than an abrupt step.

The fourth recurring issue is specifying an unrealistic impedance for the chosen stackup. We occasionally receive designs requesting 50-ohm single-ended impedance on a 3.5-mil trace over a 3-mil dielectric, which physically calculates to approximately 43 ohms with standard FR-4. No amount of process control can bridge a 7-ohm gap between what the physics dictates and what the drawing demands. This is why we always run our own impedance modeling during DFM review and flag discrepancies before production begins. For detailed guidance on how to correctly document impedance requirements on your fabrication drawing, see our article on how to specify controlled impedance in your PCB fab drawing.

Glass Weave Effects and Their Impact on Impedance Consistency

The glass reinforcement in FR-4 and most high-speed laminates is not a uniform material. It is a woven fabric of glass fiber bundles with resin-filled gaps between them. The glass fibers have a Dk of approximately 6.2 while the surrounding resin has a Dk of approximately 3.2 to 3.5. This creates a spatially varying dielectric constant across the laminate surface, and whether a given trace runs over a glass bundle or over a resin pocket can shift the local Dk, and therefore the impedance, by a measurable amount.

The magnitude of this fiber weave effect depends heavily on the glass style used in the prepreg and core. Coarse weave styles like 7628, which uses thick glass bundles with wide openings, exhibit the most pronounced Dk variation across the surface because the glass-to-resin ratio changes dramatically over short distances. Finer weave styles like 1080 and 2116 have smaller bundle diameters and tighter spacing, which reduces the Dk spatial variation. The finest styles, such as 1067 and 1035, are sometimes called spread-glass or flat-glass because the bundles are mechanically spread to minimize gaps, creating a nearly uniform Dk distribution across the surface.

For standard ±10% impedance tolerance work, the glass weave effect is generally within the noise of other process variations. The Dk variation due to weave pattern is typically ±1 to 2% for styles like 2116 and 1080, well within the tolerance budget. At ±7% tolerance, we begin recommending that designers avoid routing high-speed differential pairs at angles that cause both traces of the pair to periodically align with the glass weave pattern, which creates a systematic skew between the two traces. Routing differential pairs at a slight angle (typically 5 to 15 degrees) to the warp and weft directions of the glass is sufficient to average out the weave effect.

At ±5% tolerance, and particularly for designs operating above 25 Gbps or requiring tight intra-pair skew control, we recommend specifying spread-glass laminates. Materials like Isola FR408HR with spread-glass construction, Panasonic Megtron 6 (which inherently uses a spread weave), or similar products reduce the surface Dk variation to ±0.5% or less. The cost premium for spread-glass is modest, typically 10 to 20% over standard weave, and for designs that genuinely require ±5% impedance tolerance, the material is already in the controlled-Dk category that the tolerance demands.

Reading Your Impedance Test Report -- What TDR Data Really Tells You

Every controlled impedance board we ship includes a TDR test report, yet many engineers are unsure how to interpret the data beyond checking whether the measured value falls within the tolerance window. Understanding what the TDR waveform actually shows can give you valuable insight into your fabricator's process quality and help you diagnose problems if they arise.

A TDR instrument works by sending a fast-rise-time electrical pulse, typically with a rise time of 20 to 35 picoseconds, down a transmission line and measuring the reflected signal as a function of time. Because the pulse propagates at a known velocity (determined by the dielectric constant), the time axis maps directly to physical distance along the trace. The reflected signal amplitude at each point is proportional to the local impedance. The result is a waveform that shows impedance versus position along the trace, giving you a spatial map of the trace's electrical characteristics.

On a well-manufactured coupon, the TDR waveform will show a launch region where the impedance transitions from the connector to the trace, a stable measurement region where the impedance is flat at the characteristic value, and a termination region where the trace ends (usually in an open circuit, which shows as a rising impedance). The impedance value reported on your test certificate is taken from the stable region, typically averaged over a defined portion of the trace length.

What distinguishes a good report from a merely passing one is the flatness of the stable region. A coupon measuring 49.8 ohms with a variation of ±0.3 ohms across the measurement region indicates excellent process control: the trace width, dielectric thickness, and material properties are uniform along the entire coupon length. A coupon measuring 49.8 ohms average but with ±2.0 ohms of ripple in the stable region technically passes a ±10% tolerance window, but it signals significant process variation that could manifest as localized impedance issues on the production board. When you receive your test report, look beyond the pass/fail verdict. Ask for the TDR waveform plots, not just the summary table, and look for the flatness of the impedance trace, any systematic slope (which could indicate a gradual change in trace width along the etch direction), and reproducibility between coupons on the same panel and across panels in the lot.

The measurement itself also has uncertainty, typically ±1 to 2% depending on the instrument calibration, the coupon launch design, and the measurement environment (temperature affects both the dielectric constant and the trace dimensions). This measurement uncertainty is separate from the manufacturing tolerance and is an inherent limit on how precisely we can verify the impedance. At ±5% tolerance, the measurement uncertainty consumes a significant fraction of the tolerance window, which is another reason why ±5% work demands careful coupon design and rigorous calibration practices.

Cost vs. Tolerance -- Making the Right Engineering Trade-Off

The cost difference between tolerance tiers is real and quantifiable, and it comes from identifiable process changes rather than arbitrary pricing. Understanding where the cost comes from helps you make rational decisions about what your design actually needs.

Moving from ±10% to ±7% tolerance typically adds 10 to 20% to the impedance-related portion of board cost. The primary cost drivers are the material upgrade to controlled-Dk laminates, which carry a 15 to 30% raw material premium over commodity FR-4, and the transition from batch-sampled to per-panel impedance testing, which adds test time and operator labor to every panel. The etch compensation step adds a small per-lot engineering cost but amortizes well across panels.

Moving from ±7% to ±5% adds another 15 to 25% on top of the ±7% pricing. The additional cost comes from inline optical measurement equipment amortization, tighter-specification prepreg with corresponding supplier premiums, per-panel cross-sectioning on complex stackups, and the yield loss from tighter acceptance criteria. At ±5%, we reject 5 to 10% more panels at impedance testing compared to ±10%, and those scrapped panels represent material, processing, and machine time that must be recovered across the passing boards.

The practical decision framework we recommend to customers is straightforward. If your signal integrity simulation shows adequate margin at ±10% tolerance, specifying tighter tolerance adds cost without improving electrical performance. Most digital designs operating at data rates below 10 Gbps fall into this category, including standard DDR4 interfaces, USB 3.2, and SATA. Designs operating at 16 Gbps and above, including PCIe Gen 5, DDR5, and 25G Ethernet, benefit from ±7% tolerance because the tighter impedance consistency provides margin against the reduced timing and voltage budgets at these speeds. Only applications with specific technical requirements for ±5% should specify it: RF front-ends where impedance matching directly affects power transfer and noise figure, precision instrumentation where phase matching between channels is critical, and specialized high-frequency analog circuits. For a detailed breakdown of how these tolerance tiers affect pricing across different board configurations, refer to our article on controlled impedance PCB pricing and cost optimization.

The worst outcome is specifying ±5% tolerance "just to be safe" on a design that would work perfectly at ±10%. You pay a 25 to 40% premium on impedance-related costs, your lead time increases because tighter-tolerance work requires dedicated scheduling and material procurement, and you gain zero functional benefit. Conversely, specifying ±10% on a 28 Gbps SerDes link to save cost can lead to yield problems at the system level that dwarf the PCB cost savings. The right answer is always driven by your signal integrity analysis, not by habit or fear.

We review every controlled impedance order for tolerance appropriateness as part of our standard DFM process. If we see a design where the specified tolerance is either unnecessarily tight or potentially too loose for the signal speeds involved, we will flag it and discuss the trade-offs before production begins. That conversation costs nothing and can save significant time and money in both directions.

Originally published on AtlasPCB. AtlasPCB specializes in controlled impedance PCB manufacturing for high-speed digital and RF applications.

PCB Assembly Process: What Actually Happens on the Production Floor (Step-by-Step)

AtlasPCBEngineering — Mon, 07 Sep 2026 00:13:05 +0000

The PCB assembly process is where a fabricated board becomes an electronic system — and it's also where the majority of quality problems in electronics manufacturing originate. As engineers at a PCB manufacturing facility, we see both the good and the bad every day: perfectly organized file packages that fly through production, and ambiguous designs that sit in our engineering queue generating clarification emails.

This guide walks through the assembly process from the manufacturer's perspective, with real parameters from our production floor.

PCB Assembly vs. PCB Fabrication

These are often confused in conversation, but they're fundamentally different operations. PCB fabrication creates the bare board — etching copper traces, laminating layers, drilling holes, applying surface finish. PCB assembly (PCBA) populates that bare board with components and creates permanent solder connections.

A board can be perfectly fabricated and still fail assembly because the design decisions that affect assembly quality — pad geometry, component spacing, fiducial placement — are different from those that affect fabrication quality.

The Data Package Your Assembler Needs

Assembly begins with a data review, not solder paste. A complete package includes:

Bill of Materials (BOM) — with manufacturer part numbers, reference designators, and DNP positions explicitly marked
Pick-and-place/centroid file — X/Y coordinates and rotation for every component
Assembly drawing — component outlines, polarity indicators, pin-one markings
Gerber paste mask layers — defines stencil apertures

The most common error we see? A mismatch between coordinate origins in the centroid file and the Gerber data. Always confirm your centroid references the same origin and unit system as your Gerber files.

Design for Assembly (DFA) — Don't Skip This

Most engineers know DFM for bare boards. Fewer apply the same rigor to DFA, and the consequences show up as placement errors and yield losses.

Key DFA considerations:

Component spacing: Minimum 0.5mm between body edges for standard packages, 1.0mm when tall components are adjacent to short ones
Fiducial marks: Global fiducials (3 per panel) for optical registration, plus local fiducials near fine-pitch ICs and BGAs
Panelization: Rail width, breakout tabs, panel fiducials, and tooling holes all affect assembly efficiency

Solder Paste Printing

A laser-cut stainless steel stencil deposits paste onto every SMT pad. Stencil thickness selection matters:

Board Type	Stencil Thickness	Reasoning
Standard pitch (0805+)	5 mil (0.127mm)	Standard paste volume
Fine pitch (<0.5mm)	4 mil	Prevents bridging
Mixed (fine + large)	Stepped stencil	Different regions need different volumes

After printing, every board goes through solder paste inspection (SPI) — arguably the most important inspection point in the entire line. A paste defect caught here costs nothing to fix. The same defect caught after reflow means rework or scrap.

For a 0402 component, the acceptable paste volume per pad is approximately 0.02 to 0.04 cubic millimeters. That's a tight window.

Pick-and-Place

Modern equipment places 40,000+ components per hour for chip-scale parts. Most lines split the work: a high-speed chipshooter handles passives and small semiconductors, while a flexible placer handles large and odd-form components.

For BGAs, the machine's vision system inspects each component before placement — checking lead coplanarity, ball diameter consistency, and orientation. A BGA with one oxidized or missing ball gets caught here rather than becoming a hidden defect after reflow.

Reflow Soldering: The Critical Profile

A typical lead-free SAC305 reflow profile:

Phase	Temperature	Duration	Purpose
Preheat	Ambient → 150°C	1-2°C/sec ramp	Equalize temperature
Soak	150-200°C	60-120 sec	Activate flux, remove volatiles
Reflow	Peak 235-250°C	40-90 sec above 217°C liquidus	Form solder joints
Cooling	217°C → ambient	2-4°C/sec	Controlled solidification

The peak temperature is constrained by the most temperature-sensitive component — most ICs are rated to 260°C max for lead-free processing. That leaves a relatively narrow process window.

Our process engineers use thermocouple-instrumented test boards matching the actual production board's thermal mass to develop and validate each profile.

Through-Hole and Mixed Technology

Through-hole components are inserted after SMT reflow, then soldered via:

Wave soldering — efficient for many THT parts, but requires masking bottom-side SMT components
Selective soldering — programmable nozzle applies solder only to specific locations, eliminates masking
Pin-in-paste (intrusive reflow) — paste printed into THT pads, components inserted before reflow

Pin-in-paste eliminates the separate soldering step entirely but requires careful paste volume control.

Common Defects and Root Causes

Tombstoning: One end of a small passive lifts during reflow. Caused by unequal paste volume, asymmetric pad size, or uneven thermal exposure. Fix: symmetrical pad design and equal copper connections to both pads.

Bridging: Solder spans between adjacent pads. Caused by excess paste, insufficient solder mask dam, or component misalignment. Minimum solder mask dam: 0.1mm standard, 0.075mm advanced.

Head-in-pillow (BGA): Ball and paste both melt but fail to merge — looks normal but is electrically unreliable. Caused by package warpage during reflow. Only detectable by X-ray. This one keeps assembly engineers up at night.

What Drives Assembly Cost

The factors engineers can actually control during design:

Component count — every additional part adds placement time, feeder positions, and potential defect sites
Technology mix — adding BGAs requires X-ray inspection; adding THT requires a separate soldering step
Single vs. double-sided — double-sided roughly doubles processing time
Volume — stencil, programming, and process development are fixed costs that amortize over the run

A simple single-sided SMT board with <50 components might cost $2-5/board in moderate volume. Mixed-technology boards with BGAs and through-hole connectors cost significantly more.

The Bottom Line

The most effective way to improve assembly yield is to engage your assembly partner early in the design cycle. A DFA review before layout is finalized costs nothing and can prevent thousands of dollars in rework and schedule delays.

This article was originally published on the AtlasPCB Engineering Blog. We offer complimentary DFA review on every assembly order.

PCB Manufacturing Files: What Your Manufacturer Actually Needs and What Gets Your Order Delayed

AtlasPCBEngineering — Sun, 06 Sep 2026 00:33:08 +0000

Reviewed by AtlasPCB Engineering Team

Every PCB begins its manufacturing journey the same way: a zip file lands in a CAM engineer's inbox. What happens in the next thirty minutes determines whether your boards ship on schedule or whether your order enters a holding pattern of clarification emails, engineering questions, and preventable delays. The PCB design file handoff is the single most consequential moment in the manufacturing timeline, and yet it is the step that receives the least attention from most design teams.

At AtlasPCB, we process hundreds of new file packages every week. Some arrive perfectly organized, with clear naming conventions, a complete fabrication drawing, and every layer accounted for. Those orders move from intake to production in under an hour. Others arrive as a jumble of ambiguously named files, missing critical information, or containing conflicting data from multiple revisions. Those orders sit in our engineering queue while we compose emails, wait for responses, and try to reconstruct the designer's intent from incomplete evidence.

This article is written from the manufacturer's side of the table. We are going to walk you through exactly what PCB manufacturing files we need, what we check first when your package arrives, what mistakes cause the most delays, and how to assemble a file package that moves through our facility without a single hold. If you design PCBs for a living, this is the article that will save you days on your next order.

What Happens When Your Files Hit Our CAM Department

When we receive your file package, the clock starts immediately. Our CAM department operates on a first-in, first-out basis for file review, and every minute spent on clarification is a minute your order is not moving toward the production floor. Understanding what happens inside our facility during those first thirty minutes will change how you think about file preparation.

The first step is import. Your zip file is extracted and loaded into our CAM software, which for most modern fabricators is either Ucamco Integr8tor, Valor Genesis, or a similar platform. The software attempts to auto-detect layer types based on file extensions and naming conventions. If your files are named clearly — GTL for the top copper layer, GBL for the bottom, GTS and GBS for solder masks — the import is seamless. If your files are named "Layer1.gbr," "Layer2.gbr," and so on, the CAM engineer must open each one individually, inspect the geometry, and manually assign layer types. This alone can add fifteen to twenty minutes to the review, multiplied across every job in the queue that day.

Once the layers are imported and assigned, the software runs an automated design-for-manufacturing check. This DFM analysis examines trace widths, clearances, annular ring sizes, acid traps, solder mask dams, drill-to-copper distances, and dozens of other parameters against the capabilities of our specific production line. Violations are flagged, categorized by severity, and compiled into a report. Minor violations — a trace that is 0.1 mil below our standard minimum, for example — are typically noted but not held. Critical violations, such as a drill hole that overlaps a copper feature on an adjacent layer or a solder mask dam below our minimum opening, will stop the job until we hear from you.

The next stage is the impedance and stackup review. If your fabrication drawing specifies controlled impedance requirements, our engineers model the stackup in a field solver, verify that the dielectric thicknesses and trace geometries will achieve your target impedance values, and propose adjustments if necessary. This is one of the areas where a complete file package makes the biggest difference. When you include a stackup drawing with your target impedance values, dielectric preferences, and copper weights clearly noted, our engineers can complete this step in minutes. When that information is missing, we must ask you a series of questions — what material do you want? What impedance targets do you need? What is the finished board thickness? Each round of questions and answers typically costs a full business day.

The final step in the intake process is the generation of a production traveler: the internal document that follows your board through every step of fabrication, from inner layer imaging to final electrical test. A clean file package with all necessary information allows us to generate this traveler on the first pass. An incomplete package means the traveler cannot be finalized, and your order waits.

In our experience, roughly forty percent of incoming file packages require at least one clarification question. Of those, the majority are missing the same few pieces of information: material specification, surface finish preference, impedance requirements, or a complete drill file set. These are not obscure requirements. They are the basics of a complete PCB manufacturing file package, and addressing them before you click "send" is the simplest way to shave days off your lead time.

The Complete PCB Manufacturing File Package

A complete file package contains more than just Gerber files. While Gerber data forms the geometric foundation of your board, it carries almost no manufacturing intelligence — it tells us what your copper looks like, but not what material to build it on, what finish to apply, or what electrical performance you expect. The complete package is a combination of geometry data, mechanical data, manufacturing instructions, and testing specifications that together give our CAM engineers everything they need to build your board correctly the first time.

The core of any file package is the set of Gerber files. At minimum, these should be in RS-274X format, which is the extended Gerber format that includes embedded aperture definitions. The older RS-274D format, which requires a separate aperture wheel file, is still occasionally encountered but creates unnecessary compatibility issues and should be avoided entirely. The newer Gerber X2 format is preferred when your EDA tool supports it, because it embeds layer type attributes directly in the file header, which eliminates guesswork during import. For a comprehensive treatment of Gerber formats and best practices, see our Gerber files guide.

Your Gerber set should include one file for every copper layer in your design, top and bottom solder mask files, at least one silkscreen file (top is standard; bottom is needed if you have bottom-side component markings), top and bottom paste mask files if your design will be assembled, and a board outline or mechanical layer file. For a standard four-layer board, that translates to a minimum of ten Gerber files: four copper layers, two solder masks, one or two silkscreens, two paste masks, and a board outline. Missing any one of these files will trigger a hold.

NC drill files in Excellon format are the second essential component. These files define every hole in your board — through-holes, vias, component mounting holes, and any slots or routed features. If your design includes blind or buried vias, you need separate drill files for each drill span, clearly labeled with the layer pairs they connect. A six-layer board with blind vias from layers one to two and layers five to six, plus through-hole vias from one to six, requires three separate drill files. Confusing these or combining them into a single file is a common source of manufacturing errors that can result in scrapped panels.

The fabrication drawing is, in our professional opinion, the single most important file in the package — and the one most frequently omitted or incomplete. We discuss this file in detail in its own section below and in our dedicated fab drawing checklist, but the essential point is this: the fabrication drawing is where you communicate everything that the Gerber data cannot. Material type, stackup specification, surface finish, copper weight, board thickness, impedance requirements, special tolerances, and any non-standard processes are all conveyed through the fab drawing. Without it, we are guessing — and we will not guess with your boards.

Stackup requirements deserve special mention, even when included in the fab drawing. If your design has controlled impedance requirements or specific dielectric material preferences, providing a dedicated stackup document dramatically accelerates our engineering review. Even a sketch showing your target layer order, copper weights, and dielectric thicknesses gives our engineers a starting point. We regularly receive designs where the only stackup information is "FR-4, 1.6mm," which tells us almost nothing about how to distribute the dielectric thickness across a multilayer construction. Our article on reading and specifying PCB stackup drawings covers this topic in depth.

The IPC-D-356 netlist file is the final component that separates a good file package from a complete one. This file defines the electrical connectivity of your board — which pads should be connected, which nets exist, and what the expected continuity should be after fabrication. We use this file to program our flying probe and bed-of-nails electrical test fixtures. Without it, we can only perform a basic continuity check against the Gerber-derived netlist, which is less reliable and cannot catch certain classes of design errors. Including the IPC-D-356 file does not add any effort on your end — every major EDA tool can generate it in seconds — but it significantly improves the quality of your final boards.

To summarize what is truly mandatory versus what is strongly recommended: copper layers, solder masks, silkscreen, board outline, NC drill files, and a fabrication drawing with material and finish specifications are non-negotiable. Paste mask files, the IPC-D-356 netlist, and a dedicated stackup document are strongly recommended and will accelerate your order. Assembly drawings and pick-and-place files are needed only if you are ordering turnkey assembly.

Gerber File Details Your Manufacturer Actually Checks

Beyond verifying that every required layer is present, our CAM engineers perform several detailed checks on your Gerber files that most designers never think about. Understanding these checks will help you catch problems before they reach our facility.

Layer naming conventions matter far more than most designers realize. When your files arrive with names like "PCB_Project_v3_final_FINAL2_TopCopper.gbr," our CAM software cannot auto-detect the layer type, and our engineers must open the file, visually inspect the geometry, and manually assign it. Worse, when similar names are used inconsistently across revisions or when a zip file contains both "TopCopper.gbr" and "Top_Copper_rev2.gbr," we have no reliable way to know which is current without asking you. The simplest approach is to use the standardized extensions that your EDA tool generates by default — .GTL, .GBL, .GTS, .GBS, .GTO, .GBO for Gerber files, and .DRL or .XLN for drill files — and to never include more than one version of any file in your submission.

Aperture list consistency is checked automatically during import. In the RS-274X format, aperture definitions are embedded in the file header, so this is rarely an issue. However, we still occasionally receive files where the aperture definitions in the header do not match the aperture calls in the body, usually as a result of manual editing or file corruption during transfer. If our import process flags aperture inconsistencies, we must put your order on hold to verify the correct data.

Solder mask openings versus pad sizes represent one of the most common geometric issues we encounter. The standard solder mask expansion — the amount by which the mask opening exceeds the pad — is typically 2 to 3 mils per side for standard surface-mount pads. When we see a file where the mask openings exactly equal the pad sizes (zero expansion) or where the mask openings are smaller than the pads (negative expansion), we flag it immediately. Sometimes this is intentional, as in the case of solder mask-defined pads for BGA components, but more often it is a configuration error in the EDA tool's design rules. In either case, we need confirmation from you before proceeding.

The paste mask file is a separate file from the solder mask, and confusing the two is a surprisingly common mistake. The solder mask defines the areas of the board where the green (or other color) coating is removed to expose copper for soldering. The paste mask defines the stencil openings for solder paste application during assembly. They look similar at a glance, but the paste mask typically has reduced openings (especially for fine-pitch components) and may include modifications like home-plate or window-pane patterns for thermal pads. If you send the solder mask file labeled as the paste mask, or vice versa, the assembly process will fail. In our facility, we catch this during the CAM review by overlaying both files and checking for the expected dimensional differences, but this check takes time and delays your order if corrections are needed.

The question of panelized versus single-board Gerbers comes up frequently. Unless you have specific panelization requirements — custom panel dimensions, particular arrangements for flex or rigid-flex boards, or fiducial placement preferences — you should send single-board Gerber data and let your manufacturer handle panelization. Our panel engineering team optimizes panel utilization to minimize waste, which often results in lower per-board cost than a customer-specified panel layout. If you do need to control the panelization, send both the single-board Gerbers and your panel drawing, and include clear notes about breakaway tab locations, V-score lines, and any keep-out areas for tooling holes.

The Fabrication Drawing — The Most Underrated File in Your Package

If there is one message we could send to every PCB designer in the world, it would be this: the fabrication drawing is not optional. It is the single most important communication tool between you and your manufacturer, and its absence is the number one cause of preventable delays in our facility. The Gerber files tell us the geometry of your board. The fabrication drawing tells us everything else.

A good fabrication drawing specifies the base material, typically by laminate designation such as FR-4 (with the specific grade, such as IT-180A or S1000-2, if you have a preference), or by performance requirement such as "mid-Tg halogen-free" if you are flexible on the exact brand. It includes the finished board thickness with tolerance, the copper weight for each layer (especially important when inner layers differ from outer layers), the surface finish (HASL, ENIG, OSP, immersion silver, or immersion tin), and any controlled impedance requirements with target values, reference layers, and tolerance bands.

What belongs on the fab drawing versus what the Gerber data already covers is a distinction worth understanding. The Gerber files define geometry: trace locations, pad shapes, solder mask openings, silkscreen graphics, and the board outline. The fabrication drawing defines process: what materials to use, how thick to make each layer, what finish to apply, what electrical performance to achieve, and what standards to inspect against. There is some overlap — the board outline appears in both, and drill information is in the NC files — but the fabrication drawing is the authoritative source for manufacturing intent. When the fab drawing and the Gerber data conflict (and they sometimes do), we follow the fab drawing and contact you to resolve the discrepancy.

Tolerances are an area where many designers either over-specify or under-specify, both of which cause problems. Over-specifying means calling out tolerances tighter than standard manufacturing capability, which forces us to either reject the requirement and ask for a revision or apply non-standard processes that increase cost and lead time. Under-specifying means providing no tolerance information at all, which forces us to apply our standard process tolerances — which may or may not meet your functional requirements. The best approach is to specify tolerances only where they matter for your design's function and to explicitly state "manufacturer's standard" for everything else. Board thickness, for example, carries an IPC standard tolerance of plus or minus ten percent, which is sufficient for the vast majority of applications. If your design requires tighter control — for a connector interface or a press-fit housing, for instance — call it out specifically and explain why, so we can plan accordingly.

Real examples from our production floor illustrate the impact of a well-prepared fabrication drawing. We recently processed a twelve-layer HDI design where the designer included a detailed fab drawing specifying Megtron 6 material, a precise stackup with impedance targets for four different trace geometries, ENIG finish with specific gold thickness requirements, and via fill with planarization for the microvias. Our CAM engineer completed the entire review, impedance modeling, and stackup finalization in forty-five minutes, and the order moved to production the same day. The following week, we received a comparable twelve-layer design with no fab drawing at all — just Gerber files and drill data in a zip file. It took three rounds of email over five business days to collect the missing information, during which the order could not proceed. Both designs were similar in complexity. The difference in lead time was entirely attributable to the file package.

The difference between a good fab drawing and one that causes three rounds of email often comes down to specificity. A fab note that reads "FR-4 material, ENIG finish, 1.6mm thick, 1oz copper" is adequate for a simple two-layer board. For anything more complex, we need more detail: which FR-4 grade, what Tg rating, what impedance targets (with the specific layers and trace widths), whether the 1oz copper is on all layers or just the outer layers, and whether "1.6mm" includes or excludes the surface finish thickness. These may seem like minor details, but each unspecified parameter generates a question, and each question adds time.

Common File Mistakes by EDA Tool

Every EDA tool has its own export workflow, default settings, and quirks that can introduce errors into your manufacturing files. At our facility, we see patterns that repeat predictably based on the design tool used, and knowing these tool-specific pitfalls can help you avoid the most common traps.

KiCad users encounter three recurring issues. The first is drill file format settings. KiCad's plot dialog offers multiple drill file formats and unit systems, and the default settings do not always produce files that align perfectly with the Gerber output. Specifically, if your Gerber files are generated in metric units but your drill file is exported in imperial (or vice versa), the hole locations will not register correctly with the pad locations when we import them. Always verify that your drill file units match your Gerber units. The second issue is the missing Edge.Cuts layer. KiCad uses a dedicated layer called Edge.Cuts for the board outline, and some designers forget to include it in their Gerber export or accidentally export the User.Comments layer instead. Without the correct board outline, we cannot determine the board dimensions or the routing path for depanelization. The third issue is a general metric-versus-imperial confusion that manifests in various ways — coordinate offsets, aperture sizes, or grid alignments that do not match between files.

Altium Designer produces generally clean output, but two issues appear repeatedly. The ODB++ export from Altium occasionally includes layer mapping errors, particularly when the designer has renamed layers from Altium's defaults or when the design uses non-standard layer configurations. If you export ODB++ from Altium, verify the layer mapping in the export dialog before generating the output, and include a standard Gerber set as backup. The second issue is layer naming. Altium allows complete freedom in layer naming, and designers often use project-specific names like "PowerPlane_3V3" or "Signal_HighSpeed_1" that, while meaningful within the design environment, do not correspond to any standard naming convention that CAM software can auto-detect. A simple readme file listing the layer names and their physical order in the stackup eliminates this ambiguity entirely.

Eagle users must contend with a legacy issue that persists in older versions and older tutorial workflows: the default Gerber output format in some Eagle configurations is RS-274D, the obsolete format that requires a separate aperture file. Modern Eagle versions default to RS-274X, but if you are following an older tutorial or using a legacy CAM processor job, you may inadvertently generate 274D output. Always verify that your export settings specify "RS-274X" and that the aperture definitions are embedded in the file rather than in a separate .APR or .WHE file.

OrCAD and Allegro present unique challenges due to their complex naming conventions and the way they handle multi-board panels. Allegro's default Gerber output uses long, descriptive filenames that often include the full layer name, the date, and other metadata, resulting in names like "design_top_copper_20260905.art" that can confuse automated import routines. More significantly, when designers export panelized designs from Allegro, the resulting Gerber files sometimes contain both the panel outline and the individual board outlines, leading to ambiguity about which outline defines the manufacturing boundary. Clear documentation in your fab drawing resolves this, but the files themselves can cause confusion without it.

Across all EDA tools, the two most universal mistakes are sending the wrong revision and packaging files in a way that creates ambiguity. Sending the wrong revision happens more often than anyone wants to admit — a designer updates the layout, regenerates one or two Gerber files, but forgets to regenerate the entire set, resulting in a package where the copper layers reflect revision C but the solder mask and drill files are still from revision B. The safest practice is to always regenerate the complete file set from scratch for every submission, delete the output directory before export, and include a version identifier in the zip file name. As for packaging, one zip file with one flat directory containing all files is ideal. Nested zip files, duplicate directories, files scattered across subdirectories, or "old" and "new" folders within the same archive all invite confusion.

IPC-2581 and ODB++ — When Smart Formats Actually Help

The Gerber format, for all its ubiquity, is fundamentally a geometry format. It describes shapes on layers. It does not inherently carry information about netlist connectivity, component placement, material requirements, stackup definitions, or manufacturing process parameters. Two newer formats — IPC-2581 and ODB++ — were designed to address these limitations by packaging all of that intelligence into a single, structured data set. For a detailed comparison, see our article on IPC-2581 versus Gerber.

IPC-2581 is an open, XML-based standard that encapsulates the complete board definition in a single file. It includes the layer geometry (equivalent to Gerber data), the netlist (equivalent to the IPC-D-356 file), the stackup definition (equivalent to the fabrication drawing's stackup section), component placement data (equivalent to a pick-and-place file), and bill-of-materials information. In theory, a single IPC-2581 file replaces the entire traditional file package. ODB++ is a similar concept developed by Mentor Graphics (now Siemens) that uses a directory structure rather than a single file, but carries comparable information density.

The practical benefit of these formats is significant when they work. Because the netlist is embedded, our CAM software can perform a true design-versus-netlist verification during import, catching shorts and opens that might not be apparent from geometric inspection alone. Because the stackup definition is included, our engineers can skip the back-and-forth about material and layer construction. Because component data is present, the transition from bare board fabrication to assembly is seamless, with no additional file exchange required.

The caveat is that not every manufacturer's CAM system can fully utilize these formats. At AtlasPCB, our toolchain supports both IPC-2581 and ODB++ import, and we encourage their use. However, we have seen cases where the IPC-2581 output from a particular EDA version contains formatting inconsistencies that our parser cannot resolve, or where the ODB++ export omits certain layer types that were present in the original design. For this reason, our standing recommendation is to include your smart format file (IPC-2581 or ODB++) as the primary data source but to always include a complete Gerber and Excellon drill set as backup. This dual-submission approach takes only a few extra minutes and provides a reliable fallback if any import issue arises with the smart format.

The practical impact on turnaround time is measurable. Orders submitted with a well-formed IPC-2581 or ODB++ file package, accompanied by a Gerber backup, average roughly twenty percent fewer engineering questions during CAM review compared to Gerber-only submissions. That translates directly to faster throughput and fewer delays. If your EDA tool supports these formats — and Altium, Cadence, Siemens Xpedition, and recent versions of KiCad all do to varying degrees — the small investment of time in learning the export workflow pays for itself on the first order.

A Manufacturer's Pre-Submission Checklist

After years of processing file packages ranging from immaculate to incomprehensible, our engineering team has distilled the ideal submission into a ten-point checklist. This is, quite literally, the manufacturer's wishlist — the ten things that, if every designer did them, would eliminate the vast majority of delays we see.

First, verify that your Gerber set is complete. Open every file in a Gerber viewer (GerbView, KiCad's viewer, or any free alternative) and confirm that every copper layer, both solder masks, at least one silkscreen, both paste masks, and the board outline are present and visually correct. Do not trust the export log alone — actually look at the files.

Second, confirm that your drill files match your Gerber data. Load both the Gerber files and the drill files into the same viewer session and verify that holes align with pads. Check the unit system — if your Gerbers are in millimeters, your drill files should be in millimeters. Verify that you have separate drill files for each drill span if your design includes blind or buried vias.

Third, include a fabrication drawing or a comprehensive set of fabrication notes. At minimum, specify the material type, board thickness, copper weight for each layer, surface finish, and any impedance requirements. If your design is straightforward, a text file with these parameters is acceptable. For anything above four layers or with controlled impedance, a proper drawing is strongly recommended.

Fourth, include your stackup requirements. Even if they are also in the fab drawing, a dedicated stackup document or table that lists each layer, its material, its thickness target, and the associated impedance specifications (if any) dramatically accelerates our engineering review.

Fifth, include the IPC-D-356 netlist. This takes seconds to generate from any EDA tool and enables us to perform comprehensive electrical testing on your finished boards.

Sixth, name your files using standard conventions. Use the default extensions from your EDA tool, or adopt a consistent naming scheme that identifies the layer type unambiguously. Include a readme file if your naming is non-standard.

Seventh, remove all old revisions from your submission. Your zip file should contain exactly one version of each file. If you need to reference a previous revision, note it in your fabrication drawing or cover email, but do not include the old files in the same package.

Eighth, package everything in a single zip file with a flat directory structure. Do not nest zip files within zip files. Do not scatter files across multiple subdirectories. One folder, all files, clearly named. Name the zip file with your project name and revision identifier: "ProjectName_RevC_20260906.zip" is ideal.

Ninth, label your revision explicitly. Include the revision identifier in the zip file name, in the fabrication drawing, and ideally in the Gerber title block. When we receive a file package, we need to know with certainty which revision it represents, especially if this is not your first submission for this design.

Tenth, send the files once, to one point of contact, through one channel. Do not send partial updates via email while the full package is uploading through the web portal. Do not send a correction to the sales team and the original to the engineering queue. One complete package, one submission, one channel. If you discover an error after submission, send a complete replacement package labeled as the new revision — not a single corrected file intended to be swapped into the original set.

These ten practices are not burdensome. Most of them take less than a minute. Together, they represent the difference between an order that flows through our facility without interruption and one that languishes in engineering hold while your lead time quietly extends.

The PCB design file handoff is not glamorous engineering work. It does not involve clever circuit design or elegant layout techniques. But it is the bridge between your design intent and the physical boards that arrive at your door, and the quality of that bridge determines whether you receive your boards on time, built to specification, and ready for assembly — or whether you spend the next week answering emails about missing files. At AtlasPCB, we have seen both outcomes thousands of times, and the deciding factor is almost always the same: a complete file package, submitted correctly, with clear documentation of your manufacturing intent.

Take the ten minutes to prepare your files properly. Your manufacturer — and your project schedule — will thank you.

Originally published on AtlasPCB Engineering Blog. We manufacture multilayer PCBs with full DFM review, impedance simulation, and stackup optimization for high-speed, RF, and HDI applications.

How to Read a PCB Stackup Drawing: A Manufacturer's Line-by-Line Guide

AtlasPCBEngineering — Sat, 05 Sep 2026 04:33:26 +0000

Every multilayer PCB begins its life as a stackup drawing. Before a single sheet of copper laminate is cut, before the first drill bit spins, and long before your board reaches a reflow oven, the stackup drawing establishes the physical architecture of your circuit board. It defines how many copper layers exist, what separates them, how thick each dielectric is, what impedance targets must be met, and what the finished board thickness will be. Despite its importance, the stackup drawing is one of the most frequently misread documents in the PCB design-to-manufacturing workflow.

At AtlasPCB, our process engineers review hundreds of stackup proposals every month. We see the same misunderstandings repeated across projects — designers who confuse core with prepreg, engineers who approve a stackup without checking whether the proposed Dk values match their simulation frequency, and project managers who do not realize that an asymmetric construction will cause their boards to warp during assembly. This guide walks through every element of a PCB stackup drawing so that you can read, interpret, and confidently approve or challenge the proposal your manufacturer sends you.

Reviewed by AtlasPCB Engineering Team

Why You Need to Understand Your Stackup Proposal

In the standard PCB manufacturing workflow, the designer sends Gerber files, a drill file, and a fabrication drawing to the manufacturer. The manufacturer's process engineering team then proposes a stackup based on the designer's layer count, impedance requirements, material specification, and overall thickness target. This proposal comes back as a stackup drawing — typically a PDF or embedded table — that the designer must review and approve before fabrication begins.

This review step is not a formality. The stackup proposal is the single most consequential document in your design package because it determines whether your impedance targets are physically achievable, whether your board will survive thermal cycling, and whether your finished product fits its enclosure. A stackup that looks reasonable at first glance can contain subtle issues that lead to impedance failures in production, unexpected cost increases due to exotic material combinations, or delivery delays when a proposed prepreg style turns out to be on extended lead time.

The problem is that many designers treat stackup approval as a checkbox rather than an engineering review. They receive the proposal, see that the layer count and total thickness look correct, and reply with an approval. Weeks later, when impedance test coupons fail or boards arrive warped, the root cause traces back to a stackup detail that was visible in the drawing but never questioned. Understanding how to read a PCB stackup drawing transforms you from a passive approver into an active participant in your board's manufacturability. If you are still deciding between four-layer and six-layer constructions, getting comfortable with stackup drawings is an essential prerequisite.

Anatomy of a PCB Stackup Drawing — What Every Line Means

A PCB stackup drawing is a cross-sectional diagram of your board, drawn from top to bottom. Each horizontal line or band represents either a copper layer or a dielectric layer, and annotations alongside each element provide the specifications that govern fabrication. While formats vary between manufacturers, every stackup drawing contains the same fundamental information.

Layer designations appear as labels on the left side of the drawing, numbered sequentially from L1 (the top copper layer) through Ln (the bottom copper layer). A standard eight-layer board will show L1 through L8, with L1 at the top and L8 at the bottom. Some manufacturers use additional naming conventions — labeling layers as "TOP," "GND1," "SIG2," "PWR," "BOT" — to indicate function. These function labels tell you whether each copper layer is intended to carry signals, serve as a ground reference plane, distribute power, or perform a mixed role. Pay attention to these labels because they affect impedance modeling: a signal layer referenced to a solid ground plane behaves differently than one referenced to a split power plane with multiple voltage islands.

Material callouts identify what fills the space between copper layers. Every dielectric region is labeled as either a core or a prepreg, and most drawings include the specific laminate grade — such as FR-4 Tg170, Megtron 6, or IS415 — along with the prepreg style number when applicable. Understanding the difference between prepreg and core is fundamental to reading any stackup drawing, and the next section examines this distinction in detail.

Dielectric thickness is specified in mils or millimeters for each core and prepreg layer, often accompanied by a tolerance range. A typical entry might read "4.5 mil +/- 0.5 mil" for a prepreg layer or "8.0 mil +/- 0.3 mil" for a core. These thicknesses directly determine your impedance values, so even small discrepancies between what the manufacturer proposes and what your field solver assumed will shift your impedance results.

Copper weight is expressed in ounces per square foot, where 1 oz corresponds to approximately 1.4 mils (35 micrometers) of copper thickness. The stackup drawing may list both the base copper weight — the foil thickness before etching — and the finished copper weight after plating. Outer layers typically gain copper during the plating process, so an outer layer that starts as 0.5 oz base copper may finish at approximately 1.0 to 1.2 oz after pattern plating and surface finish. Inner layers remain at their base copper weight since they are etched before lamination and receive no additional plating.

Overall board thickness is stated at the bottom or side of the drawing, usually with a tolerance such as "1.6 mm +/- 10%." This figure includes all copper layers, all dielectric layers, the solder mask on both sides, and the surface finish. Verify that this number matches your mechanical enclosure requirements and connector specifications — a board that comes in at 1.75 mm when your card guide tolerates only 1.7 mm maximum will cause mechanical interference that cannot be corrected after fabrication.

Impedance targets may appear within the stackup drawing itself or in a separate impedance table attached to the same document. They specify the target impedance in ohms, the trace width and spacing required to achieve it, and the reference layer used as the return path. Impedance tables deserve their own discussion, which follows in a later section.

Drill span callouts appear on stackup drawings for boards with blind or buried vias. These annotations show which layers a via connects — for example, "L1-L4 blind via" or "L3-L6 buried via" — and they define the lamination sequence. A board with buried vias requires multiple press cycles, which affects both cost and lead time. If you see drill span callouts on your stackup proposal that you did not request, ask your manufacturer whether they are interpreting your via structure correctly.

Core vs Prepreg — Understanding the Building Blocks

The distinction between core and prepreg is the foundation of stackup literacy, yet it remains one of the most common sources of confusion among designers reviewing a stackup proposal for the first time.

A core is a fully cured, rigid laminate sheet that arrives at the factory with copper foil already bonded to one or both sides. Think of it as a finished, stable building block. The factory etches circuit patterns onto the core's copper surfaces, inspects the results with automated optical inspection, and then stacks the etched cores together with prepreg sheets between them. Because the core is already cured, its thickness is fixed and tightly controlled. When a stackup drawing shows a core at 8.0 mils, you can expect the actual thickness to fall within a narrow tolerance window — typically plus or minus 0.3 mils for thin cores and plus or minus 10 percent for thicker ones.

Prepreg, short for pre-impregnated, is a sheet of woven fiberglass cloth coated with partially cured (B-stage) epoxy resin. During the lamination press cycle, heat and pressure cause the resin to flow, filling the gaps left by etched copper patterns on adjacent layers and bonding everything together into a solid structure. Because the resin flows during pressing, the finished thickness of a prepreg layer depends on how much copper was removed from the adjacent layers. An inner layer with large copper pours leaves less space for resin to fill, so the prepreg finishes closer to its nominal thickness. An inner layer with minimal copper (mostly etched away) creates more void space, and the prepreg resin flows into those voids, making the finished prepreg layer thinner than its nominal specification.

On a stackup drawing, cores and prepregs are visually and textually distinct. Cores are typically shown as solid bands labeled with "Core" and a thickness, while prepregs are shown with a crosshatch or different shading and labeled with the prepreg style number. Common prepreg styles include 1080 (thin, approximately 2.8 mils nominal), 2116 (medium, approximately 4.6 mils nominal), and 7628 (thick, approximately 7.0 mils nominal). Manufacturers choose specific prepreg styles based on the dielectric thickness required for impedance control. When a stackup calls for a 5.0-mil dielectric, the process engineer might select a single sheet of 2116 plus resin content adjustment, or two sheets of 1080 stacked together. Multiple prepreg sheets give more precise thickness control and better resin fill for layers with heavy copper removal.

Another detail worth noting is the distinction between foil construction and cap construction on the outer layers. In foil construction, the outer copper is a thin foil sheet that is laminated directly onto prepreg during the final press cycle. In cap (or core) construction, the outer layers use a thin core with copper on both sides, where the inner copper surface is etched and the outer copper surface becomes the finished outer layer. Cap construction gives tighter thickness control on the outermost dielectric, which is critical for controlled impedance on outer-layer traces. If your design requires tight impedance tolerance on L1 or Ln, check whether your manufacturer's proposal uses foil or cap construction and understand the tradeoff.

Reading Impedance Tables in Your Stackup Proposal

For any design with controlled impedance requirements, the stackup drawing will include an impedance table — either embedded in the drawing itself or delivered as a companion document. This table is where your electrical intent meets your manufacturer's physical implementation, and it demands careful review.

A typical impedance table contains columns for impedance type (single-ended or differential), target impedance value in ohms, trace width, trace spacing (for differential pairs), copper layer, reference layer, dielectric thickness to the reference, and the Dk (dielectric constant) value used in the calculation. Some manufacturers also include their calculated impedance result and the tolerance window, typically plus or minus 10 percent.

Start your review by confirming that every impedance-controlled net class in your design appears in the table. If your design has 50-ohm single-ended traces, 90-ohm differential USB pairs, and 100-ohm differential Ethernet pairs, all three should be listed. Missing entries mean the manufacturer did not model those impedance targets, and the resulting trace geometry may not achieve your required values.

Next, check the trace widths against your design rules. The manufacturer's impedance model may require trace widths that differ from what you assumed during layout. A stackup with a thinner dielectric than you expected will require narrower traces to maintain the same impedance, and if those narrower traces violate your minimum width design rules, you have a conflict that must be resolved before fabrication.

The Dk value listed in the impedance table deserves particular scrutiny. Laminate datasheets typically report Dk at 1 MHz, but the effective Dk at your operating frequency can be significantly different. For standard FR-4 at 1 GHz, the Dk drops from the datasheet value of approximately 4.2-4.5 down to roughly 4.0-4.2. At 10 GHz, the effective Dk for high-speed laminates like Megtron 6 is around 3.6 versus a 1-MHz datasheet value of 3.7. If your manufacturer used the 1-MHz Dk value in their impedance calculation while you simulated at your actual operating frequency, the predicted impedance values will diverge. Ask which frequency their Dk value corresponds to, and if they cannot answer, that is a warning sign about the rigor of their impedance modeling.

Finally, verify the reference layer assignments. A signal trace on L3 referenced to a solid ground plane on L2 will have a different impedance than the same trace referenced to a power plane on L4, even if the dielectric thicknesses are identical, because copper pattern density on the reference layer affects the effective dielectric environment. For impedance-controlled designs, confirming the correct reference layer is non-negotiable.

Five Things to Check Before Approving a Stackup Proposal

After you understand every element on the drawing, a structured review ensures nothing critical slips through. These five checks, performed in order, will catch the vast majority of stackup issues before they become production problems.

First, verify that dielectric thicknesses support your impedance targets. Take the proposed dielectric thickness between each signal layer and its reference plane, plug it into your own field solver along with the manufacturer's proposed trace width and the correct Dk value at your operating frequency, and confirm that the calculated impedance falls within your tolerance window. Do not rely solely on the manufacturer's calculation — they may have used different Dk values, different copper roughness assumptions, or different solver software. Independent verification takes fifteen minutes and can prevent weeks of delay when impedance coupons fail.

Second, confirm that copper weights meet your current-carrying requirements. A stackup proposing 0.5 oz copper on inner power layers may not support the current density your power distribution network requires. Calculate the maximum current each power plane must carry, determine the required trace or plane cross-section using IPC-2152 guidelines, and verify that the proposed copper weight provides adequate margin. Outer layers are less of a concern because plating adds copper, but inner layers get exactly what the stackup specifies.

Third, check that the overall board thickness fits your mechanical constraints. Add up all the layers yourself — every copper thickness, every dielectric thickness, solder mask on both sides (typically 0.5 to 1.0 mil per side), and surface finish (ENIG adds about 0.2 mils, HASL adds more variability). Compare your total to the manufacturer's stated overall thickness. If the numbers do not match, one of you has an error. Also verify that the finished thickness, including tolerances, falls within your enclosure and connector specifications.

Fourth, ensure the proposed material grade matches your thermal and electrical requirements. If your design specifies Megtron 6 for low-loss high-speed signaling, but the stackup proposal shows standard FR-4 Tg170, you have a material mismatch that will cause signal integrity problems. Conversely, if your design only needs standard FR-4 but the manufacturer proposed a specialty laminate, you may be paying a premium without benefit. Check that the laminate grade, Tg rating, and Dk/Df characteristics align with your design intent.

Fifth, confirm that the stackup is symmetrical about the board center. A balanced stackup — where material types, dielectric thicknesses, and copper weights are mirrored around the midplane — prevents warpage during lamination and reflow. Compare the top half of the stackup to the bottom half layer by layer. If L1 has 1 oz copper on a 4-mil prepreg over a ground plane, then the corresponding bottom construction should mirror that arrangement. Asymmetric stackups create differential stress that causes boards to bow and twist, which leads to solder joint failures on fine-pitch BGAs and QFNs. If the proposed stackup is asymmetric, ask the manufacturer for the engineering justification and understand the warpage risk before approving.

When to Push Back on Your Manufacturer's Proposal

Not every stackup proposal deserves an immediate approval. There are specific situations where you should send the proposal back with questions or requested changes, and recognizing these situations is a skill that improves with experience.

The most common reason to push back is a material mismatch. If your fabrication notes specify a particular laminate system — say Isola 370HR for its combination of thermal performance and controlled Dk — and the manufacturer's proposal substitutes a different material without explanation, you need to understand why. Sometimes the substitution is benign: the factory may not stock your specified laminate but offers an equivalent from a different supplier with matching Dk, Df, Tg, and CTE characteristics. Other times, the substitution changes the electrical performance of your board in ways the manufacturer may not have evaluated. Ask for the datasheet of the proposed alternative, compare the key parameters at your operating frequency, and make an informed decision rather than accepting a material change on faith.

Impedance target discrepancies are another trigger for pushback. If the impedance values in the manufacturer's table differ from your design intent by more than the agreed tolerance, the stackup needs revision. This can happen when the manufacturer uses a different stackup arrangement than you assumed in layout — for example, referencing a signal layer to a power plane instead of a ground plane, or using a thinner dielectric that requires trace width changes you have not accounted for in your layout. Resolve these discrepancies before approving rather than hoping the impedance will fall within tolerance during production.

Asymmetric stackups without justification should always prompt a conversation. While there are legitimate reasons for asymmetry — some rigid-flex designs and certain via-in-pad constructions require it — a manufacturer should be able to explain why the proposed stackup is not balanced. If the answer is simply "this is what our standard book stackup looks like," push for a modification that achieves symmetry. The small increase in material cost is almost always cheaper than dealing with warped boards on your assembly line.

Non-standard prepreg combinations that may affect availability are worth questioning as well. If the stackup calls for an unusual combination of prepreg styles — for example, three sheets of 1080 where a single sheet of 2116 plus one 1080 would achieve the same thickness — ask whether the proposed combination offers a tangible benefit or is simply how the software generated the solution. Simpler prepreg combinations mean fewer material line items to procure, which can reduce lead time and price.

Finally, look for cost optimization opportunities the manufacturer may not have suggested. A stackup that uses 2 oz copper on all inner layers when only one power layer actually needs heavy copper is more expensive than it needs to be. A construction that requires three lamination press cycles when a minor rearrangement of blind via spans could reduce it to two will save both time and money. Manufacturers are often conservative in their proposals because the safest stackup for fabrication yield is not always the most cost-effective stackup for you. If you understand the drawing well enough to identify these opportunities, you can negotiate a better balance of performance, reliability, and cost.

Stackup Review Workflow — From Proposal to Production

Integrating stackup review into your project schedule requires treating it as an engineering milestone rather than an administrative step. The most effective workflow follows a clear sequence from initial proposal through final approval, with specific checkpoints that prevent schedule surprises.

The process begins when you submit your fabrication package and the manufacturer returns a stackup proposal. Set a firm internal deadline for completing your review — typically two to three business days. During this window, perform the five-point check described above, run your own impedance simulations against the proposed geometry, and compare the material specification to your design requirements. If the proposal passes all checks, approve it and note the approval date in your project tracker. If it does not, send back specific, actionable feedback rather than vague concerns. "The dielectric between L3 and L4 should be 4.0 mils, not 3.5 mils, to maintain 50-ohm impedance at 5/3.5 trace width/spacing" is far more productive than "please check the impedance."

Once you approve the stackup, you have reached what the industry calls "stackup freeze." After this point, changes to the stackup require a formal revision cycle with a new proposal, new impedance calculations, and potentially new layout adjustments. Stackup changes after freeze are the single most common source of schedule delay in multilayer PCB projects, because every change ripples through impedance modeling, trace width adjustments, design rule checks, and Gerber regeneration. Build adequate time into your project schedule for the initial review so that you get it right the first time, rather than rushing an approval and discovering problems after fabrication has started.

For complex projects with 12 or more layers, hybrid material stackups, or blind and buried vias, consider requesting a pre-production stackup review meeting — a 30-minute call with the manufacturer's process engineer to walk through the proposal line by line. This investment of time pays for itself many times over by catching ambiguities in the drawing, aligning expectations on tolerance and process capability, and building a working relationship with the person who will ultimately oversee your board's fabrication.

The stackup drawing is not just a technical specification — it is the contract between your design intent and the manufacturer's fabrication process. Every line on that drawing translates directly into a physical reality inside your finished PCB. Learning to read it with the same rigor you apply to your schematic review will make you a better designer, a more effective manufacturing partner, and a more confident owner of the boards that carry your designs into production.

Originally published on AtlasPCB Engineering Blog. We manufacture advanced multilayer PCBs with full impedance simulation and stackup optimization for high-speed, RF, and HDI applications.

How to Read a PCB Stackup Drawing: A Practical Guide to Understanding Your Manufacturer Proposal

AtlasPCBEngineering — Sat, 05 Sep 2026 00:58:21 +0000

Reviewed by AtlasPCB Engineering Team

The Document That Defines Your Board

Every multilayer PCB begins its manufacturing life not with copper imaging or drilling, but with a stackup drawing. This document, typically a single page, describes the complete cross-sectional architecture of your board from top copper to bottom copper, specifying every layer of copper and every layer of dielectric material in between. It is the blueprint that determines your impedance values, your signal integrity performance, your thermal behavior during assembly, and ultimately whether your board works or fails.

Most engineers are comfortable designing stackups in their EDA tools. Fewer are comfortable reading the stackup proposal that comes back from their manufacturer, which often uses different conventions, different dielectric values, and sometimes proposes changes the designer did not expect. The gap between what you specified and what your manufacturer proposes to build is where problems hide. Understanding how to read and interpret that proposal is one of the most important skills a hardware engineer can develop, because once you approve a stackup and boards go into production, the construction is locked.

When we send stackup proposals to customers at AtlasPCB, we include every parameter needed to verify the design intent. This guide walks through each element of a stackup drawing, explains what it means from both the designer's and manufacturer's perspective, and provides a practical checklist for reviewing and approving any stackup proposal you receive.

Anatomy of a PCB Stackup Drawing

A stackup drawing presents the board construction as a vertical cross-section. Reading from top to bottom, each row represents either a copper layer or a dielectric layer. Every row carries specific information that defines the manufacturing process. Understanding what each column and annotation means is the first step toward meaningful review.

Layer Designation and Function

The leftmost column in any stackup drawing identifies each copper layer with a sequential number, typically L1 through L6 for a six-layer board or L1 through L10 for a ten-layer design. Adjacent to the layer number, most manufacturers include a function label that describes the intended purpose of that copper layer. Common function labels include Signal for layers carrying routed traces, Ground or GND for unbroken ground reference planes, Power or PWR for power distribution planes, and Mixed for layers that carry both routed signal traces and partial plane areas.

These function labels are not merely decorative. They tell the manufacturer which layers require trace routing with specific width and spacing rules and which layers should remain as continuous copper pours with only anti-pad clearances around vias. When you review a stackup proposal, verify that the function assignments match your design. A layer you intended as a solid ground reference should not be labeled Mixed, because manufacturing processes for plane layers differ from those for signal layers in terms of copper balance and etching compensation.

Dielectric Material Identification

Between every pair of copper layers sits a dielectric material, and the stackup drawing must identify whether that material is a core or a prepreg. This distinction is fundamental to understanding how the board will be constructed, and confusing the two is a common source of misunderstanding between designers and manufacturers.

A core is a fully cured, rigid laminate panel with copper foil already bonded to both sides. It arrives at the factory as a finished product from the laminate supplier. The manufacturer images and etches circuit patterns onto the copper surfaces of the core, creating inner-layer pairs. In the stackup drawing, a core always appears between two copper layers that were processed together as a single unit.

A prepreg, by contrast, is a sheet of woven fiberglass cloth that has been impregnated with partially cured epoxy resin. During the lamination press cycle, heat and pressure cause the prepreg resin to soften, flow into the etched copper pattern on adjacent cores, and then fully cure into a rigid bond. Prepreg is the adhesive that holds the entire multilayer sandwich together. In the stackup drawing, prepreg appears between copper layers that belong to different cores and need to be bonded during pressing.

Understanding the core-versus-prepreg distinction helps you understand why certain dielectric thicknesses are achievable and others are not. A core thickness is fixed by the laminate supplier and cannot be adjusted during manufacturing. A prepreg thickness, however, changes during pressing because resin flows into the copper pattern on adjacent layers, meaning the final pressed thickness depends on the copper density of the neighboring layers.

Dielectric Thickness and Glass Weave Style

Each dielectric row in the stackup drawing specifies a thickness value, usually in mils (thousandths of an inch) or millimeters, along with a glass weave style designation such as 1080, 2116, or 7628. These numbers refer to specific fiberglass cloth constructions defined by IPC standards, and they carry significant implications for both impedance control and signal integrity.

A 1080 prepreg uses a thin, open-weave glass cloth with approximately 65 percent resin content by weight. Because it has more resin and less glass, its dielectric constant is lower, typically around 3.9 to 4.1 for standard FR-4 formulations. A 7628 prepreg uses a thick, tight-weave glass cloth with approximately 42 percent resin content, giving it a higher dielectric constant around 4.4 to 4.6. The 2116 falls between these two extremes with roughly 50 percent resin content and a Dk around 4.2 to 4.4.

When your manufacturer specifies a particular glass weave style in the stackup, they are making a deliberate choice that affects the dielectric constant used for impedance calculations, the pressed thickness tolerance they can achieve, the availability of the material from their suppliers, and the cost of the finished board. A stackup built entirely with 1080 prepreg will have different impedance characteristics than one built with 7628, even if the nominal thickness is the same. Always verify that the glass weave styles in the proposal match the dielectric constant values used in the impedance calculation table.

Copper Weight

Each copper layer in the stackup drawing specifies a copper weight, expressed in ounces per square foot or equivalently in micrometers of thickness. The most common values are half-ounce (17.5 micrometers), one-ounce (35 micrometers), and two-ounce (70 micrometers) copper. The stackup drawing may distinguish between base copper weight, which is the foil laminated to the core or applied during initial layup, and finished copper weight, which includes the additional copper deposited during the plating process.

For outer layers, the plating process typically adds 20 to 30 micrometers of copper on top of the base foil. This means a one-ounce base copper outer layer will have a finished thickness closer to 55 to 65 micrometers. Inner layers do not receive additional plating, so their thickness remains close to the base copper weight. This distinction matters for impedance calculations because trace cross-sectional geometry directly affects characteristic impedance. Make sure you understand whether the copper weights in the stackup drawing refer to base or finished values, and confirm that the impedance simulation used the correct finished thickness.

Overall Board Thickness

Near the bottom or side of the stackup drawing, you will find the total finished board thickness with a tolerance band, typically expressed as a nominal value plus or minus some percentage or absolute dimension. The standard PCB thickness is 1.6 millimeters (63 mils), but designs range from 0.4 millimeters for thin mobile device boards to 3.2 millimeters or more for backplanes and thick power electronics.

The overall thickness is the sum of all copper layers and all dielectric layers after pressing, plus any surface finish contribution. Verify that the proposed thickness fits within your mechanical enclosure constraints, particularly for board-to-board connector mating heights, card-edge connector slot widths, and chassis slot dimensions.

Reading the Impedance Table

The impedance control section of a stackup drawing is where many engineers focus their attention, and rightly so. This table translates the physical construction into electrical performance. A typical impedance table includes the target impedance value in ohms, the trace width and spacing required to achieve that impedance, the reference layer for each controlled signal, and the dielectric constant value used in the calculation.

When reviewing the impedance table, the most important check is comparing the Dk value used by the manufacturer against the Dk value you used in your own simulation. Manufacturers typically use Dk values from the specific laminate datasheet at a frequency relevant to your application, while designers sometimes use a generic FR-4 Dk value of 4.4 that may not match the actual material. A difference of 0.2 in Dk can shift the required trace width by one to two mils, which translates to an impedance error of five to eight percent on the finished board.

If the manufacturer's trace widths differ from yours by more than half a mil, do not simply assume one calculation is wrong. Ask the manufacturer which Dk value they used, at what frequency, and for which specific prepreg or core material. Then re-run your simulation with their values. In our engineering review process at AtlasPCB, we always provide the exact Dk and Df values from the laminate datasheet alongside the impedance calculation so that customers can verify independently using their preferred impedance calculator.

A Practical Example: Reading a Six-Layer Stackup

To make these concepts concrete, consider a typical six-layer stackup proposal for a design with 50-ohm single-ended and 100-ohm differential impedance targets. Working from top to bottom, the stackup might read as follows.

Layer L1 is designated as a Signal layer with one-ounce base copper. Below L1 sits a single sheet of 1080 prepreg at 3.2 mils nominal pressed thickness. Layer L2 is a Ground plane with half-ounce copper. Below L2 is a 0.8-millimeter FR-4 core with half-ounce copper on both sides. Layer L3 is labeled as a Signal layer, and Layer L4 below it is labeled as a Power plane. Between L4 and L5 sits another 0.8-millimeter core with half-ounce copper on each side. Layer L5 is a Ground plane. Between L5 and L6 is a single sheet of 1080 prepreg at 3.2 mils pressed. Layer L6 is the bottom Signal layer with one-ounce base copper.

Reading this stackup, several things become immediately apparent. The construction uses two cores and two prepreg layers, making it a standard press construction with one lamination cycle. The outer signal layers (L1 and L6) are referenced to adjacent ground planes (L2 and L5) through thin 1080 prepreg, giving tight coupling for good impedance control. The inner signal layers (L3 and L4) are separated by a different dielectric, and depending on whether L3 routes referenced to L2 above or L4 below, the impedance characteristics will differ.

Notice the symmetry of this construction. The top half (L1-prepreg-L2-core-L3) mirrors the bottom half (L4-core-L5-prepreg-L6). This symmetry is critical for preventing board warpage during lamination and thermal cycling. If a manufacturer proposes an asymmetric construction, such as using a thicker prepreg on top than on bottom, ask why and request a bow-and-twist analysis.

Five Checks Before You Approve

After you understand what the stackup drawing says, you need to verify that what it says is correct for your design. In our experience reviewing thousands of stackup approvals, these five checks catch the vast majority of issues before they reach production.

The first check is dielectric thickness versus impedance. Take the proposed dielectric thickness between your controlled signal layer and its reference plane, plug it into your impedance calculator along with the manufacturer's Dk value, and confirm the result matches the impedance target within two ohms. If it does not match, either the dielectric thickness or the trace width needs adjustment.

The second check is copper weight versus current capacity. Verify that the copper weight on power and ground layers can handle your maximum sustained current without excessive temperature rise. A half-ounce inner layer carrying two amps through a 10-mil trace will see meaningful heating. If your design has high-current paths, confirm that the proposed copper weight provides adequate margin per IPC-2152 guidelines.

The third check is overall thickness versus your mechanical constraints. Add up all the layers including copper and dielectric to verify the total matches the proposal's stated overall thickness. Then confirm that thickness works within your enclosure, connector, and assembly constraints.

The fourth check is material grade versus your requirements. The stackup drawing should name a specific laminate, such as Shengyi S1000-2 or ITEQ IT-180A. Verify that the specified grade meets your thermal requirements for glass transition temperature, your electrical requirements for Dk and Df at your operating frequency, and any industry-specific requirements such as IPC-4101 slash sheet compliance for aerospace or automotive applications.

The fifth check is construction symmetry. Compare the top half and bottom half of the stackup layer by layer. The materials, thicknesses, and copper weights should mirror around the center. Minor asymmetry in copper density due to different routing densities on different layers is acceptable, but structural asymmetry in dielectric thickness or material type is a red flag for warpage.

When to Push Back on a Proposal

A manufacturer's stackup proposal is a starting point for discussion, not a final decree. There are several situations where pushing back is not just acceptable but necessary.

If the proposed laminate grade does not match your fabrication notes, ask why the substitution was made. Sometimes it reflects material availability, which is a legitimate concern, but you need to understand the impact on Dk, Df, and thermal performance before accepting. If the manufacturer cannot source your specified material, they should propose an equivalent grade with documented property comparison and request your written approval.

If impedance targets in the proposal differ from your design by more than two ohms, do not approve without investigation. Small differences often stem from Dk value discrepancies between your simulation and theirs, which can be resolved by agreeing on the correct value. Larger differences suggest a fundamental stackup issue that could cause signal integrity problems.

If the manufacturer proposes non-standard prepreg combinations to achieve an unusual dielectric thickness, be aware that this may create material procurement delays. A standard 4-layer stackup using common 7628 or 2116 prepreg will have faster delivery than an exotic construction requiring special-order thin prepreg. Ask your manufacturer about material availability before approving an unusual construction.

From Proposal to Production: The Approval Workflow

The stackup approval process should follow a clear workflow that prevents miscommunication. After receiving the stackup proposal from your manufacturer, perform the five checks described above. If everything passes, send written approval to proceed. If anything needs revision, clearly describe the required changes and request an updated proposal. Do not approve a stackup with verbal caveats or conditional notes; the document that gets approved is the document that gets built.

Once approved, the stackup enters what manufacturers call a "stackup freeze." This means the construction is locked for that production order, and changes after this point will incur delays and potentially re-tooling charges. Build the stackup review into your project schedule between design completion and production order placement, and allocate enough time for at least one revision cycle if your design has impedance control or non-standard construction.

The most efficient approach is to engage your manufacturer early, ideally during the stackup design phase rather than after layout is complete. When we work with customers at AtlasPCB, we prefer to review stackup proposals before routing begins so that any material constraints or impedance adjustments can be incorporated into the layout rather than requiring post-layout changes that delay the project.

Understanding your manufacturer's stackup drawing is not about becoming an expert in laminate chemistry or press cycle parameters. It is about being an informed participant in a collaborative process where your design knowledge and their manufacturing expertise combine to produce a board that works the first time. The few hours spent carefully reviewing a stackup proposal can save weeks of troubleshooting failed prototypes and costly re-spins.

FR-4 PCB Material: Properties, Grades, and Specification Guide for Engineers

AtlasPCBEngineering — Fri, 04 Sep 2026 05:59:57 +0000

Reviewed by AtlasPCB Engineering Team

What FR-4 Actually Is — And What It Is Not

Every PCB designer has written "FR-4" on a fabrication drawing. Most assume they are specifying a material. They are not. FR-4 is a grade designation defined by the National Electrical Manufacturers Association under the NEMA LI-1 standard, and it describes a broad class of flame-retardant woven-glass-reinforced epoxy laminates that achieve a UL94 V-0 flammability rating. The designation tells you that the material self-extinguishes within ten seconds after the ignition source is removed and that it uses woven E-glass cloth as its reinforcement fiber. It says nothing specific about the resin chemistry, the glass transition temperature, the dielectric properties, or the thermal decomposition threshold.

The confusion runs deep because the PCB industry has used "FR-4" as shorthand for decades. When an engineer says "standard FR-4 board," they typically mean a 1.6-millimeter-thick laminate with a glass transition temperature around 130 to 140 degrees Celsius, a dielectric constant in the neighborhood of 4.4 at 1 GHz, and a price point at the lowest tier of the laminate market. That mental model was adequate when boards ran at tens of megahertz and assembly used tin-lead solder at 220 degrees Celsius peak reflow. It falls apart for modern designs with lead-free assembly temperatures reaching 260 degrees Celsius, signal frequencies measured in gigahertz, and reliability requirements spanning automotive and medical device lifecycles.

When we receive a bare fabrication note at AtlasPCB that says only "Material: FR-4" with no further qualification, our engineering team must make assumptions about what the designer actually needs. For a simple two-layer consumer board, those assumptions are usually safe. For a ten-layer impedance-controlled design headed for an automotive application, the absence of a specific material callout creates real risk. The fabricator might select a standard-Tg laminate that cannot survive six lead-free reflow cycles. The impedance values might shift by eight to twelve percent if a different resin system is used than what the designer modeled in their stackup calculator.

The physical composition of an FR-4 laminate involves three primary components. The first is woven E-glass fiber cloth, which provides the mechanical backbone of the material. E-glass (electrical-grade glass) is a borosilicate glass formulation with a dielectric constant around 6.1, offering good strength-to-cost ratio for structural reinforcement. The second component is the epoxy resin system, which fills the spaces between glass fibers and bonds adjacent layers together under heat and pressure. This resin is where most of the performance variation occurs between FR-4 grades because different epoxy formulations produce different glass transition temperatures, different dielectric properties, and different thermal stability. The third component is the flame-retardant additive, which in traditional FR-4 is brominated chemistry and in halogen-free variants is a phosphorus or nitrogen-based system.

Understanding that FR-4 is a family rather than a single material is the first step toward specifying your PCB correctly. The next step is understanding the properties within that family that determine whether a specific FR-4 grade will meet your design requirements.

FR-4 Material Properties That Drive Your Design Decisions

The properties that matter most when selecting an FR-4 grade fall into two categories: thermal properties that determine manufacturing and reliability performance, and electrical properties that determine signal integrity performance. Both categories vary significantly across the FR-4 family, and understanding the specific numbers for each property helps engineers make informed material choices. For a deeper exploration of how to read and compare laminate datasheets across all these parameters, our guide to PCB laminate datasheet parameters provides detailed methodology.

Glass Transition Temperature

Glass transition temperature, abbreviated Tg, is the temperature at which the epoxy resin transitions from a rigid glassy state to a softer rubbery state. This transition is not a melting point and it is not a maximum operating temperature, but it marks a critical threshold where the material's coefficient of thermal expansion in the Z-axis increases dramatically, typically by a factor of three to five. Below Tg, the Z-axis CTE of FR-4 ranges from 50 to 70 parts per million per degree Celsius. Above Tg, that number jumps to 250 to 300 parts per million per degree Celsius. This expansion drives barrel cracking in plated through-holes and via fatigue during thermal cycling.

Standard FR-4 laminates have Tg values in the 130 to 140 degree Celsius range. Mid-Tg FR-4 sits at 150 to 155 degrees Celsius. High-Tg FR-4 reaches 170 to 180 degrees Celsius. The choice between these tiers depends primarily on your assembly process and your product's operating environment. Lead-free reflow profiles with peak temperatures at 245 to 260 degrees Celsius push the laminate well above the Tg of standard FR-4 for a significant duration, accelerating Z-axis expansion during the hottest phase of assembly. In our production facility, we have observed measurably higher first-pass yields on complex multilayer boards when the laminate Tg is at least 20 degrees Celsius above the standard FR-4 threshold, which is one reason we recommend mid-Tg or high-Tg FR-4 for any lead-free assembly with eight or more layers. Our detailed comparison of Tg 150 versus Tg 170 FR-4 examines the cost and reliability tradeoffs of each tier for specific application categories.

Thermal Decomposition Temperature

Thermal decomposition temperature, abbreviated Td, is the temperature at which the resin system begins to decompose irreversibly, measured as the point where five percent weight loss occurs under thermogravimetric analysis. Unlike Tg, crossing Td causes permanent damage to the laminate. Standard FR-4 grades typically have Td values around 300 to 310 degrees Celsius, while high-performance FR-4 grades push Td above 340 degrees Celsius and in some cases above 350 degrees Celsius.

Td matters most during lead-free assembly where peak reflow temperatures reach 260 degrees Celsius. While 260 degrees is below even the lowest Td values, multiple reflow cycles, rework operations, and wave soldering of through-hole components on the secondary side all add cumulative thermal exposure. Boards that see three or more thermal excursions above 240 degrees Celsius need Td values above 330 degrees Celsius to maintain long-term reliability. In automotive applications where the board may undergo additional thermal stress from its operating environment over a fifteen-year service life, specifying Td above 340 degrees Celsius provides an important safety margin.

Dielectric Constant

The dielectric constant, abbreviated Dk or Er, determines the speed at which electromagnetic waves propagate through the material and directly controls the impedance of PCB traces. A higher Dk means slower propagation and narrower traces for a given impedance target. For FR-4, Dk values at 1 GHz typically range from 4.2 to 4.7 depending on the specific laminate, the measurement frequency, the resin content of the prepreg or core, and the glass weave style.

The frequency dependence of Dk is an important but often overlooked characteristic. All FR-4 materials show decreasing Dk as frequency increases, but the rate of decrease varies between grades. Standard FR-4 might measure Dk of 4.5 at 1 MHz and 4.35 at 1 GHz. A low-loss grade might measure 3.9 at 1 MHz and 3.68 at 1 GHz. For impedance calculations in modern high-speed designs, always use Dk values at the frequency closest to the Nyquist frequency of your fastest signal, not the 1 MHz value that appears prominently on many older datasheets.

Resin content also affects Dk significantly. Within the same laminate family, a 1080 prepreg style with approximately 65 percent resin content might have a Dk of 3.9 at 1 GHz, while a 7628 prepreg style with approximately 42 percent resin content from the same resin system measures Dk of 4.4 at 1 GHz. This happens because the resin itself has a lower Dk (approximately 3.2 to 3.5) than the E-glass fibers (approximately 6.1), so a higher proportion of resin pulls the composite Dk downward. This variation is the reason that accurate impedance-controlled PCB design requires specifying both the laminate grade and the prepreg style in the stackup, not just a generic FR-4 Dk value.

Dissipation Factor

Dissipation factor, abbreviated Df or loss tangent, quantifies how much signal energy the dielectric absorbs and converts to heat as an electromagnetic wave travels through it. Lower Df means lower signal attenuation, which translates directly to longer allowable trace lengths, cleaner eye diagrams, and wider timing margins at high data rates. Of all the FR-4 properties, Df has the strongest influence on whether a design works at gigabit data rates.

Standard FR-4 has a Df of 0.018 to 0.025 at 1 GHz. Mid-loss FR-4 grades reduce this to 0.012 to 0.016 at 1 GHz. Low-loss FR-4 grades like Isola FR408 achieve Df values around 0.010 at 1 GHz. To put these numbers in practical perspective, a twelve-inch trace on standard FR-4 at 10 Gbps loses approximately 1.2 to 1.5 dB more signal amplitude than the same trace on a low-loss FR-4 grade. At 25 Gbps, that difference widens to 3 to 4 dB, which can be the difference between an open eye diagram and a closed one.

Like Dk, dissipation factor increases with frequency. A laminate with Df of 0.015 at 1 GHz might measure 0.020 at 10 GHz. This frequency dependence is more pronounced in standard FR-4 grades than in low-loss grades, which means the performance gap between material tiers widens as signal speed increases.

Coefficient of Thermal Expansion

The coefficient of thermal expansion, abbreviated CTE, describes how much the material expands per degree of temperature change. FR-4 has dramatically different CTE values depending on the axis of measurement. In the X and Y plane (parallel to the glass weave), CTE ranges from 12 to 16 parts per million per degree Celsius, which is reasonably close to the 17 ppm/C of copper. This similarity means that the copper features on the board surface expand at approximately the same rate as the laminate, preventing excessive stress at the copper-laminate interface during thermal cycling.

The Z-axis is where the story changes. Below Tg, Z-axis CTE for standard FR-4 is typically 50 to 70 ppm/C, roughly four to five times higher than the in-plane value. Above Tg, Z-axis CTE jumps to 250 to 300 ppm/C. This anisotropic expansion is what makes plated through-hole vias vulnerable to thermal cycling fatigue. Each time the board heats up and cools down, the laminate expands and contracts more in the Z-axis than the copper barrel lining the via, putting tensile stress on the copper. After enough cycles, the copper fatigues and cracks, creating an open circuit.

High-Tg FR-4 grades improve this situation in two ways. First, they have slightly lower Z-axis CTE below Tg, typically 45 to 60 ppm/C instead of 50 to 70 ppm/C. Second, by raising the Tg threshold itself, they keep the board in the lower-CTE regime for a wider temperature range, reducing the total Z-axis expansion during each thermal excursion. For boards with aspect ratios above 8:1 (board thickness to smallest via diameter), this improvement in Z-axis CTE can mean the difference between passing and failing 500-cycle thermal shock testing per IPC-TM-650.

Thermal Conductivity

Thermal conductivity of FR-4 is approximately 0.3 watts per meter-kelvin in the through-plane direction and slightly higher, around 0.6 to 0.8 W/m-K, in the in-plane direction. These values make FR-4 a relatively poor thermal conductor compared to metals but adequate for most electronics applications where heat is managed through thermal vias, copper pours, and external heatsinks rather than through the laminate itself.

The low thermal conductivity of FR-4 becomes a limiting factor in power electronics and LED applications where significant heat must be conducted away from components. In these cases, metal-core PCBs using aluminum or copper substrates with thermal conductivity of 1 to 3 W/m-K offer a better solution, though at a substantial cost premium and with design constraints that FR-4 does not impose.

The FR-4 Family — Specific Laminate Grades Every Engineer Should Know

Understanding that FR-4 is a family of materials is only useful if you know the specific members of that family and how they differ. In our fabrication facility, we stock and process laminates from multiple suppliers, and we have direct experience with how each grade performs through lamination, drilling, plating, and final inspection. The following overview covers the grades that appear most frequently in our production and in the broader PCB industry, organized by performance tier.

Standard FR-4: The Baseline

Standard FR-4 represents the lowest cost and most widely available tier. The defining example is Shengyi S1141, a workhorse laminate with a glass transition temperature of 135 degrees Celsius, a Dk of approximately 4.45 at 1 GHz, and a Df of 0.020 at 1 GHz. Its thermal decomposition temperature sits at 305 degrees Celsius. Kingboard A3141 is a comparable laminate at a similar price point. These laminates dominate the consumer electronics segment where boards are assembled once using lead-free solder, operate at moderate temperatures, and carry signals at frequencies below 500 MHz.

Standard FR-4 is entirely adequate for power supplies, simple microcontroller boards, LED drivers, IoT sensor nodes running at sub-gigahertz frequencies, and any application where impedance control is either not required or specified with tolerances wider than plus or minus ten percent. The cost advantage is significant: standard FR-4 is typically 20 to 30 percent less expensive than mid-Tg grades and 40 to 50 percent less expensive than high-Tg grades when comparing equivalent thickness and copper weight configurations.

The limitation of standard FR-4 becomes apparent during lead-free assembly of complex boards. In our production data, boards with twelve or more layers built on standard Tg laminate show approximately twice the rate of via microcracking after three reflow cycles compared to the same designs built on mid-Tg material. For simple two-layer and four-layer boards with via aspect ratios below 6:1, this difference is negligible. For high-layer-count boards with tight via geometries, it becomes a reliability concern.

Mid-Tg FR-4: The Production Sweet Spot

Mid-Tg FR-4 occupies what we consider the optimal balance point for the majority of modern PCB designs. Shengyi S1000-2 is the most widely used laminate in this tier, with a Tg of 150 degrees Celsius measured by DSC, a Td of 340 degrees Celsius, a Dk of 4.40 at 1 GHz, and a Df of 0.017 at 1 GHz. ITEQ IT-158 offers comparable specifications at a similar price point and is particularly popular with fabricators in Taiwan and Southeast Asia.

The jump from standard to mid-Tg FR-4 addresses the two most common reliability risks in modern PCB assembly. First, the higher Tg keeps the material in its lower-CTE regime throughout more of the lead-free reflow profile, reducing Z-axis stress on vias. Second, the significantly higher Td of 340 degrees Celsius versus 305 degrees Celsius provides a larger margin against cumulative thermal damage during multiple assembly operations including reflow, wave soldering, and rework.

When we review fabrication notes that specify only "FR-4, Tg 150 minimum," Shengyi S1000-2 is our default selection unless the design has additional requirements that push it toward a higher tier. This grade handles eight-layer and ten-layer stackups reliably, supports impedance-controlled designs with reasonable accuracy when the correct Dk values are used in the stackup model, and costs only a modest premium over standard FR-4. For a comprehensive understanding of how prepreg and core layers work together in a multilayer stackup using these materials, understanding the lamination structure is essential to proper material specification.

High-Tg FR-4: For Demanding Applications

High-Tg FR-4 provides glass transition temperatures of 170 to 180 degrees Celsius and is specified for automotive, industrial, aerospace, and any application requiring extended thermal reliability. Three laminates dominate this tier in our production experience.

Shengyi S1170 offers a Tg of 170 degrees Celsius by DSC, a Td of 345 degrees Celsius, a Dk of 4.30 at 1 GHz, and a Df of 0.018 at 1 GHz. It represents the most cost-effective entry into the high-Tg tier and is our standard recommendation for automotive body electronics and industrial control boards that need high-Tg performance without the premium of the top-tier materials.

ITEQ IT-180A pushes Tg to 175 degrees Celsius with a Td of 350 degrees Celsius and offers improved electrical performance with a Df of 0.016 at 1 GHz. This laminate has become extremely popular for designs that need both high thermal reliability and moderate signal integrity performance, such as automotive infotainment systems running LVDS or GMSL interfaces, and industrial IoT gateways with Gigabit Ethernet.

Isola 370HR provides a Tg of 180 degrees Celsius, a Td of 340 degrees Celsius, a Dk of 4.17 at 1 GHz, and a Df of 0.019 at 1 GHz. It is specified heavily in aerospace and defense applications, partly because of its long qualification history and established track record in high-reliability programs. Isola 370HR is referenced in numerous military and aerospace qualified product lists, making it a default choice when the application demands traceability to established qualification data.

Low-Loss FR-4: Bridging Toward High-Speed Materials

The low-loss tier of the FR-4 family represents the performance ceiling for epoxy-based laminates before designers must transition to fundamentally different resin systems. These grades achieve dissipation factors competitive with some mid-tier high-speed laminates while retaining the processability and supply chain advantages of the FR-4 family.

Isola FR408 is the benchmark in this category, with a Dk of 3.68 at 1 GHz, a Df of 0.010 at 1 GHz, a Tg of 180 degrees Celsius, and a Td of 360 degrees Celsius. These numbers make FR408 approximately twice as good as standard FR-4 in terms of signal loss per unit length at gigahertz frequencies. For designs running 5 to 10 Gbps serial links where standard FR-4 falls short but Rogers or Megtron pricing is not justified, FR408 occupies a valuable middle ground.

Nelco N4000-13 offers similar performance with a Dk of 3.70 at 1 GHz and a Df of 0.009 at 1 GHz, though availability can be more limited in the Asia-Pacific fabrication base. Both of these laminates command a price premium of approximately 60 to 80 percent over standard FR-4, which positions them as significantly less expensive than true high-speed materials like Panasonic Megtron 6 or Rogers RO4350B while delivering enough electrical performance to serve the 5 to 8 GHz frequency range.

Halogen-Free FR-4: Meeting Environmental Requirements

Halogen-free FR-4 replaces the traditional brominated flame-retardant chemistry with phosphorus or nitrogen-based alternatives to comply with environmental regulations and customer requirements beyond standard RoHS compliance. Shengyi S1165 and ITEQ IT-168G1 are representative examples in this category, offering Tg values around 150 to 160 degrees Celsius with electrical properties comparable to their brominated mid-Tg counterparts.

The shift to halogen-free FR-4 introduces some processing differences that fabricators must account for. Halogen-free laminates tend to absorb moisture more readily, which requires tighter baking protocols before lamination and soldering. Drill wear rates are slightly higher due to the different filler chemistry. In our experience, these differences are well understood and do not affect yield when proper process controls are in place, but they do contribute to a modest cost premium of approximately 10 to 15 percent over equivalent halogen-containing grades.

The following comparison summarizes key properties across the FR-4 family. These values represent typical datasheet specifications and should be confirmed against the manufacturer's current datasheet for any specific design.

Laminate	Supplier	Tg (DSC)	Td (5%)	Dk at 1 GHz	Df at 1 GHz	Cost Tier
S1141	Shengyi	135 C	305 C	4.45	0.020	Baseline
S1000-2	Shengyi	150 C	340 C	4.40	0.017	1.2x
IT-158	ITEQ	150 C	340 C	4.40	0.016	1.2x
S1170	Shengyi	170 C	345 C	4.30	0.018	1.4x
IT-180A	ITEQ	175 C	350 C	4.25	0.016	1.5x
370HR	Isola	180 C	340 C	4.17	0.019	1.6x
FR408	Isola	180 C	360 C	3.68	0.010	1.8x
N4000-13	Nelco	175 C	350 C	3.70	0.009	1.8x
S1165	Shengyi	155 C	340 C	4.35	0.018	1.3x

Fiber Weave Effect — The Hidden FR-4 Problem at High Speeds

Every FR-4 laminate is reinforced with woven E-glass fiber cloth, and that weave pattern creates a problem that most FR-4 guides never mention. The woven structure means that at any given point on the board, a trace might sit directly over a glass fiber bundle with Dk around 6.1, or it might sit over a pocket of resin with Dk around 3.2 to 3.5. This local variation in dielectric constant creates non-uniform signal propagation that manifests as skew in differential pairs and localized impedance deviations.

The effect depends heavily on the glass weave style used in the prepreg and core layers. Three weave styles appear most frequently in FR-4 PCB construction, and they have very different characteristics.

Style 7628 is a coarse, heavy weave with thick fiber bundles and relatively large open windows between bundles. It uses a balanced weave pattern with approximately 42 percent resin content. The large bundle size means that a narrow trace can fit entirely over a glass bundle or entirely over a resin pocket, creating maximum Dk variation across the trace width. A differential pair routed on a 7628 prepreg layer can experience intra-pair skew of 10 to 15 picoseconds per inch simply because one trace of the pair sits over glass while the other sits over resin.

Style 2116 is a medium weave that represents the most common prepreg style in multilayer FR-4 stackups. It has a tighter weave pitch than 7628 and approximately 52 percent resin content. The smaller bundle spacing reduces but does not eliminate the Dk non-uniformity. Typical intra-pair skew on a 2116 prepreg is 5 to 8 picoseconds per inch for standard pitch differential pairs.

Style 1080 is a fine, lightweight weave with thin fiber bundles, tight pitch, and approximately 65 percent resin content. The fine weave structure averages out the glass-resin Dk variation more effectively, reducing intra-pair skew to 2 to 4 picoseconds per inch. The high resin content also lowers the composite Dk, which is why 1080 prepreg has a lower Dk than 2116 or 7628 prepreg from the same laminate family.

For designs running at or below 5 Gbps per lane, the fiber weave effect on standard FR-4 weaves is generally within the timing margin budget. At 10 Gbps and above, the accumulated skew over a six-inch differential pair can consume a significant portion of the timing budget, particularly for protocols like PCIe Gen 4 or USB 3.2 Gen 2x2 that have tight skew specifications.

Three mitigation strategies exist for high-speed designs that must remain on FR-4. The first is specifying spread-glass or flat-glass prepreg styles such as Shengyi's 1078 spread glass, which mechanically flattens the glass bundles during weaving to create a more uniform glass distribution. Spread glass can reduce intra-pair skew to 1 to 2 picoseconds per inch, approaching the performance of resin-based materials. The second strategy is routing differential pairs at an angle to the glass weave, ideally at approximately 10 to 15 degrees off the warp or weft direction, which ensures that both traces of a pair see a statistical average of glass and resin rather than each sitting over a consistent stripe. Some designers route at a full 45 degrees for maximum averaging, though this consumes additional board area. The third strategy is specifying NE-glass (also called L-glass or low-Dk glass) fiber instead of standard E-glass. NE-glass has a Dk of approximately 4.4 compared to 6.1 for E-glass, which reduces the magnitude of the Dk non-uniformity between glass and resin regions from a ratio of nearly 2:1 to approximately 1.3:1.

When we review high-speed designs that push FR-4 to its limits, one of the first questions our signal integrity team asks is what glass weave style was assumed in the simulation model. A designer who modeled their stackup using a bulk Dk value of 4.2 without accounting for the weave-induced variation may find that production boards show more skew and more impedance scatter than the simulation predicted. Specifying the glass weave style in the fabrication notes, alongside the laminate grade and impedance control requirements, ensures that the fabricated board matches the simulation model.

How to Specify FR-4 in Your Fabrication Drawing

The fabrication drawing is the contract between the designer and the manufacturer. Everything the fabricator needs to know about material selection should appear on that drawing or in the accompanying specification. Vague material callouts are the single most common source of material-related quality issues in our production experience, and they are entirely preventable.

For a standard consumer electronics product assembled with lead-free solder and operating at frequencies below 1 GHz, a minimal but adequate material specification looks like this: "Material: FR-4, Tg 150C minimum (DSC), UL94 V-0. IPC-4101/126 or equivalent. Shengyi S1000-2 preferred." This tells the fabricator the performance tier, provides a recognized industry specification for acceptable alternatives, and names a specific preferred material. It gives the fabricator flexibility to source from their existing inventory while establishing a clear performance floor.

For an impedance-controlled design, the material specification must be more detailed because the impedance of every trace depends directly on the dielectric constant and thickness of the specific laminate used. The specification should read: "Material: FR-4, Tg 170C minimum (DSC), Td 340C minimum. Approved materials: ITEQ IT-180A, Shengyi S1170, or Isola 370HR. Impedance stackup per attached stackup drawing. Any material substitution requires re-simulation of impedance stackup and written approval from [company name]. Prepreg styles per stackup: 1080, 2116, or 3313 as specified." This level of detail eliminates ambiguity and prevents the fabricator from substituting a material that would shift impedance values outside your tolerance band. Our guide to controlled impedance PCB stackup calculations details how each of these material parameters flows into the impedance model.

For high-reliability applications including automotive, medical, and aerospace, the specification should reference the IPC-4101 slash sheet number explicitly and include additional requirements: "Material: FR-4, IPC-4101/129 or /130. Tg 175C minimum (DSC), Td 350C minimum. Dk at 1 GHz: 4.2 plus or minus 0.15. Z-axis CTE below Tg: 55 ppm/C maximum. Lead-free compatible per J-STD-020. Laminate manufacturer certificate of conformance required with each production lot. Material substitution not permitted without written engineering change order approval."

When we see a fabrication note that says simply "Material: FR-4" with no further qualification, our engineering review team adds a flag and contacts the customer before proceeding. For a two-layer board at 1.6 millimeters with no impedance requirements, we will typically select our standard stocked laminate and proceed after confirmation. For anything more complex, we need specific material guidance to ensure the finished board meets the designer's actual requirements.

One specification detail that many engineers overlook is the IPC-4101 slash sheet system. IPC-4101 is the industry standard for base materials, and each slash sheet number (such as /21, /24, /26, /126, /129) defines a specific set of property requirements including Tg, Td, Dk, Df, CTE, and flammability. Specifying a slash sheet number rather than a brand name gives the fabricator flexibility to use any qualifying laminate from any manufacturer, which improves availability and can reduce cost, while still ensuring that the material meets your performance requirements. Slash sheet /126 covers mid-Tg FR-4 with 150 degrees Celsius minimum Tg and is the most commonly specified sheet for general-purpose lead-free applications. Slash sheet /129 covers high-Tg FR-4 with 170 degrees Celsius minimum Tg for demanding applications.

Material Substitution — When Your Fabricator Uses a Different FR-4

Material substitution is a routine part of PCB fabrication, and whether it causes problems depends entirely on the specific design and how the substitution is managed. Understanding when substitution is safe, when it is risky, and how to control it gives engineers practical tools for protecting their designs without over-constraining the supply chain.

Substitution happens for practical reasons. A fabricator might be out of stock on the specified laminate and have an alternative with equivalent or better specifications available immediately. Regional supply chains favor different brands, with Chinese fabricators stocking primarily Shengyi and ITEQ while North American and European shops tend to carry Isola and Nelco. A customer may specify a laminate that the fabricator does not carry at all, requiring either a special order with lead time or a substitution with equivalent properties.

For designs that are not impedance-controlled and do not have specific thermal performance requirements, substitution between laminates of the same Tg tier is generally safe. Replacing Shengyi S1000-2 with ITEQ IT-158 on a non-impedance-controlled eight-layer board, for example, involves two laminates with nearly identical properties and introduces no measurable risk to the finished product.

Substitution becomes risky when the design is impedance-controlled because even small differences in Dk between laminate grades shift the trace impedance. The difference between Dk of 4.40 for S1000-2 and Dk of 4.25 for IT-180A may seem small, but it translates to approximately a three to four percent impedance shift on a typical 50-ohm microstrip, which is a meaningful fraction of a plus-or-minus ten percent impedance tolerance. If the designer modeled the stackup with one laminate's Dk and the fabricator substitutes another without re-simulating the stackup, the finished board may fail impedance testing.

Substitution is most dangerous in high-reliability applications where the design has been qualified on a specific material. Automotive, aerospace, and medical electronics often undergo formal qualification testing where the specific laminate is part of the qualified configuration. Changing the laminate without re-qualification can invalidate the qualification status, which in regulated industries can have serious consequences beyond just board-level performance.

To prevent problematic substitution, the most effective approach is combining an approved material list with a substitution approval requirement in the fabrication notes. Listing two or three acceptable laminates by brand and part number gives the fabricator sourcing flexibility while constraining the material to grades you have already verified in your stackup model. Adding a clause that requires written approval before any substitution not on the approved list provides a final checkpoint. For production orders, requesting the laminate certificate of conformance with each shipment allows incoming inspection to verify the actual material used without relying solely on the fabricator's process discipline.

When FR-4 Reaches Its Limits

FR-4 is the default PCB material for good reason: it is inexpensive, widely available, well-characterized, and adequate for the vast majority of electronic applications. But every material has limits, and understanding where FR-4's performance ceiling lies prevents engineers from pushing a design past the point where the material can deliver reliable results.

The primary performance limit of FR-4 is signal loss at high frequencies. The dissipation factor of the epoxy resin system absorbs signal energy that increases with frequency, and the dielectric constant non-uniformity from the glass weave adds impedance scatter that degrades signal quality. For standard FR-4 with Df around 0.020, the practical frequency limit for reliable signal transmission is approximately 1 to 2 GHz for long traces (over six inches) and 2 to 3 GHz for short traces (under three inches). Beyond these thresholds, the eye diagram for a serial data link begins closing, and the bit error rate increases above acceptable levels.

Low-loss FR-4 grades extend the usable frequency range. With Df around 0.010 to 0.012, laminates like Isola FR408 support reliable signaling up to approximately 6 GHz for moderate trace lengths, corresponding to data rates around 10 to 12.5 Gbps per lane with NRZ encoding. This covers the requirements of PCIe Gen 3, USB 3.2 Gen 2, 10 Gigabit Ethernet, and SATA III with comfortable margin.

Beyond 6 GHz, even the best FR-4 grades begin showing insertion loss that exceeds the loss budgets of modern high-speed protocols. PCIe Gen 5 at 32 GT/s, 100 Gigabit Ethernet at 25 Gbps per lane, and USB4 at 40 Gbps require channel insertion loss well below what FR-4 can deliver over typical backplane or board-to-board trace lengths. These applications require low-loss materials such as Panasonic Megtron 6, Isola I-Tera MT40, or Rogers RO4350B, which achieve Df values of 0.002 to 0.006 at frequencies above 10 GHz.

To illustrate the practical impact, consider a ten-inch differential pair carrying a 25 Gbps NRZ signal. On standard FR-4 with Df of 0.020, the total dielectric insertion loss at the Nyquist frequency of 12.5 GHz is approximately 1.8 dB per inch, giving a total trace loss of 18 dB. The receiver requires a minimum of -12 dBm signal level to achieve a bit error rate of 10 to the power of negative 12, but after 18 dB of dielectric loss plus additional 4 to 6 dB of conductor loss, the signal is well below the receiver sensitivity threshold. The same trace on a low-loss FR-4 with Df of 0.010 reduces dielectric loss to approximately 1.0 dB per inch, bringing total loss to 10 dB of dielectric plus 4 to 6 dB of conductor loss, which is marginal. On Megtron 6 with Df of 0.004, dielectric loss drops to 0.4 dB per inch, and the link closes with comfortable margin.

Our comprehensive comparison of FR-4 versus Rogers materials examines the specific frequency crossover points where transitioning from FR-4 to specialized high-frequency laminates becomes necessary, including cost analysis and hybrid stackup approaches that use Rogers or PTFE only on the critical signal layers while retaining FR-4 for the remaining structure.

Temperature is the second performance boundary. Standard FR-4 with Tg of 135 degrees Celsius should not be used in applications where the board temperature exceeds 110 degrees Celsius in sustained operation. Even high-Tg FR-4 with Tg of 180 degrees Celsius is not appropriate for sustained temperatures above 150 degrees Celsius. For applications requiring continuous operation above 150 degrees Celsius, polyimide laminates with operating temperatures up to 260 degrees Celsius or ceramic substrates provide the necessary thermal performance. Power amplifier modules, downhole drilling electronics, and under-hood engine sensors are typical applications that exceed FR-4's thermal envelope.

The third limit is mechanical. FR-4 is a relatively rigid material with limited flexibility, and it does not tolerate repeated bending without fracturing. Applications requiring a flexible or rigid-flex construction must use polyimide flex materials in the flexible zones, though FR-4 rigid sections can be combined with polyimide flex sections in a rigid-flex construction.

Understanding these limits is not about avoiding FR-4 but about using it where it works and upgrading where it does not. In our production mix at AtlasPCB, approximately 85 percent of all boards we fabricate use FR-4 in some grade, because the vast majority of electronics applications fall well within FR-4's performance envelope. The remaining 15 percent use specialized materials for specific technical reasons, most commonly RF performance, extreme temperature exposure, or flex requirements.

FR-4 in the Manufacturing Process — A Fabricator's Perspective

The choice of FR-4 grade affects not just the finished board's performance but also how the board behaves during every step of manufacturing. Engineers who understand these manufacturing interactions make better material decisions and write better fabrication specifications.

Laminate procurement is the first consideration. Not all FR-4 grades are available at every fabricator, and lead times vary significantly. Standard FR-4 from Shengyi is available in virtually every panel size and copper weight combination with immediate stock at most Asian fabricators. High-performance grades like Isola FR408 or Nelco N4000-13 may require special ordering with two to four weeks of additional lead time, particularly at fabricators whose primary supply chain is built around Chinese domestic laminate suppliers. When we review a new design at AtlasPCB, one of our first checks is whether the specified laminate is in our regular stock program, because material availability directly affects the quoted lead time.

During inner layer processing, different FR-4 grades exhibit different drilling and routing characteristics. Higher-Tg laminates with modified resin systems tend to be slightly harder and more abrasive to drill bits, which increases drill wear rates and can affect hole quality if the fabricator does not adjust their drill parameters accordingly. Standard FR-4 cores drill cleanly with standard carbide bits for 2000 to 3000 hits before quality degrades. High-Tg cores may reduce that to 1500 to 2500 hits, requiring more frequent bit changes to maintain hole wall quality. Halogen-free laminates with their different filler chemistry can be particularly aggressive on drill tooling.

The lamination process in multilayer PCB manufacturing is where FR-4 grade selection has the most direct process impact. Each laminate family has specific lamination recipes defining the temperature ramp rate, maximum temperature, dwell time, and pressure profile required for proper resin flow and cure. Using the wrong lamination recipe for a given material can result in insufficient resin flow leaving voids, excessive resin flow causing thickness variation, or incomplete cure leaving the resin in a partially polymerized state that compromises long-term reliability. When a fabricator substitutes a different FR-4 grade, the lamination recipe may need adjustment, which is one reason why uncontrolled substitution is risky for complex multilayer builds.

After lamination, the cured FR-4 panel undergoes drilling, plating, outer layer imaging, etching, solder mask, and surface finish. The FR-4 grade has relatively minor influence on these downstream processes, though the surface roughness of the laminate can affect dry film adhesion during imaging, and the moisture absorption characteristics affect whether the panel needs pre-baking before solder mask or surface finish application.

The overall message for designers is that FR-4 selection is not just a performance specification on a datasheet. It is a manufacturing decision that ripples through the entire fabrication process. Working with a fabricator who understands the specific characteristics of the laminate grade you specify, and who stocks it regularly enough to have well-characterized process parameters for it, reduces risk and improves first-pass yield.

Choosing the Right FR-4 Grade for Your Application

Material selection ultimately comes down to matching the laminate's capabilities to the design's requirements across thermal, electrical, and reliability dimensions. Rather than always specifying the highest-performance grade available, engineers should identify the specific requirements that drive the selection and choose the most cost-effective grade that satisfies all of them.

For consumer electronics with standard lead-free assembly, moderate signal speeds below 1 GHz, and no extended thermal exposure, mid-Tg FR-4 such as Shengyi S1000-2 provides the optimal balance. It costs only marginally more than standard FR-4, handles lead-free reflow reliably, and supports impedance control with adequate precision for most digital interfaces.

For automotive and industrial applications requiring high thermal reliability, extended operating temperature range, or multiple reflow cycles, high-Tg FR-4 such as ITEQ IT-180A or Isola 370HR is the appropriate tier. The cost premium of 40 to 60 percent over standard FR-4 is justified by the improved Z-axis CTE, higher Td, and better long-term reliability in thermal cycling environments.

For high-speed digital designs pushing 5 to 10 Gbps per lane, low-loss FR-4 such as Isola FR408 delivers the signal integrity performance these interfaces demand without the full cost impact of premium high-speed laminates. When trace lengths are short enough, mid-loss high-Tg grades like ITEQ IT-180A may provide sufficient signal integrity while also meeting thermal requirements, which simplifies the material specification to a single grade.

For designs operating above 10 GHz or above 10 Gbps per lane over moderate trace lengths, FR-4 in any grade is likely insufficient, and the designer should evaluate specialized materials or hybrid stackups. Starting the material evaluation early in the design phase, ideally before layout begins, prevents expensive board respins caused by discovering late that the selected material cannot support the required channel loss budget.

In every case, the fabrication drawing should reflect the material decision with the level of detail appropriate to the design's complexity and criticality. Specifying a generic "FR-4" callout is acceptable only for the simplest designs where any FR-4 grade will work. For everything else, naming the specific laminate grade, the Tg and Td requirements, and the IPC-4101 slash sheet provides the clarity that both the fabricator and the designer need to ensure the finished board meets its intended performance requirements.

4-Layer vs 6-Layer PCB: A Manufacturer's Decision Guide with Real Cost and Routing Data

AtlasPCBEngineering — Thu, 03 Sep 2026 00:24:21 +0000

Originally published on AtlasPCB Engineering Blog. AtlasPCB specializes in multilayer PCB manufacturing from 1 to 30 layers.

Reviewed by AtlasPCB Engineering Team

The Real Question: Is the Extra Cost Worth It?

The jump from four layers to six is the most common layer-count decision that lands in our engineering review queue. Designers know their boards need more than two layers, they have already committed to a multilayer build, and now they face a choice that affects both their bill of materials and their confidence in passing EMC certification on the first attempt.

The short answer is straightforward. If your design includes any BGA with a pitch at or below 0.8 millimeters, any DDR4 or DDR5 memory interface, any serial link running faster than 5 gigabits per second, or if your board area is too tight to route all your nets on two signal layers, you need six layers. For everything else, four layers handle the job at lower cost. The detailed answer requires understanding exactly what those two additional layers give you, what they cost in real production dollars, and where the break-even point falls for your specific design.

At AtlasPCB, we manufacture roughly equal volumes of 4-layer and 6-layer boards across our production lines. The designs that succeed on four layers share common characteristics: moderate pin density, clock frequencies below 200 megahertz, generous board area relative to component count, and interfaces that do not require matched-length differential routing. The designs that need six layers also share patterns, and understanding those patterns before you commit your stackup saves both money and schedule.

Stackup Architecture: What the Extra Layers Provide

A 4-layer PCB stackup uses the standard configuration of Signal-Ground-Power-Signal, placing one reference plane (ground) directly beneath the top signal layer and one reference plane (power) above the bottom signal layer. This gives you two outer routing layers, each with a single adjacent reference plane for impedance control.

A 6-layer PCB stackup in its most common configuration uses Signal-Ground-Signal-Power-Ground-Signal. The critical additions are a third signal layer (L3) buried between the ground and power planes, and a second ground plane (L5) that provides a dedicated reference for the bottom signal layer.

The structural differences are more significant than the simple addition of two copper layers suggests. In a 4-layer board, the two reference planes (L2 ground and L3 power) are separated by the full core thickness, typically 1.0 to 1.2 millimeters. This wide spacing means the power-ground plane pair provides minimal interplane capacitance for power delivery decoupling. In a 6-layer board, the power plane (L4) and its adjacent ground plane (L5) are separated by only 3 to 5 mils of prepreg, creating a tightly coupled capacitor structure that dramatically reduces power distribution network impedance at frequencies from 100 megahertz to over a gigahertz.

The buried signal layer (L3) in a 6-layer board sits between two continuous reference planes — ground above and power below. This configuration is called a stripline environment, and it provides superior noise isolation compared to the microstrip traces on outer layers. Outer-layer microstrip traces radiate energy into the air above them and are susceptible to external electromagnetic interference. The shielded L3 stripline sees neither problem because the reference planes above and below contain the electromagnetic field completely. For sensitive or high-speed signal routing, this shielding advantage alone often justifies the additional cost.

Routing Capacity: When Two Signal Layers Are Not Enough

The most concrete way to evaluate whether you need six layers is to calculate your routing demand against available routing capacity. This calculation depends on your component pin count, BGA pitch, board dimensions, and the minimum trace width and spacing your design requires.

On a 4-layer board, you have two routing layers — the top and bottom surfaces. Every signal must be routed on one of these two layers or transition between them through vias that consume board area and add cost. A standard routing channel between two 0.5-millimeter-pitch BGA pads allows one trace at 4-mil trace width with 4-mil spacing. With two routing layers, you can escape two rows of BGA pins per routing channel before running out of space.

A 0.5-millimeter-pitch BGA with a 15-by-15 array has 225 pads. After placing power and ground pads (typically 30 to 40 percent of total), you have roughly 135 to 155 signal pins that need escape routing. On a 4-layer board with two available signal layers, escaping this many pins from a 0.5mm pitch BGA requires either via-in-pad technology or a large via fanout area surrounding the component, both of which add significant cost and board area. With three signal layers available on a 6-layer board, the same BGA can be escaped more compactly because the interior pins route down to L3 through microvias or through-hole vias, freeing the outer layers for the peripheral pins.

The practical threshold we see in production is this: if your design has fewer than 300 total signal pins on components with pitch at or above 0.65 millimeters, and your board area is at least 1.5 times the component placement area, a 4-layer board provides adequate routing capacity. Once you exceed 400 signal pins, drop below 0.65mm pitch, or have a board area ratio below 1.2, a 6-layer board almost always produces a cleaner layout with shorter trace lengths and fewer vias.

EMI Performance and Signal Integrity

The electromagnetic behavior of a PCB is fundamentally shaped by how completely and consistently the signal traces are referenced to adjacent ground planes. This is where 4-layer and 6-layer boards diverge most significantly for designs operating above 100 megahertz.

On a 4-layer board in the standard S-G-P-S configuration, the top signal layer is referenced to the L2 ground plane and the bottom signal layer is referenced to the L3 power plane. When a signal transitions from the top layer to the bottom layer through a via, the return current must also transition from the ground plane to the power plane. If the ground and power planes are not well connected at that point by decoupling capacitors, the return current finds a long path that creates a loop antenna radiating electromagnetic energy. This return path discontinuity is the single largest source of EMC failures in 4-layer designs.

A 6-layer board addresses this problem from two directions. First, the tightly coupled L4-L5 power-ground pair provides intrinsic interplane capacitance that allows return current to transition between planes without relying solely on discrete decoupling capacitors. Second, the most sensitive signals can be routed on the shielded L3 layer, where they never need to change reference planes and where external noise cannot couple into them.

In our EMC pre-compliance testing at AtlasPCB, we consistently observe that 6-layer boards achieve 6 to 15 dB lower radiated emissions than equivalent 4-layer designs at frequencies above 200 megahertz, assuming competent layout practices on both. For products targeting FCC Class B certification (the stricter consumer standard), this margin often represents the difference between passing on the first test and requiring a board respin.

Power Delivery Network Comparison

The power delivery network performance gap between 4-layer and 6-layer boards is substantial and often underestimated during the design phase. Modern digital ICs switch large transient currents at frequencies from tens of megahertz to several gigahertz, and the PCB plane structure must supply those currents with minimal voltage fluctuation.

In a 4-layer board, the ground plane (L2) and power plane (L3) are separated by the core laminate, typically 1.0 to 1.2 millimeters thick. The interplane capacitance of this pair is approximately 25 picofarads per square centimeter — enough to provide some high-frequency decoupling, but not enough to maintain low impedance above 100 megahertz without extensive discrete capacitor placement. Engineers compensating for this limitation must place more decoupling capacitors, use larger capacitor values, and pay careful attention to capacitor mounting loop inductance. The board area consumed by these capacitors can be significant.

In a 6-layer board, the L4-L5 power-ground pair is separated by only 3 to 5 mils of prepreg, creating interplane capacitance of approximately 500 to 800 picofarads per square centimeter — a twenty-fold improvement. This embedded capacitance provides effective decoupling at frequencies from approximately 200 megahertz to over 1 gigahertz without discrete components. The practical result is that a 6-layer board typically needs 30 to 50 percent fewer decoupling capacitors than a 4-layer board for the same target PDN impedance, which partially offsets the higher bare-board cost through reduced BOM cost and simplified assembly.

Interface-by-Interface Decision Table

Rather than applying general rules, the most reliable way to choose your layer count is to evaluate each interface on your board against its specific requirements. The following recommendations are based on our manufacturing and signal integrity experience across thousands of production designs.

For USB 2.0 operating at 480 megabits per second, a 4-layer board is fully adequate. The differential pair requires 90-ohm impedance and benefits from a continuous ground reference, both of which a standard 4-layer stackup provides. USB 3.0 at 5 gigabits per second can work on 4 layers if the differential pair routing is short (under 100 millimeters) and well-isolated, but a 6-layer board provides better margin. USB 3.2 Gen 2 at 10 gigabits per second and USB4 should use 6 layers, with the differential pairs routed on the shielded internal layer.

Ethernet interfaces follow a similar pattern. 10/100BASE-T and Gigabit Ethernet work well on 4-layer boards. 2.5GBASE-T benefits from 6 layers for the improved differential pair environment. 5GBASE-T and 10GBASE-T require 6 layers as a minimum, with careful attention to impedance control and crosstalk management.

PCIe Gen 3 at 8 gigatransfers per second can be implemented on 4 layers for single-lane interfaces with short traces. PCIe Gen 4 at 16 gigatransfers per second should use 6 layers. PCIe Gen 5 at 32 gigatransfers per second is best served by 8 layers or more, though carefully designed 6-layer implementations with premium materials can work for single-lane connections.

DDR4 memory interfaces should use 6 layers as a standard practice. While simple DDR4-2133 implementations have been done on 4 layers, the layout complexity and signal integrity risk are disproportionate to the board cost savings. DDR5, with its higher data rates and tighter timing margins, requires 6 layers as an absolute minimum and benefits from 8 layers for dual-rank configurations.

HDMI 2.0 at up to 18 gigabits per second aggregate bandwidth benefits from 6 layers for the TMDS differential pairs. HDMI 2.1 at 48 gigabits per second should use 6 layers with careful material selection, potentially requiring low-loss laminates for longer trace runs.

Real Manufacturing Cost Breakdown

Understanding where the cost comes from helps you make informed trade-offs rather than simply reacting to a quoted price. The manufacturing process for a 6-layer board involves specific additional steps compared to a 4-layer board, and each step adds a quantifiable cost increment.

A 4-layer board requires one inner-layer imaging and etching cycle (for L2 and L3), one lamination press cycle, outer-layer processing (drilling, plating, imaging, etching), and finishing. A 6-layer board adds a second inner-layer imaging and etching cycle (for the additional L2/L3 pair in the construction), a second lamination press cycle (or a more complex single-cycle press with additional layup), and tighter registration requirements that reduce first-pass yield by approximately 2 to 5 percent.

For a standard 100 by 100 millimeter board in FR-4 with 1-ounce copper and ENIG surface finish, our typical production pricing shows the following relationship. At 10 pieces, a 4-layer board costs approximately $9 to $12 per unit and a 6-layer board costs $14 to $20 per unit, representing a 55 to 67 percent premium. At 100 pieces, the 4-layer costs approximately $4 to $6 per unit and the 6-layer costs $6 to $9 per unit, a 50 to 55 percent premium. At 1,000 pieces, the 4-layer costs approximately $1.80 to $2.50 per unit and the 6-layer costs $2.70 to $3.80 per unit, a 45 to 52 percent premium.

For larger boards at 150 by 200 millimeters, the material cost becomes a more significant fraction of total cost. The premium for 6 layers over 4 drops to approximately 40 to 50 percent at prototype quantities because the additional processing steps are spread over a larger panel utilization. Conversely, for very small boards under 50 by 50 millimeters, the per-unit premium is higher in percentage terms because the fixed setup and processing costs dominate.

Lead time also differs. A standard 4-layer board typically ships in 5 to 7 working days from our facility, while a 6-layer board requires 7 to 10 working days due to the additional lamination and processing cycles. Quick-turn options are available for both, but the express premium for 6-layer boards is proportionally higher because the bottleneck is lamination press capacity, which cannot be easily accelerated.

The Hidden Cost of Choosing Too Few Layers

The most expensive PCB decision is not choosing six layers when you should have — it is choosing four layers and discovering the mistake after your first prototype fails EMC testing or exhibits signal integrity problems in the field.

An EMC test failure at a certified lab typically costs $3,000 to $8,000 per session, including setup, testing, and the engineer's report. If the root cause is inadequate reference plane coverage or return path discontinuities — problems fundamentally caused by insufficient layer count — the fix requires a board respin. A complete respin cycle (layout modification, new Gerbers, fabrication, assembly, and re-testing) adds four to eight weeks and $5,000 to $15,000 to your project cost, depending on BOM complexity and test lab availability.

Compare that to the incremental cost of specifying six layers from the start. For a typical production run of 500 boards at 100 by 100 millimeters, the difference between 4-layer and 6-layer is approximately $1,500 to $2,500 total. If there is any reasonable doubt about whether four layers will meet your EMC requirements, the six-layer option is the financially rational choice before factoring in schedule risk.

We track the reasons for board respins across our customer base, and layer count under-specification accounts for roughly 12 to 15 percent of first-revision failures. The most common failure modes are radiated emissions above the FCC Class B limit at harmonics of the main clock frequency, power supply noise coupling into sensitive analog circuits through the poorly-decoupled power-ground plane pair, and DDR memory timing failures caused by excessive crosstalk on unshelded outer-layer routing.

Design Rules and DFM Considerations

The manufacturing process capabilities for 4-layer and 6-layer boards are largely identical at standard technology levels, but the tighter registration requirements of 6-layer boards affect some design rules in practice.

For trace width and spacing, both layer counts support the same minimums at a given fabricator — typically 3.5 to 4 mil trace width and spacing for standard process, or 3 mil for advanced process. However, the additional inner layers in a 6-layer board must account for registration tolerance between the inner-layer artwork and the drilled holes. Our standard layer-to-layer registration tolerance is plus or minus 3 mils for conventional multilayer boards. This means that the minimum annular ring for inner-layer pads must accommodate the registration tolerance in addition to the drill tolerance. For a 10-mil drill hole with 3-mil registration tolerance and 1-mil drill wander, the minimum pad diameter is 18 mils (10 + 2 x 3 + 2 x 1) to guarantee a 1-mil annular ring on all inner layers.

Via structure is another consideration. Through-hole vias in a 4-layer board pass through all four layers, which is straightforward. In a 6-layer board, through-hole vias also pass through all six layers, but the longer via barrel means the via acts as a more significant impedance discontinuity for high-speed signals. For designs with signal speeds above 5 gigabits per second, the via stub created by a through-hole via in a 6-layer board (where the signal enters on L1 and transitions to L3) can cause resonant notches that degrade signal quality. Backdrill technology removes the unused via stub, but it adds approximately 15 to 25 percent to fabrication cost.

For thermal management, both layer counts provide similar options through thermal vias and copper pours. The additional copper layers in a 6-layer board do provide more thermal spreading capacity, which can be significant for designs with concentrated heat sources like power regulators or high-performance processors.

When Four Layers Are Enough

Despite the advantages of six layers, many designs are perfectly served by a 4-layer stackup, and choosing four layers in these cases saves real money without technical compromise.

Microcontroller-based designs running at clock frequencies below 100 megahertz with moderate pin counts (fewer than 200 signal pins) route cleanly on two signal layers. Power supply and motor driver boards where the primary routing challenge is wide power traces rather than dense signal routing benefit from the simplicity and lower cost of four layers. IoT sensor modules with wireless connectivity (WiFi, BLE, LoRa) typically have low pin-count SoCs and antenna structures that are well-served by a 4-layer board with careful ground plane design. Industrial control boards with relay drivers, optocouplers, and simple serial interfaces rarely need more than two routing layers.

The key indicators that four layers will work are: all interfaces operating below 1 gigabit per second, no BGA packages with pitch below 0.8 millimeters, board area at least twice the component footprint area, and no stringent EMC requirements beyond basic CE marking with standard mitigation techniques.

When to Skip Straight to Eight Layers

At the other end of the spectrum, some designs should bypass the 6-layer option entirely and move directly to 8-layer or higher stackups.

Designs with dual-channel DDR5 memory running at 4800 megatransfers per second or above need the additional routing layers and reference planes that an 8-layer board provides. Multi-lane PCIe Gen 5 interfaces at 32 gigatransfers per second demand the signal integrity margin of stripline routing with low-loss materials, which is easier to achieve with the additional reference planes available in an 8-layer stackup. Dense FPGA designs with BGA packages at 0.4 millimeters pitch and pin counts above 500 typically cannot be routed within the constraints of three signal layers and need four or more.

The cost jump from 6 to 8 layers (approximately 30 to 40 percent additional) is proportionally smaller than the jump from 4 to 6 layers, so the financial case for moving up is often easier to justify when the technical requirements are clear.

Making the Decision: A Practical Framework

If you have read this far and still are not certain whether four or six layers is the right call for your design, apply this sequential test. First, check your fastest interface. If anything on the board runs at or above 5 gigabits per second, choose six layers. Second, count your BGA signal pins. If any single BGA has more than 100 signal pins at 0.8 millimeters pitch or finer, choose six layers. Third, estimate your routing density. If your total net count exceeds 200 and your board area is below 80 square centimeters, choose six layers. Fourth, assess your EMC requirements. If you need to pass FCC Class B or CISPR 32 Class B without ferrite beads and common-mode chokes on every cable, choose six layers.

If none of these conditions apply, four layers serve your design well at a meaningfully lower cost. The savings are not just in the bare board price — a 4-layer design is simpler to lay out, faster to fabricate, and easier to modify during prototyping iterations.

The layer count decision should be made during the schematic phase, before component placement begins. Changing from four layers to six after layout has started requires significant rework of the stackup definition, impedance targets, and potentially the component placement to accommodate the changed via structures. Getting it right the first time, using the criteria in this guide, eliminates one of the most common and costly missteps in the PCB design process.

This article was originally published on AtlasPCB.com. For a free DFM review of your multilayer design, visit atlaspcb.com/get-quote.

PCB Prepreg vs Core: What Actually Matters From a Manufacturer's Perspective

AtlasPCBEngineering — Wed, 02 Sep 2026 00:40:07 +0000

Every multilayer PCB starts with the same two dielectric materials: core and prepreg. If you've designed a few boards, you probably know the textbook definitions — core is cured, prepreg isn't. But the practical implications run deeper than most articles cover, especially when it comes to pressed thickness, impedance accuracy, and specification errors that slow down your order.

I work in PCB fabrication, and these are the issues I deal with daily. Here's what actually matters.

The Fundamental Difference

A PCB core is a fully cured copper-clad laminate — rigid, dimensionally stable, with copper bonded to both sides. It's ready for inner-layer imaging and etching. The dielectric thickness is essentially fixed by the time it reaches our facility.

Prepreg is a partially cured (B-stage) bonding material made from the same glass fiber and resin system. During lamination at 170-185°C under 250-400 psi, the resin softens, flows into etched copper relief on adjacent layers, and then cross-links into a permanent bond.

This cured-vs-uncured distinction drives every practical difference:

Core thickness is predictable before lamination
Prepreg thickness changes during pressing based on adjacent copper patterns
Your impedance model needs to account for both behaviors differently

Glass Weave Styles: What You Need to Know

Both materials are built on standardized glass weaves (IPC-4412). The common styles:

Style	Nominal Thickness/ply	Resin Content	Best For
106	~1.5 mil	70-75%	Thinnest dielectric layers
1080	~2.6-3.0 mil	63-68%	Workhorse for thin layers
2116	~4.5-5.0 mil	48-54%	Medium dielectric, good fill
3313	~4.0-4.5 mil	52-58%	Medium-thick constructions
7628	~7.5-8.0 mil	42-48%	Thick layers, strong mechanical

Practical tip: Most fabricators stock 1080, 2116, and 7628 for FR-4. If you specify a style they don't carry, you'll trigger an engineering query (adding days) or a material order (adding a week). Better approach: specify your target dielectric thickness and impedance, and let the fab pick the glass combination from their qualified inventory.

The Pressed Thickness Problem

This is where most articles fall short. The thickness on a prepreg datasheet is the nominal thickness of a single uncured sheet. It is not the dielectric thickness in your finished board.

Here's real production data for 1080 prepreg (Shengyi S1000-2M):

Adjacent Copper Coverage	Pressed Thickness/ply
75%+ (ground/power planes)	2.0-2.3 mil
~50% (moderate routing)	2.3-2.5 mil
25% or less (sparse traces)	2.5-2.8 mil

That's up to 0.8 mil variation from a single ply of the same prepreg, depending on what's on the adjacent layers. For a 50Ω microstrip on a 3 mil dielectric, this can shift impedance by 5-8 ohms if you use the wrong thickness assumption.

This is precisely why fabricators insist on providing impedance-modeled stackups. We calculate pressed thickness for each prepreg layer based on the actual copper distribution extracted from your Gerber files.

Resin Starvation: The Failure Mode Nobody Talks About

When there isn't enough resin in the prepreg to fill the copper relief during lamination, you get voids, incomplete bonding, and eventually delamination.

The math is straightforward: 1 oz copper with 50% removal creates ~1.4 mil deep etch channels. 2 oz copper with the same pattern creates ~2.8 mil channels — needing roughly twice the resin volume. For heavy copper designs, a single prepreg ply may not have enough resin capacity.

It gets worse with uneven copper distribution. A large ground plane (90% copper) next to sparse traces (15% copper) creates differential resin flow — the resin migrates toward the area with more relief, potentially starving the plane area.

Prevention:

Use copper balancing and thieving to equalize distribution
Specify adequate prepreg plies for your copper weight
Let your fabricator validate resin sufficiency during DFM review

Five Specification Mistakes I See Every Week

After processing thousands of designs:

1. Confusing core thickness with dielectric thickness. Core thickness includes base laminate + copper. The dielectric spacing (what matters for impedance) is the core minus copper on each side. An "8 mil core" might have 7.1 mil actual dielectric.

2. Copying exact prepreg style numbers from another fab. Your previous fab's "2 plies of 2116" was based on their inventory. Specify target dielectric thickness instead.

3. Over-constraining the material brand. Unless you genuinely need Rogers 4350B for RF, don't specify "Isola 370HR only" when a Shengyi S1000-2M at lower cost and shorter lead time has equivalent properties.

4. Missing impedance callouts. If your design needs impedance control but the fab drawing doesn't say so, the board gets built without impedance verification.

5. Asymmetric stackups. A stackup that isn't symmetric about the center line causes warpage during lamination. We see this surprisingly often — usually unintentional.

How to Specify Materials Correctly

For standard FR-4 multilayer boards, here's what your fab drawing should include:

Material performance class: "FR-4, Tg 150 min, IPC-4101/126 or equivalent"
Layer-by-layer dielectric targets: "Dielectric L2-L3: 8 mil nominal ±1.5 mil"
Impedance requirements: "50Ω SE, 100Ω differential ±10%, L1/L6 referenced to adjacent planes"
Special requirements only if genuinely needed: "Lead-free compatible, halogen-free per IPC-4101B required"

What NOT to do: copy a specific stackup table from another fabricator's documentation. Their stackup was designed around their inventory and press conditions.

For mixed dielectric stackups (e.g., Rogers + FR-4), specifying the material family by name is appropriate since those electrical properties aren't interchangeable.

The bottom line: core gives you dimensional predictability, prepreg gives you bonding capability. Understanding how both behave during real manufacturing — not just their textbook definitions — is what separates a producible stackup from one that generates engineering queries.

Originally published on the AtlasPCB Engineering Blog. We manufacture multilayer PCBs with impedance-controlled stackups from 2 to 30 layers.

PCB Design for Cost: A Manufacturer's Guide to Reducing Manufacturing Expenses

AtlasPCBEngineering — Tue, 01 Sep 2026 00:18:49 +0000

This article was originally published on AtlasPCB. As a PCB manufacturer processing thousands of designs monthly, we're sharing the real cost drivers we see — with actual multipliers and optimization strategies.

Why Most of Your PCB Cost Is Decided Before You Click "Order"

There is a persistent misconception among hardware engineers that PCB manufacturing cost is primarily a function of the fabricator's pricing and the current materials market. In reality, roughly 70 percent of your total board cost is locked in the moment you finalize your design files. Every specification you set in your EDA tool — layer count, via structure, trace widths, drill sizes, material grade, surface finish — maps directly to specific manufacturing processes, each carrying its own cost multiplier.

In our production lines at AtlasPCB, we process thousands of unique designs every month. The price difference between a well-optimized design and a carelessly specified one can easily reach 40 to 60 percent for the exact same electrical functionality. That gap does not come from clever negotiation or volume discounts. It comes from understanding how each design parameter translates into manufacturing operations and making informed tradeoffs where performance requirements allow flexibility.

This guide walks through every major cost driver in PCB fabrication, with real multipliers and optimization strategies drawn from our manufacturing data. Whether you are designing a prototype or preparing for volume production, these principles will help you reduce PCB manufacturing cost without sacrificing the performance your application demands.

Layer Count: The Single Biggest Cost Lever

No other design decision affects fabrication cost as dramatically as the number of copper layers. Each layer pair added to a PCB stackup requires an additional lamination cycle, inner layer imaging and etching, oxide treatment for adhesion, and precise registration alignment. The relationship between layer count and cost is not linear — it follows a staircase pattern driven by the number of lamination press cycles required.

Based on our production pricing data, here is how layer count affects relative fabrication cost, normalized to a standard 2-layer board:

2-layer: 1.0x (baseline)
4-layer: 1.4x to 1.6x
6-layer: 1.8x to 2.2x
8-layer: 2.4x to 3.0x
10-layer: 3.2x to 4.0x
12-layer and above: 4.5x and up

The jump from 2 to 4 layers is where most engineers face their first cost decision. A 4-layer board provides a dedicated ground plane and power plane, dramatically improving signal integrity and simplifying routing. For many designs, the decision between 2-layer and 4-layer stackups comes down to whether the added signal integrity and routing freedom justifies the 40 to 60 percent cost increase.

From a manufacturer's standpoint, the most common unnecessary cost escalation we see is designs that use 6 layers when 4 would suffice. Careful component placement and routing optimization — especially using modern autorouter-assisted tools — can often eliminate the need for those extra two layers. We recently reviewed a customer's IoT gateway design that was originally laid out on 6 layers. After rearranging the connector placement and consolidating the power distribution, the entire design fit comfortably on 4 layers with no change in electrical performance, saving approximately 30 percent on fabrication cost across their 5,000-unit production run.

Board Dimensions and Panel Utilization

The physical size of your PCB affects cost in ways that extend well beyond the obvious material consumption. PCB fabrication facilities work with standardized production panels — typically 18 by 24 inches (457 by 610 mm) or 16 by 22 inches (406 by 559 mm) depending on the factory's equipment. Your individual boards are arranged on these panels in an array, and the efficiency of that arrangement directly determines your per-unit cost.

Panel utilization is the ratio of usable board area to total panel area. When your board dimensions do not divide cleanly into the working panel dimensions (after subtracting the tooling rails, typically 5 to 10 mm on each side), you end up with wasted panel space that you are still paying for. A board measuring 105 mm by 75 mm might yield 24 units per panel, but adjusting the outline to 100 mm by 70 mm could yield 30 units — a 25 percent improvement in utilization that translates almost directly into per-unit cost savings.

Before finalizing your board outline, it is worth discussing panelization options and depaneling methods with your manufacturer. Even small adjustments of 2 to 3 mm in board dimensions can shift the panelization from an inefficient arrangement to an optimal one. We routinely provide panelization recommendations to customers during our DFM review process, and this single step has saved clients anywhere from 8 to 20 percent on unit cost.

Irregular board shapes — non-rectangular outlines with cutouts, slots, or internal routing — present additional challenges. These shapes reduce panelization density and require more complex CNC routing during depaneling, adding both material waste and process time. Where your mechanical enclosure allows it, maintaining rectangular or near-rectangular board outlines is one of the simplest ways to keep manufacturing cost down.

Via Technology: Through-Hole to Microvia Cost Ladder

Via technology selection has become an increasingly significant cost driver as designs push toward higher density. The cost difference between standard through-hole vias and advanced microvia structures can be substantial, and choosing the right via technology for each interconnect in your design is a critical cost optimization opportunity.

Standard mechanical through-hole vias — drilled with a carbide bit and plated through the full board thickness — are by far the most economical option. They can be drilled at high speed, require no special processing, and the tooling lasts thousands of hits. This is your baseline cost.

Blind vias, which connect an outer layer to one or more inner layers without passing through the entire board, require sequential lamination. The board must be partially fabricated, drilled, plated, and then laminated with additional layers. This sequential build process typically adds 30 to 50 percent to fabrication cost compared to an equivalent board using only through-hole vias.

Buried vias, connecting two or more inner layers without reaching either surface, carry a similar cost premium to blind vias since they also require sequential lamination. The cost compounds when a design uses both blind and buried vias, as each type may require its own lamination sequence.

Microvias — laser-drilled holes typically 75 to 150 micrometers in diameter — are the most expensive via technology. They require laser drilling equipment, specialized plating processes, and careful fill and planarization. For a detailed breakdown of how microvia structures affect pricing, our guide on HDI PCB cost factors covers the topic in depth.

The practical optimization here is straightforward: use through-hole vias wherever your design density allows. Reserve blind and buried vias for areas where routing density genuinely demands them, and specify microvias only when component pitch or layer interconnect requirements make them necessary. In our experience, roughly 20 percent of designs we review specify blind or buried vias that could be replaced with through-hole vias after minor routing adjustments.

Drill Size and Hole Count Optimization

Drilling is one of the most time-intensive steps in PCB fabrication, and the number of holes in your design — along with their sizes — has a direct impact on manufacturing time and cost. A typical production panel might contain tens of thousands of drill hits, and the drilling machine's cycle time is largely determined by hole count and the number of tool changes required.

Smaller drill sizes mean slower drilling speeds, faster tool wear, and more frequent bit replacements. The industry standard minimum for mechanically drilled holes is 0.2 mm (8 mil) finished hole size, and going below this threshold moves into laser drilling territory with its associated cost premium. For through-hole vias, a finished hole size of 0.3 mm (12 mil) or larger keeps drilling in the fast, economical range. Dropping to 0.2 mm finished size roughly doubles the drilling cost per hole due to reduced hit speed and increased breakage rates.

For a deeper understanding of how drill hole sizing, finished tolerances, and plating allowances interact, reviewing the mechanical drilling specifications is worthwhile before finalizing your via and pad design.

Reducing the total number of unique drill sizes in your design also saves cost by minimizing tool changes. Each tool change on a CNC drilling machine takes several seconds, and across a production panel with thousands of holes, these seconds add up. If your design uses fifteen different drill sizes, consolidating to eight or ten — where tolerances allow — can reduce drilling cycle time by 10 to 15 percent.

The most effective drill optimization combines three strategies: use the largest via hole size your routing density permits, minimize the total number of unique drill sizes, and avoid specifying holes smaller than 0.3 mm unless the design genuinely requires them.

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Copper Weight Selection and Its Ripple Effects

Copper weight — specified in ounces per square foot — affects more than just the current-carrying capacity of your traces. Heavier copper requires longer etching times, tighter process controls to maintain trace width accuracy, and can necessitate thicker prepreg layers to fill the increased copper topography during lamination.

Standard 1 oz (35 micrometer) copper on outer layers and 0.5 oz (17.5 micrometer) on inner layers represents the most economical choice. Moving to 2 oz outer copper adds approximately 15 to 25 percent to fabrication cost, while 3 oz and heavier copper can double the baseline price due to extended etching, wider minimum trace and space requirements, and specialized lamination parameters.

The ripple effect of heavy copper is important to understand: specifying 2 oz copper forces wider minimum trace and space specifications (typically 6 mil minimum instead of 4 mil for 1 oz), which in turn reduces routing density and may push you to additional layers — compounding the cost increase. Where your design requires heavy copper only in specific areas (such as power distribution), consider using mixed copper weights on different layers rather than specifying heavy copper across the entire board.

Surface Finish: Matching Cost to Application Requirements

The surface finish applied to exposed copper pads is one of the more visible cost decisions, and it is also one where we see the most frequent over-specification. Different finishes serve different purposes, and selecting the right one for your application can save meaningful cost.

Here are the relative cost multipliers for common surface finishes, based on our current production pricing:

OSP (Organic Solderability Preservative): 1.0x — lowest cost, adequate shelf life for immediate assembly
HASL (Hot Air Solder Leveling): 1.05x to 1.1x — robust and well-proven, but creates uneven pad surfaces
Lead-Free HASL: 1.1x to 1.15x — slightly higher temperature process, same surface evenness limitations
Immersion Tin: 1.15x to 1.2x — flat surface, good solderability, limited shelf life
ENIG (Electroless Nickel Immersion Gold): 1.3x to 1.5x — excellent flatness and shelf life, industry standard for fine-pitch
ENEPIG: 1.5x to 1.8x — premium finish for wire bonding and mixed-technology assemblies

For a comprehensive comparison of each finish's performance characteristics and cost implications, our surface finish selection guide provides detailed tradeoff analysis.

The key insight from a cost perspective is that many designs specify ENIG when OSP or HASL would perform identically in the application. If your board uses standard-pitch components (0.5 mm pitch and above), does not require wire bonding, and will be assembled within a few weeks of fabrication, OSP provides perfectly adequate solderability at a fraction of the ENIG cost. The savings become meaningful at volume — on a 10,000-unit run, switching from ENIG to OSP can save several hundred dollars on fabrication alone.

Material Selection: The Cost Ladder From FR-4 to High-Frequency Laminates

PCB substrate material selection follows a steep cost progression, and the differences are far more dramatic than most engineers realize until they see their first Rogers or Megtron quote.

Standard FR-4 (Tg 130-140C) is the baseline, and it covers the vast majority of commercial and industrial applications. Moving up the material ladder:

Standard FR-4 (Tg 130-140C): 1.0x baseline
Mid-Tg FR-4 (Tg 150-155C): 1.05x to 1.1x — minimal cost increase for improved thermal reliability
High-Tg FR-4 (Tg 170C+): 1.1x to 1.2x — required for lead-free assembly with multiple reflow cycles
Low-loss FR-4 variants (Panasonic Megtron 4, Isola FR408HR): 1.3x to 1.6x
High-frequency laminates (Megtron 6, Isola Astra MT77): 2.0x to 3.0x
PTFE/Rogers materials (RO4003C, RO4350B): 3.0x to 5.0x
Advanced Rogers (RT/duroid 5880, RO3003): 5.0x to 8.0x and above

The practical optimization here is twofold. First, do not specify high-Tg material unless your assembly process or operating environment genuinely demands it. Standard FR-4 handles single-pass lead-free reflow just fine for most designs. Second, for mixed-signal designs that require low-loss material only on specific layers (such as an RF front-end on layers 1-2 with digital logic on inner layers), hybrid stackups that combine Rogers on outer layers with standard FR-4 cores can reduce material cost by 30 to 50 percent compared to an all-Rogers construction.

Tolerance Specifications: When Tighter Means Wasted Money

Every tightened tolerance on your fabrication drawing maps to slower production speeds, more process steps, or increased scrap rates — all of which drive up cost. The most common tolerance-related over-specifications we encounter involve trace width and spacing, hole positional accuracy, and board thickness.

Standard PCB manufacturing capabilities have advanced significantly. Most facilities comfortably produce 4 mil (100 micrometer) trace and space on inner layers and 3.5 mil on outer layers without any special processing or cost premium. Specifying 3 mil trace and space, however, pushes into fine-line processing territory, requiring direct imaging (instead of conventional photolithography), premium dry film, and tighter etch process controls. The cost impact is typically 15 to 25 percent above standard processing.

Similarly, standard positional hole accuracy of plus or minus 3 mil is achievable on any modern CNC drilling machine at full production speed. Tightening this to plus or minus 2 mil or below requires slower drilling speeds and may necessitate x-ray registration for inner layer alignment, adding both time and cost.

The optimization principle is simple: specify only the tolerances your design actually needs. Review your fabrication notes and remove any overly tight specifications that were carried over from previous projects or template drawings. If your design works within standard manufacturing tolerances, say so explicitly — it avoids potential misinterpretation by the fabricator and keeps your board in the standard-cost processing lane.

Impedance Control: Knowing When to Specify It

Controlled impedance is essential for high-speed digital and RF designs, but it is also one of the most commonly over-applied specifications. Adding impedance control to a fabrication order typically increases cost by 5 to 15 percent because it requires the manufacturer to build dedicated test coupons on every production panel, measure impedance using time-domain reflectometry (TDR), and adjust dielectric thickness to hit target values within tolerance.

Our guide to controlled impedance PCB pricing and cost optimization covers this topic in detail, but the short version is this: impedance control is justified for signal traces operating above roughly 100 MHz, USB 2.0 and above, HDMI, PCIe, Ethernet differential pairs, and RF transmission lines. It is not needed for power traces, low-speed GPIO lines, I2C buses, SPI at modest clock rates, or analog signals well below the frequency where transmission line effects matter.

We regularly review designs where impedance control is specified on all layers uniformly, including layers that carry only power distribution and slow control signals. Restricting impedance requirements to only the layers and traces that need them reduces the number of test coupon measurements and can bring the impedance cost adder from 15 percent down to 5 percent.

Solder Mask and Silkscreen: Small Choices With Cost Impact

Solder mask and silkscreen are often treated as afterthoughts, but non-standard specifications in either can add unexpected cost. Standard green LPI (Liquid Photo-Imageable) solder mask on both sides is included in the base fabrication price. Switching to matte black, white, red, blue, or other specialty colors adds a modest 3 to 8 percent premium — mostly driven by smaller batch sizes for non-green inks, longer UV cure times for darker colors, and additional inspection steps since defects are harder to spot on dark masks.

White silkscreen on green solder mask is the standard, lowest-cost combination. Black silkscreen or any combination requiring multiple silkscreen colors adds both material and an additional print pass.

For production volumes, stick with green solder mask and white silkscreen unless your product requirements or brand guidelines dictate otherwise. The cost is small per unit, but it adds up across large runs and — perhaps more importantly — non-standard colors can extend lead time by 1 to 2 days if the manufacturer needs to set up a dedicated solder mask line.

Panelization Strategy for Assembly Cost Reduction

While panelization directly affects fabrication cost through panel utilization (discussed earlier), its impact on assembly cost is equally significant. A well-designed assembly panel reduces pick-and-place cycle time, minimizes changeover overhead, and improves throughput at every station in the SMT line.

The key panelization decisions that affect assembly cost include array size (more boards per panel means fewer panel loads per batch), panel rail width and fiducial placement (affects machine handling reliability), depaneling method (V-score is cheaper than tab routing but requires straight edges), and component keepout from panel edges and scoring lines.

For detailed guidance on panelization methods including V-score and tab routing, our panelization guide covers the mechanical design considerations. From a cost perspective, the most important principle is to discuss panelization with both your fabricator and assembler early in the design process. We have seen cases where a panelization arrangement optimized for fabrication efficiency turned out to be suboptimal for assembly, and vice versa. Getting both parties aligned before finalizing the panel design prevents costly redesigns.

Order Quantity Economics: Prototype to Production Pricing

Understanding how pricing scales with quantity helps you make better procurement decisions. PCB manufacturing has significant fixed costs — CAM engineering, tooling, panel setup, first-article inspection — that are amortized over the order quantity. This creates a steep cost curve at low volumes that flattens as quantities increase.

Here is a representative cost progression for a standard 4-layer board, normalized to the 1,000-unit price:

5 units (prototype): 8x to 15x per unit
10 units: 5x to 10x per unit
50 units: 2.5x to 4x per unit
100 units: 1.8x to 2.5x per unit
500 units: 1.2x to 1.5x per unit
1,000 units: 1.0x baseline
5,000 units: 0.7x to 0.85x per unit
10,000 units and above: 0.5x to 0.7x per unit

The steepest savings occur between 50 and 500 units, where fixed costs are being diluted most rapidly. Above 1,000 units, additional cost reduction comes primarily from purchasing efficiency and production line optimization rather than fixed-cost amortization.

For prototype and low-volume orders, the most effective cost strategy is to ensure your design is fully optimized before ordering. The per-unit cost of prototypes is so high that any design revision requiring a second prototype run effectively doubles your prototyping expense. Running a thorough DFM check using a pre-order checklist before submitting prototype orders is one of the highest-ROI activities in the entire development cycle.

The Hidden Costs: Engineering Queries, Revisions, and DFM Failures

The costs discussed so far are the visible, line-item expenses on your fabrication quote. But in our experience, the hidden costs of poorly optimized designs often exceed the direct fabrication savings that careful optimization achieves. These hidden costs rarely appear on an invoice, but they consume engineering time, extend schedules, and introduce risk.

Engineering queries are the most common hidden cost. When our CAM engineers review incoming Gerber files and find DFM violations — traces too close to board edges, acid traps in copper pours, annular rings below minimum, missing solder mask dams between fine-pitch pads — they must halt the order and send a query to the designer. Each query-response cycle adds 1 to 3 business days to the production schedule. Across our production data, approximately 30 percent of first-time customer orders trigger at least one engineering query, and the average resolution time is 1.5 business days.

Design revisions are even more expensive. When a DFM issue is discovered after fabrication has already begun — perhaps a drill file does not match the Gerber layers, or a specification conflict is found during inner layer imaging — the work-in-progress panels may need to be scrapped and the order restarted. This can add a full production cycle to the lead time and, depending on the order terms, may result in additional charges for wasted materials and machine time.

Then there is the cost of DFM failures that are not caught until assembly or field deployment. A marginal annular ring that passes fabrication but causes pad lifting during wave soldering, an inadequate thermal relief that creates tombstoning during reflow, or a trace impedance mismatch that only manifests at temperature extremes — these failures are astronomically expensive compared to the fabrication cost they could have been prevented by.

The solution is straightforward: invest in a thorough DFM review before submitting your files. Use your EDA tool's built-in DFM checks, review your fabrication drawing against your manufacturer's published capabilities, and take advantage of any free DFM review services offered by your fabricator. The 30 minutes spent on pre-submission DFM review can save weeks of schedule and thousands of dollars in revision and failure costs.

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A Real Optimization Example: Before and After

To illustrate how these principles compound, consider a real design optimization we performed during a customer's DFM review. The original design was a wireless sensor module with the following specifications: 6-layer stackup, ENIG finish, 2 oz outer copper, controlled impedance on all layers, high-Tg FR-4, 0.2 mm minimum drill size, and irregular board outline with internal cutouts.

After reviewing the schematic and layout constraints, our engineering team proposed the following changes. The layer count was reduced from 6 to 4 by consolidating the power distribution and re-routing two signal layers. The surface finish was changed from ENIG to OSP since the boards would be assembled within one week of delivery. Copper weight was reduced from 2 oz to 1 oz on outer layers after confirming the current requirements were well within 1 oz trace capacity. Impedance control was restricted to only the RF signal layer instead of all layers. Material was changed from high-Tg FR-4 to standard FR-4 since the device operates at room temperature with a single reflow pass. Minimum drill size was increased from 0.2 mm to 0.3 mm by adjusting via pad sizes. The board outline was squared off, eliminating internal cutouts by moving one connector to the board edge, which improved panel utilization from 18 to 26 units per panel.

The cumulative cost impact across a 2,000-unit production order:

Layer reduction (6 to 4): saved 28 percent
Surface finish (ENIG to OSP): saved 8 percent
Copper weight (2 oz to 1 oz): saved 5 percent
Impedance control (all layers to one): saved 6 percent
Material grade (high-Tg to standard): saved 4 percent
Drill optimization: saved 3 percent
Panel utilization improvement: saved 15 percent

The total fabrication cost reduction was approximately 45 percent. The board performed identically in all functional and environmental testing. No electrical specification was compromised — the savings came entirely from removing unnecessary over-specification and optimizing mechanical design for manufacturing efficiency.

Putting It All Together: A Cost Optimization Checklist

Designing for cost does not mean designing a lesser product. It means understanding the manufacturing implications of every specification and making deliberate choices about where to invest and where standard parameters will serve the design equally well. The engineers who consistently achieve the lowest manufacturing costs are not the ones who cut corners — they are the ones who understand which specifications actually matter for their application and which are just adding cost for no functional benefit.

Start with the highest-impact decisions: layer count, board dimensions, and via technology. These three factors alone typically account for 60 to 70 percent of the fabrication cost delta between an optimized and unoptimized design. Then work through material selection, surface finish, copper weight, and tolerance specifications. Finally, review panelization strategy with your manufacturer and ensure your files are clean before submission.

Every dollar saved in fabrication is a dollar that can be invested in better components, more thorough testing, or competitive pricing for your end product. In a market where hardware margins are perpetually under pressure, designing for cost is not optional — it is a core engineering competency.

If you are preparing a design for production and want a manufacturer's perspective on cost optimization opportunities, our engineering team reviews Gerber files at no charge and provides specific, actionable recommendations for reducing manufacturing cost while maintaining your design's performance requirements.

Reviewed by AtlasPCB Engineering Team — 15+ years in advanced PCB fabrication for RF, HDI, and rigid-flex applications.

Want a manufacturer's take on your specific design? Our engineering team reviews Gerber files and identifies cost-saving opportunities at no charge. Get a free DFM review at AtlasPCB.

Originally published at atlaspcb.com

Flex PCB Stiffener Design Guide: What Your Fab Needs You to Know

AtlasPCBEngineering — Mon, 31 Aug 2026 00:21:01 +0000

Flexible circuits solve a fundamental packaging problem — they bend, fold, and route through three-dimensional enclosures where rigid boards cannot fit. But that same flexibility becomes a liability the moment you need to mount a BGA, solder a ZIF connector, or run the board through a pick-and-place machine. The circuit that bends beautifully through a hinge also warps under reflow temperatures, deflects during connector insertion, and resists accurate placement in automated assembly fixtures.

The flex PCB stiffener exists to resolve this tension. It is a non-electrical reinforcement plate bonded to specific areas of a flexible circuit, providing local rigidity exactly where the design demands it while preserving flexibility everywhere else. In our flex fabrication lines, we estimate that roughly six out of every ten assembly-related defects on flex boards — tombstoning, solder bridging, connector contact failures — trace directly to inadequate stiffener specification or incorrect placement. The stiffener is not an afterthought to add during assembly; it is a design decision that should be made alongside the circuit layout from the earliest schematic review.

This guide covers the four primary stiffener materials, explains how to select the right thickness for your application, compares attachment methods and their reliability implications, and provides the exact fab drawing callout format your manufacturer needs to build it correctly.

When a Stiffener Solves Your Problem and When Rigid-Flex Is the Better Answer

Before specifying any stiffener, the first question every design team should answer is whether the board should be a stiffened flex or a true rigid-flex PCB. Both approaches provide rigid areas on a flexible circuit, but they differ fundamentally in cost, capability, and manufacturing complexity.

A stiffened flex circuit is a standard flex board with separate rigid plates bonded to it after fabrication. The stiffener does not contain any electrical traces or vias — it is purely mechanical reinforcement. This approach works well when the design has one or two areas that need rigidity for component mounting, when the component density in those areas is moderate (discrete passives, simple ICs, connectors), and when the rigid sections do not require multilayer routing beneath the components. The manufacturing process is straightforward: fabricate the flex circuit, cut the stiffeners from sheet stock, apply adhesive, and bond them in a lamination press or by hand for PSA types.

A rigid-flex PCB integrates the rigid sections directly into the laminated stackup during fabrication. The rigid zones contain copper layers, vias, and routing just like a conventional multilayer board, and the flex zones transition seamlessly through the layer stack. This approach becomes necessary when the rigid areas need via-in-pad routing under fine-pitch BGAs, when three or more separate rigid zones are required (each stiffener adds a separate bonding operation and alignment step), or when the design demands controlled impedance routing in the rigid sections that the stiffener approach cannot provide.

The cost difference is significant. A two-layer flex circuit with two FR-4 stiffeners typically costs 30 to 50 percent less than an equivalent rigid-flex design, because the rigid-flex process requires additional lamination cycles, sequential drilling operations, and tighter registration tolerances across the rigid-to-flex transitions. However, that cost advantage disappears quickly as the number of stiffened zones increases beyond two, because each additional stiffener requires its own cutting, alignment, and bonding step. For designs requiring three or more rigid areas with any routing complexity, rigid-flex almost always delivers better value and higher reliability.

The Four Stiffener Materials and When to Use Each

Stiffener material selection determines the thickness profile, thermal behavior, weight, and cost of the finished assembly. The four materials used in production — FR-4 glass epoxy, polyimide film, stainless steel, and aluminum — each address different application requirements, and choosing the wrong one creates problems that cannot be corrected during assembly.

FR-4 Glass Epoxy

FR-4 is the default stiffener material for general-purpose flex circuits and the one you should specify unless a specific requirement pushes you toward an alternative. It provides the highest rigidity per unit cost, machines cleanly with standard routing equipment, and is available in standard laminate gauges of 0.2 mm, 0.4 mm, 0.8 mm, 1.0 mm, and 1.6 mm. The glass-fiber reinforcement gives FR-4 excellent dimensional stability through reflow soldering temperatures, and its coefficient of thermal expansion in the X-Y plane (14 to 17 ppm per degree C) is close enough to the polyimide flex substrate (17 ppm per degree C) to avoid significant thermal stress at the bond interface during assembly.

FR-4 stiffeners are the correct choice for SMT component mounting areas where BGAs, QFPs, and discrete packages need a flat, stable platform during reflow. They work well for through-hole connector zones, card-edge interfaces, and any area where the primary requirement is mechanical rigidity at minimum cost. In production volumes above 1000 pieces, an FR-4 stiffener measuring 20 by 15 mm with PSA attachment typically adds 0.03 to 0.08 USD per piece to the flex circuit cost.

Polyimide Film

Polyimide stiffeners use the same base material as the flex substrate itself — Kapton or equivalent films from DuPont, SKC Kolon, or Kaneka — and are available in standard thicknesses of 0.025 mm (1 mil), 0.05 mm (2 mil), 0.075 mm (3 mil), 0.125 mm (5 mil), and 0.225 mm (9 mil) through single or laminated layers. The material's excellent CTE match with the flex substrate eliminates differential thermal expansion stress at the bond line, and its temperature resistance exceeding 260 degrees C makes it fully compatible with lead-free reflow profiles.

The primary application for polyimide stiffeners is ZIF (zero insertion force) connector interfaces, where the total insertion thickness — flex substrate plus adhesive layer plus stiffener — must match the connector manufacturer's specification within a tolerance of plus or minus 0.05 mm. A typical FPC-to-ZIF interface uses a 0.05 mm flex substrate, a 0.025 mm adhesive layer, and a 0.125 mm polyimide stiffener to achieve a total insertion thickness of 0.20 mm. This level of thickness precision is difficult to achieve with FR-4, whose minimum practical gauge of 0.2 mm is already too thick for many ZIF connector specifications. Polyimide stiffeners cost approximately 0.02 to 0.05 USD per piece in volume, making them the most economical option for thin-profile applications.

Stainless Steel

Stainless steel stiffeners (typically SUS304 grade) deliver the highest rigidity in the thinnest profile of any stiffener material. A 0.2 mm stainless steel stiffener provides roughly equivalent bending stiffness to a 0.8 mm FR-4 stiffener, which makes it the material of choice when vertical space is severely constrained but mechanical rigidity cannot be compromised. Typical thicknesses range from 0.1 mm to 0.5 mm, with 0.2 mm and 0.3 mm being the most common production gauges.

Beyond mechanical support, stainless steel stiffeners can serve a secondary function as EMI shielding when grounded to the circuit's ground plane through conductive adhesive or spring contacts. This dual-purpose application is common in smartphone and wearable device flex assemblies, where the stiffener simultaneously supports a connector area and shields an adjacent RF section. The trade-off is weight — stainless steel's density of 7.9 grams per cubic centimeter is more than four times that of FR-4 — and cost, which runs 0.08 to 0.15 USD per piece due to precision machining requirements and the harder material's slower cutting speed.

Aluminum

Aluminum stiffeners provide mechanical support combined with thermal management capability that no other stiffener material can match. With thermal conductivity of 205 watts per meter-kelvin compared to 0.3 for FR-4, an aluminum stiffener acts as an effective heatsink for power components, LED arrays, and voltage regulators mounted on flex circuits. Standard thicknesses range from 0.25 mm to 1.0 mm, and the material is typically alloy 5052 or 6061 for its combination of machinability and thermal performance.

The primary applications are LED flex strips used in automotive interior lighting, power conversion circuits in compact battery-powered devices, and any design where a component on the flex circuit generates enough heat to require spreading beyond the copper traces alone. Aluminum's CTE of 23 ppm per degree C is notably higher than polyimide's 17 ppm, which means thermal stress at the adhesive bond line is a design concern for applications experiencing large temperature swings. In our production experience, aluminum stiffeners bonded with PSA to flex circuits operating between minus 20 and plus 85 degrees C show measurable adhesive creep after approximately 500 thermal cycles, which is why we recommend thermal bonding with a filled epoxy adhesive for any aluminum stiffener application in automotive or industrial environments.

How to Choose the Right Stiffener Thickness

Selecting stiffener thickness is not a matter of choosing the thickest option available for maximum rigidity. The correct thickness is determined by the specific functional requirement at each stiffened location, and different areas on the same flex circuit may require different stiffener thicknesses and even different materials.

For ZIF connector interfaces, thickness selection is driven entirely by the connector specification. Every ZIF connector has a specified insertion thickness — the total thickness of the flex circuit plus stiffener that the connector's contacts are designed to engage. A Molex 54132 series connector, for example, specifies an insertion thickness of 0.30 mm plus or minus 0.05 mm. If your flex substrate is 0.11 mm thick (a common two-layer flex construction with coverlay on both sides) and your adhesive layer adds 0.025 mm, the stiffener must be exactly 0.165 mm — which means a 0.175 mm polyimide stiffener (0.125 mm plus a 0.05 mm laminated layer) or a precision-ground polyimide at 0.165 mm. Getting this tolerance wrong by even 0.08 mm means the connector either cannot close properly or makes unreliable contact, and the defect is invisible to electrical testing until the product experiences vibration or thermal cycling in the field.

For SMT component mounting areas, the primary requirement is sufficient rigidity to maintain flatness during reflow soldering. The stiffener must prevent the flex substrate from warping under the thermal stress of the reflow profile, which can produce localized deformation of 0.5 to 1.0 mm in an unstiffened flex circuit — more than enough to cause tombstoning on 0402 passives or solder bridging on fine-pitch QFP leads. FR-4 at 0.8 mm thickness provides adequate rigidity for most SMT areas up to approximately 30 by 30 mm. For larger stiffened areas or designs with heavy components (large transformers, shielding cans, or connectors with significant mass), 1.0 mm or 1.6 mm FR-4 is appropriate. The penalty for over-specifying thickness is increased overall assembly height and potentially increased material cost, but it is far smaller than the penalty for under-specifying thickness and experiencing reflow defects.

For mechanical mounting and fixture reference areas, stiffener thickness should match the expected mechanical loads. If the flex circuit will be screwed into an enclosure through mounting holes in the stiffened area, the stiffener must be thick enough to distribute the screw clamping force without deforming. FR-4 at 1.0 mm or thicker, or stainless steel at 0.3 mm, is typical for screw-mounted applications.

Attachment Methods and Reliability Implications

The method used to bond a stiffener to a flex circuit has direct implications for assembly cost, rework capability, and long-term reliability under thermal and mechanical stress.

Pressure-sensitive adhesive (PSA) is the simplest and most economical attachment method. PSA tapes — typically 3M 467MP or 468MP acrylic transfer adhesive — are applied to the stiffener surface, and the stiffener is positioned onto the flex circuit using alignment fixtures and pressed into place. The bond forms immediately at room temperature with no curing step required. PSA attachment costs approximately 0.01 to 0.02 USD per stiffener in production and allows rework if the stiffener needs to be repositioned or replaced. However, PSA adhesion strength is lower than thermal bonding, and the acrylic adhesive degrades under extended thermal cycling. In our reliability testing, PSA-bonded FR-4 stiffeners begin showing edge delamination after approximately 200 cycles between minus 40 and plus 85 degrees C at 30-minute dwell times. For IPC Class 1 consumer electronics with expected operating temperature ranges of 0 to 60 degrees C, PSA adhesive provides perfectly adequate reliability for the product's expected life.

Thermal bonding uses thermoset adhesive films — typically modified epoxy or acrylic adhesives that cure under heat and pressure in a lamination press. The bond is permanent and provides significantly higher adhesion strength than PSA, with peel strength values typically exceeding 1.0 N per mm compared to 0.3 to 0.5 N per mm for PSA. Thermal bonding is the required attachment method for IPC Class 3 applications in aerospace, medical, and automotive environments per IPC-2223 guidelines, and it is strongly recommended for any application where the assembly will experience more than 500 thermal cycles or sustained operating temperatures above 85 degrees C. The trade-off is cost — thermal bonding adds a lamination press cycle to the manufacturing process, increasing the per-stiffener cost by approximately 0.02 to 0.04 USD and adding 1 to 2 days to the production lead time.

Structural epoxy adhesive applied as a liquid or paste provides a middle ground between PSA convenience and thermal bonding reliability. Epoxy adhesives offer strong adhesion (0.7 to 1.2 N per mm peel strength) and can be applied and cured without a lamination press, though they require fixture clamping during the cure cycle. This approach is most common for aluminum and stainless steel stiffeners, where the metallic surface benefits from the epoxy's superior wetting compared to PSA tape.

Design Rules and Fab Drawing Specification

The stiffener specification on your fabrication drawing is the document your manufacturer uses to cut, prepare, and bond the stiffener to your flex circuit. An incomplete or ambiguous specification guarantees questions during engineering review, which delays your build start, or worse, results in the manufacturer making assumptions that may not match your intent.

Every stiffener callout on a fab drawing should include the following information: the stiffener material and grade (for example, "FR-4 per IPC-4101/21, Tg 150C minimum"), the thickness with tolerance ("0.8 mm plus or minus 0.08 mm"), the outline dimensions referenced to board datum features, the attachment method and adhesive specification ("PSA, 3M 467MP or equivalent" or "thermal bond, modified epoxy film, cure 170C at 60 minutes"), and the side of the flex circuit where the stiffener is applied.

The stiffener outline should be defined on a dedicated mechanical layer in your CAD tool — typically a user-defined layer labeled "Stiffener" or "Mechanical 3" — and exported as a separate Gerber file or included in your fabrication drawing as a dimensioned detail. Include reference dimensions from the board outline or datum holes to the stiffener edges, with a placement tolerance of plus or minus 0.15 mm for standard production.

Clearance from bend zones is the single most critical dimensional requirement in stiffener design. IPC-2223 recommends a minimum of 1.5 mm between the nearest stiffener edge and the beginning of any bend zone, measured along the flex substrate surface. In our production standard, we specify 2.0 mm minimum clearance to account for adhesive squeeze-out during bonding (which can extend 0.3 to 0.5 mm beyond the stiffener edge) and the placement tolerance of the stiffener itself. Insufficient clearance creates a stress concentration at the stiffener edge during bending, which concentrates the bend radius into a sharp crease rather than distributing it across the designed bend zone. This crease causes copper trace cracking that typically manifests as an intermittent open circuit — the most difficult fault to diagnose in a flex circuit assembly. For more on bend radius design and copper fatigue in flex circuits, our dedicated guide covers the engineering in depth.

Clearance from the board edge should be a minimum of 0.5 mm to prevent the stiffener from interfering with routing or V-score depaneling operations. If the flex circuit includes a coverlay opening at a component pad area, verify that the stiffener does not overlap the coverlay boundary — the stiffener should extend at least 0.3 mm beyond the coverlay opening on all sides to ensure the adhesive bond lands on coverlay rather than exposed copper.

How Stiffeners Affect SMT Assembly

Stiffener placement has a direct impact on SMT assembly yield that many designers overlook until they encounter problems on the production line. The stiffener is not just a mechanical reinforcement — it is a thermal mass that alters the reflow profile, a reference surface for pick-and-place equipment, and a structural element that affects how the flex circuit behaves during automated handling.

During reflow soldering, the stiffener absorbs heat and creates a thermal lag between the stiffened and unstiffened regions of the flex circuit. A 1.0 mm FR-4 stiffener measuring 25 by 20 mm adds approximately 3 to 5 seconds to the time required for the solder joints beneath it to reach peak reflow temperature, compared to solder joints on the unstiffened flex substrate adjacent to it. For standard SAC305 lead-free solder with a liquidus temperature of 217 degrees C and a typical reflow peak of 240 to 250 degrees C, this delay is usually within acceptable limits. However, for large stiffened areas exceeding 40 by 40 mm, or for stainless steel and aluminum stiffeners with significantly higher thermal mass, the reflow profile must be characterized with thermocouples placed on both the stiffened and unstiffened surfaces to verify that all joints reach liquidus temperature for the required time above liquidus (typically 60 to 90 seconds for SAC305).

Pick-and-place machines use the stiffened surface as a mechanical reference for part placement. If the stiffener is on the bottom side of the flex circuit (the more common configuration), it provides the flat reference that the board support system needs to hold the flex circuit stable during component placement on the top side. If components are mounted on the same side as the stiffener, the stiffener edge creates a step change in surface height that the pick-and-place nozzle must account for — ensure that no component placement zone is within 1.0 mm of a stiffener edge to avoid nozzle interference.

Common Stiffener Design Mistakes and How to Avoid Them

In our engineering review process, which evaluates every incoming flex PCB design before production begins, stiffener-related issues account for approximately 15 percent of all DFM findings on flex circuit orders. The following patterns appear repeatedly and are worth understanding before your design reaches the review stage.

Insufficient bend zone clearance is the most common and most consequential stiffener design error. Engineers who place the stiffener edge within 1 mm of a bend zone often do so to maximize the stiffened area for component mounting, not realizing that the stress concentration at the stiffener edge will cause copper fatigue cracking within the first few hundred bend cycles. The failure mode is progressive — the circuit works perfectly during initial testing but develops intermittent opens after thermal cycling or mechanical flexing in the field. Always maintain at least 2 mm clearance, even if it means moving a component or reducing the stiffened area.

Incorrect thickness for ZIF connector mating is the second most common issue. The designer specifies a stiffener material and thickness based on general rigidity requirements without verifying the resulting total insertion thickness against the connector's datasheet. The resulting assembly is either too thick to insert into the connector housing or too thin to make reliable contact. This mistake is particularly expensive because it is typically discovered during assembly, after the flex circuits and stiffeners have already been fabricated. Always calculate the full stack: flex substrate thickness plus adhesive thickness plus stiffener thickness, and verify that the sum falls within the connector's specified insertion thickness tolerance.

Using PSA adhesive in a high-reliability application happens when the designer does not specify the attachment method on the fab drawing, and the manufacturer defaults to PSA because it is simpler and cheaper. The assembly passes initial testing but fails in the field after thermal cycling degrades the adhesive bond. For any application classified as IPC Class 2 with extended thermal cycling requirements or any IPC Class 3 application, specify thermal bonding explicitly on the fabrication drawing.

Forgetting to account for stiffener thickness in the overall assembly height causes mechanical interference when the flex circuit is installed in its enclosure. A flex circuit with a 1.0 mm FR-4 stiffener on one side has a total local thickness of approximately 1.2 mm (flex substrate plus adhesive plus stiffener), which may exceed the clearance available in a tightly packaged consumer device. Always include stiffener thickness in your mechanical 3D model and verify clearance against the enclosure design.

Not specifying adhesive type on the fabrication drawing leaves a critical reliability parameter to your manufacturer's discretion. Manufacturers will default to the most cost-effective option consistent with the order's IPC class, but if your specific application has requirements beyond the standard class definition — such as extended temperature range, chemical resistance, or vibration durability — those requirements must be stated explicitly.

For a comprehensive walkthrough of pre-production design verification including stiffener checks, our complete DFM checklist covers the full scope of flex and rigid-flex design review. You can also find detailed cost optimization strategies in our flex PCB pricing guide, which includes stiffener material and attachment method as cost variables in the breakdown.

Reviewed by AtlasPCB Engineering Team

This article was originally published on AtlasPCB Engineering Blog. AtlasPCB specializes in flex, rigid-flex, and HDI PCB manufacturing for hardware engineers worldwide.

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