DEV Community: ai pics

The Quiet Failure Mode in a 12 V to 5 V Buck Converter

ai pics — Mon, 31 Aug 2026 03:40:22 +0000

A 12 V to 5 V buck converter can look perfect on the schematic and still fail during a load step. The output may dip too far, ring for several microseconds, or restart when a motor, radio, or processor wakes up. The usual instinct is to blame the regulator IC. In practice, the inductor, compensation network, current loop, and measurement setup are just as likely to be responsible.

Start with the current waveform

The first useful measurement is not the multimeter reading. It is the input and output current waveform during the event that causes the failure. A converter rated for 3 A may be perfectly comfortable at a steady 2 A and still struggle with a 2 A-to-5 A transient if the inductor saturates or the control loop responds slowly.

Record the load-step amplitude, rise time, repetition rate, and minimum output voltage. A short pulse and a continuous overload are different design cases. Also check whether the load has a large input capacitor. That capacitor can make the first edge look acceptable while the converter later runs out of current and hits thermal or cycle-by-cycle limits.

Inductor saturation is a dynamic problem

The inductor current is not just the DC output current. In a simplified buck converter, the peak current is approximately:

Ipeak = Iout + ΔIL / 2

where ΔIL is the inductor ripple current. The selected part must maintain enough inductance at the actual peak current and temperature. A catalog headline such as “5 A rated” is not sufficient unless the rating definition is understood.

When the core begins to saturate, inductance falls. Ripple current increases, switch current rises, and the converter may become noisier precisely when the load needs clean power. Check the inductance-versus-current curve, saturation definition, copper loss, and temperature rise rather than selecting by nominal inductance alone.

Layout decides which loop the current follows

The high di/dt loop usually contains the input ceramic capacitor, the high-side switch, the low-side path, and the return connection. Keep this loop compact. Place the input capacitor close to the power pins, keep the switch node physically small, and route sensitive feedback traces away from the switching node and inductor.

The feedback divider should return to a quiet ground reference. It should not share a long, high-current copper path with the input capacitor or power-stage return. A converter can have the right compensation values and still oscillate or show excess ripple if the feedback signal measures the wrong ground.

For the first design pass, the power-management IC category at MOZ Electronics is useful for comparing controller functions and regulator architectures. The category is only a starting point; the final choice must be checked against the inductor, switching frequency, current limit, compensation method, and thermal conditions.

Separate control-loop problems from probing problems

A long oscilloscope ground lead can add enough inductance to create ringing that is not present at the load. Measure directly across the output capacitor with a short spring ground, then repeat the measurement at the load connector. If the two waveforms differ, the board or cable impedance is part of the problem.

It is also worth checking whether the ringing frequency changes when the probe position changes. If it does, improve the measurement before changing the design. If it remains stable and appears at both the converter and the load, investigate the control loop, output capacitor ESR, and layout.

Derate before the BOM is frozen

A first-pass review should cover the maximum input voltage, output current, inductor peak current, switch voltage stress, capacitor ripple current, and semiconductor junction temperature. The component derating calculator can help expose a weak voltage or power margin quickly, but it does not replace the manufacturer’s curves or a measured thermal test.

Manufacturing details matter too. A small power board may use large copper pours, thermal vias, and several capacitor sizes. The PCB assembly guidance from MOZPCB is relevant when stencil openings, component orientation, reflow, and inspection coverage can change the final electrical behavior.

A repeatable bring-up sequence

Power the board from a current-limited source with the load disconnected.
Confirm the switching frequency, output voltage, soft-start waveform, and no-load current.
Add a resistive or electronic load in small steps and record ripple and temperature.
Apply the fastest realistic load transient and capture the waveform at both the converter and the load.
Repeat at minimum and maximum input voltage and at the intended enclosure temperature.

The goal is not simply to obtain 5 V on a meter. A reliable buck converter is one whose current path, control signal, thermal margin, and production process remain predictable when the load changes. For broader power-design context, Octatronics’ power and energy application resources are a useful way to connect the converter choice to the final product environment.

USB-C PD 3.1 at 240 W: The Power Number Is Only the Starting Point

ai pics — Fri, 28 Aug 2026 08:20:32 +0000

USB-C Power Delivery has moved far beyond phone charging. The USB-IF says PD 3.1 extends the system to 240 W using the Extended Power Range (EPR), with fixed levels up to 48 V and 5 A. That sounds like a connector upgrade, but it is really a system-level power-design problem.

Why the connector is not the design

A 240 W port needs more than a Type-C receptacle. The source and sink must negotiate a valid PD contract over the CC pins, the cable must support the required current and voltage range, and the power path must survive abnormal conditions. The design also needs a controller, VBUS protection, current sensing, thermal monitoring, and a converter or charger that can operate across the negotiated range.

The 48 V EPR level changes the protection problem. A short-to-VBUS event, hot-plug transient, or ESD strike now has a larger energy budget than a conventional 5 V USB port. A dedicated Type-C protection device can reduce the burden on the main converter, but layout still matters: keep the VBUS protection loop short, place the high-current capacitors close to the port, and separate noisy switching nodes from the CC and USB data paths.

For battery-powered equipment, a bidirectional buck-boost stage is often more flexible than a fixed buck charger. It can accept a wide input range, charge the battery, and provide power back to the USB-C port when the product is used as a source. Texas Instruments’ PMP41115 reference design demonstrates a 240 W USB PD 3.1 battery charger using a four-switch buck-boost topology and reports 97.6% full-load efficiency under its test conditions. That is a reference result, not a guarantee for every board, but it shows the architecture is practical.

A component-level checklist

PD controller: Confirm the required power roles, EPR support, firmware or configuration method, and fault reporting.
VBUS protection: Check the maximum working voltage, short-circuit behavior, ESD rating, and whether protection remains effective during negotiation.
Power switch and magnetics: Select MOSFETs, inductors, and capacitors using switching loss, RMS current, temperature rise, and derating—not headline current alone.
Thermal path: Calculate copper loss and switching loss at the worst-case contract. A compact enclosure may need more copper, airflow, or a different switching frequency.
Cable and compliance: EPR operation depends on the cable and system implementation. Use certified components and run the required compliance tests before advertising a power level.

The power-management section at MOZ Electronics is a useful starting point when comparing controllers and regulators by function. For the PCB, high-current paths should be reviewed together with assembly constraints; MOZPCB’s PCB assembly guidance covers stencil, reflow, polarity, inspection, and first-article risks that can affect a dense power board.

Finally, do not treat derating as paperwork. A simple component derating calculator can expose an obviously weak voltage or power margin before the BOM is frozen. At 240 W, margin is part of the architecture.

The practical takeaway

USB-C PD 3.1 makes one connector capable of powering a much wider class of products, from portable power stations to tools and displays. The winning designs will not be the ones that merely expose a 240 W number. They will be the ones that negotiate power safely, control heat, protect the port, and validate the complete cable–connector–PCB–converter chain.

Drive 16 (or More) LEDs with Two 74HC595 Shift Registers Using Only 3 Arduino Pins

ai pics — Fri, 10 Oct 2025 02:26:27 +0000

Why this project?

Arduino boards run out of GPIO pins fast when you start doing LED patterns or building a control panel. The 74HC595 serial-in/parallel-out (SIPO) shift register lets you trade a few pins (data, clock, latch) for many outputs. Each chip adds 8 outputs, and by chaining IC chips you can scale well beyond 16 channels—limited mainly by signal integrity, update speed, and power.

This guide shows you how to:
Wire two 74HC595s to control 16 LEDs using only three Arduino pins
Add more chips with no code rewrite (change one number)
Use PWM on OE for global brightness
Initialize cleanly to avoid “mystery LEDs” turning on at power-up
Organize code so each LED is addressed by a single channel index (0..N-1)
Bill of Materials

Required

1 × Arduino Uno (or any 5 V-logic compatible board)

2 × 74HC595 shift registers

16 × LEDs

16 × 220 Ω resistors (one per LED; 180–330 Ω is typical—see Current section)

Breadboard(s) and jumper wires

Optional but recommended

2 × 0.1 µF ceramic capacitors (one per 74HC595 between VCC and GND for decoupling)

1 × External 5 V supply if you plan to light many LEDs at once

1 × Potentiometer (if you insist on analog dimming in series—not recommended)

1 × PWM-capable Arduino pin wired to OE for global brightness (recommended)

How the 74HC595 Works (Quickly)

DS (SER, pin 14): Data in (one bit per clock)

SH_CP (SRCLK, pin 11): Shift clock; on rising edge the bit on DS enters the shift register

ST_CP (RCLK, pin 12): Latch clock; rising edge copies the internal shift register to outputs Q0..Q7

Q7′ (pin 9): Serial data out; chain this to the next chip’s DS

OE (pin 13): Output enable, active low (LOW = outputs active). Tie to GND, or to a PWM pin for dimming

MR (pin 10): Master reset, active low. Keep HIGH for normal use. Pulse LOW to clear all bits

Data is clocked into the first chip; bits ripple toward the last chip. On latch, all outputs update together—zero flicker if you write quickly.

Wiring (Two Chips → 16 LEDs)
Common Power/Control

VCC (pin 16) → 5 V

GND (pin 8) → GND

0.1 µF between VCC and GND on each chip (close to the IC)

Control Lines (Arduino → both chips)

SH_CP (pin 11) → Arduino D12 (clock)

ST_CP (pin 12) → Arduino D8 (latch)

OE (pin 13) → GND (or a PWM pin like D3 for global brightness)

MR (pin 10) → 5 V (or a digital pin if you want software reset)

Serial Data & Daisy-Chain

Chip 1 DS (pin 14) → Arduino D11 (data)

Chip 1 Q7′ (pin 9) → Chip 2 DS (pin 14)

If you add a third chip: Chip 2 Q7′ → Chip 3 DS, and so on

LEDs

For each chip:

Q0..Q7 (pins 15, 1, 2, 3, 4, 5, 6, 7) → 220 Ω resistor → LED → GND
(You can reverse LED polarity if you prefer sourcing vs sinking current; the code is the same—just invert logic if needed.)

Channel Numbering (Simple Mental Model)

The chip closest to Arduino is register 0: it controls channels 0..7

The next chip is register 1: channels 8..15

With N chips, channels go 0..(8N−1)
The code below lets you call regWrite(channel, state) without caring which register or bit that is.

Power & Current: What You Can Safely Drive

Typical LED current with 220 Ω at 5 V is ~5–10 mA depending on LED color (VF).
Example (red LED): (5 V − 2.0 V) / 220 Ω ≈ 13.6 mA (often too bright; many LEDs are fine at 5 mA)

The 74HC595 can’t source/sink large current on all pins simultaneously. Keep per-pin current ≤ 8 mA and total per chip ≤ ~50 mA (check your datasheet).

If you need to drive lots of LEDs at once at higher current, use transistor arrays (e.g., ULN2803) or MOSFETs, or multiplex with 74HC595 + 74HC138 etc.

For many simultaneously-on LEDs, use a separate 5 V supply for the LED side and common GND with Arduino.

Avoid “Random LEDs on at Power-Up”

At startup, the internal register has undefined contents.

Software fix: Immediately write zeros and latch in setup()

Hardware fix: Tie MR to an Arduino pin; briefly drive LOW→HIGH after boot

No-glare boot: Hold OE HIGH (outputs off), preload zeros, then set OE LOW

Why PWM on OE Beats a Series Pot

Putting a pot in series with all LEDs changes current and can cause color mismatch and uneven brightness. Driving OE from a PWM pin keeps per-LED resistors fixed and dims everything uniformly via duty cycle. (Remember: OE is active LOW. More PWM duty = darker unless you invert it in code.)

Step-by-Step Assembly

Place the two SN74HC595N on the breadboard with power rails connected; add 0.1 µF caps per chip.

Wire Arduino D11→DS(14), D12→SH_CP(11), D8→ST_CP(12). Tie OE(13)→GND and MR(10)→5 V (or to Arduino pins as described).

Connect Chip 1 Q7′(9)→Chip 2 DS(14).

Add resistors from each Q pin to its LED, and LEDs back to GND.

Double-check power and grounds; verify no shorts.

Upload the sketch and test.

The Code (drop-in, scalable)

Change NUM_REGS to match how many 74HC595s you chained.

Use regWrite(channel, state) to set any LED.

flush() pushes the entire state array out.

Optional OE_PIN for global brightness via analogWrite.

// ===== User Configuration =====
const int DATA_PIN = 11; // DS -> 74HC595 pin 14
const int CLOCK_PIN = 12; // SH_CP-> 74HC595 pin 11
const int LATCH_PIN = 8; // ST_CP-> 74HC595 pin 12

const int MR_PIN = -1; // Tie to 5V or assign a pin (active LOW). -1 = tied HIGH.
const int OE_PIN = -1; // Tie to GND or assign a PWM pin (active LOW). -1 = tied LOW.

const int NUM_REGS = 2; // 2 chips = 16 channels; set to your chain length
// ==============================

byte regs[NUM_REGS]; // Each byte is Q0..Q7; bit 0 -> Q0, bit 7 -> Q7

inline void latch() {
digitalWrite(LATCH_PIN, LOW);
digitalWrite(LATCH_PIN, HIGH);
}

// Push regs[] to the chain (send farthest chip first)
void flush() {
digitalWrite(LATCH_PIN, LOW);
for (int i = NUM_REGS - 1; i >= 0; --i) {
shiftOut(DATA_PIN, CLOCK_PIN, MSBFIRST, regs[i]);
}
digitalWrite(LATCH_PIN, HIGH);
}

void clearAll() {
for (int i = 0; i < NUM_REGS; ++i) regs[i] = 0;
flush();
}

// Set one channel (0..NUM_REGS*8-1), then flush
void regWrite(int channel, bool state) {
if (channel < 0 || channel >= NUM_REGS * 8) return;
int r = channel / 8; // which register
int b = channel % 8; // which bit (0=Q0 .. 7=Q7)
bitWrite(regs[r], b, state);
flush();
}

// Optionally set all 8-bit registers at once then flush (length must be NUM_REGS)
void writeAll(const byte* values) {
for (int i = 0; i < NUM_REGS; ++i) regs[i] = values[i];
flush();
}

void setup() {
pinMode(DATA_PIN, OUTPUT);
pinMode(CLOCK_PIN, OUTPUT);
pinMode(LATCH_PIN, OUTPUT);

if (MR_PIN >= 0) {
pinMode(MR_PIN, OUTPUT);
digitalWrite(MR_PIN, HIGH); // keep not-reset (LOW would clear)
}
if (OE_PIN >= 0) {
pinMode(OE_PIN, OUTPUT);
digitalWrite(OE_PIN, LOW); // enable outputs (LOW = on)
}

// Clean startup
clearAll();

// If you wired MR to a pin and want to hard-reset at boot:
// if (MR_PIN >= 0) { digitalWrite(MR_PIN, LOW); delay(1); digitalWrite(MR_PIN, HIGH); }

// If you wired OE to a pin and want outputs disabled during init:
// if (OE_PIN >= 0) { digitalWrite(OE_PIN, HIGH); /* preload zeros */ clearAll(); digitalWrite(OE_PIN, LOW); }
}

void loop() {
const int N = NUM_REGS * 8;

// 1) Light up one-by-one
for (int i = 0; i < N; ++i) { regWrite(i, true); delay(60); }
delay(200);
for (int i = N - 1; i >= 0; --i) { regWrite(i, false); delay(40); }
delay(200);

// 2) Single "runner" back and forth
clearAll();
for (int pass = 0; pass < 2; ++pass) {
for (int i = 0; i < N; ++i) { clearAll(); regWrite(i, true); delay(40); }
for (int i = N - 1; i >= 0; --i) { clearAll(); regWrite(i, true); delay(40); }
}

// 3) Even/odd blink pattern
byte evenMask = 0b01010101; // Q0,2,4,6
byte oddMask = 0b10101010; // Q1,3,5,7
for (int k = 0; k < 6; ++k) {
for (int r = 0; r < NUM_REGS; ++r) regs[r] = (k % 2 == 0) ? evenMask : oddMask;
flush();
delay(180);
}

// 4) Global brightness sweep via OE (if connected to PWM pin)
// NOTE: OE is active LOW. We invert the duty with (255 - d).
/*
if (OE_PIN >= 0) {
for (int r = 0; r < NUM_REGS; ++r) regs[r] = 0xFF; // all on
flush();
for (int d = 0; d <= 255; d += 5) { analogWrite(OE_PIN, 255 - d); delay(8); }
for (int d = 255; d >= 0; d -= 5) { analogWrite(OE_PIN, 255 - d); delay(8); }
}
*/
}

Scaling to More LEDs

Hardware: Chain Q7′ of the last chip to DS of the new chip; share clock, latch, OE, MR, VCC, GND.

Software: Set NUM_REGS to your new count. Your channel numbers keep increasing linearly (e.g., with 3 chips, channels 0–23).

Troubleshooting

Some LEDs randomly on at power-up
Initialize with clearAll() in setup(); optionally wire MR and/or OE to Arduino pins as explained.

Nothing lights
Check VCC/GND, verify latch wiring (ST_CP). Make sure you call flush() or use regWrite() which calls it for you.

Only first 8 work
Q7′(pin 9) of chip 1 must go to DS(pin 14) of chip 2. Also confirm you’re shifting MSBFIRST and sending the last register first in the loop.

Flicker or unreliable updates with many chips
Lower clock rate (use shiftOut as is, or add small delays), keep wires short, add decoupling capacitors, ensure solid ground. Consider buffering if chain gets long.

Uneven brightness
Use individual current-limiting resistors per LED and dim via OE PWM, not a shared series potentiometer.

Frequently Asked (Useful) Variations

Can I multiplex instead to reduce current and chips?
Yes. For matrixes (e.g., 8×8), pair 74HC595 with a row/column driver (like ULN2803, TPIC6B595, or a 74HC138) and scan rows. Code is different but very scalable.

What about SPI for speed?
You can wire DS→MOSI, SH_CP→SCK, and manually toggle ST_CP as latch. Then use SPI.transfer() for much faster updates than shiftOut().

Can I use 3.3 V boards?
74HC595 typically works at 3.3–5 V. Check your particular HC family and ensure LED current and logic thresholds are respected.

Summary

Two 74HC595s = 16 LED channels using just 3 Arduino pins

Global brightness via OE on a PWM pin is cleaner than a series potentiometer

Add more chips: wire Q7′→DS, change NUM_REGS, done

The provided code presents a universal channel interface and example effects you can extend

If you want, I can also provide a version wrapped as a small C++ class (with non-blocking timers for smooth patterns) or an SPI-accelerated variant for longer chains.

STM32 Internal Temperature Sensor Reading (With DMA + Timer Trigger) — Complete Guide & Example Code

ai pics — Thu, 25 Sep 2025 02:48:23 +0000

STM32 microcontrollers include an internal temperature sensor connected to a dedicated ADC channel. The sensor is intended primarily for monitoring the temperature of the silicon die rather than measuring ambient temperature. It is therefore best suited to thermal trend detection, system health monitoring, thermal throttling, and failsafe logic.

With an adequate ADC sampling time, compensation for supply-voltage changes, deterministic triggering, and basic calibration, the internal sensor can still provide stable and repeatable readings for many embedded applications.

This tutorial shows how to:

Enable the internal temperature sensor and VREFINT channels
Trigger ADC conversions at 50 Hz using TIM3 TRGO
Transfer two ADC channels through DMA in circular mode
Compensate for VDD variation using VREFINT
Convert the measured sensor voltage into degrees Celsius
Calibrate and stabilize the result for a real product

Important: Always check the datasheet and reference manual for your exact STM32 part number. Temperature-sensor constants, factory calibration data, channel names, ADC resolution, trigger routing, and initialization details vary between STM32 families and sometimes between device revisions.

What the Internal Temperature Sensor Measures
Measurement Flow and Conversion Equation
Project Architecture: A 50 Hz Sampling Pipeline
STM32CubeMX Configuration
HAL Example Code
Calibration and Accuracy Tips
PCB Implementation Considerations
Troubleshooting FAQ
Wrap-Up

1. What the Internal Temperature Sensor Measures

The STM32 temperature sensor produces a voltage, normally identified as VSENSE, that changes with die temperature. This voltage is routed internally to an ADC channel; no external sensor pin is required.

A second internal ADC channel, VREFINT, exposes the MCU's internal bandgap reference. By measuring VREFINT, the firmware can estimate the actual analog supply voltage and compensate the VSENSE calculation for VDD variation.

This distinction matters because the ADC result is a ratio between the input voltage and the ADC reference. If the firmware assumes a fixed 3.3 V supply while the real VDD changes, the calculated temperature will drift even if the die temperature remains constant.

The internal sensor is useful for:

Detecting rising or falling die temperature
Initiating thermal throttling or a controlled shutdown
Recording thermal behavior during system tests
Comparing operating modes or firmware workloads
Detecting abnormal self-heating

It is not the right choice when the application requires precise room, enclosure, battery, surface, or remote-object temperature measurement. Those tasks normally require a properly positioned external sensor.

2. Measurement Flow and Conversion Equation

The basic measurement sequence is:

Enable the internal temperature-sensor and VREFINT paths.
Configure a sampling time that meets the datasheet minimum.
Trigger a two-channel ADC sequence at a fixed rate.
Read VREFINT and VSENSE.
Estimate the actual VDD from VREFINT.
Convert the raw temperature-sensor code into VSENSE.
Convert VSENSE into temperature using the correct device constants.

For STM32 devices that use the typical V25 and average-slope method, the equation has this form:

Temperature (°C) = ((V25 − VSENSE) / Avg_Slope) + 25

Where:

V25 is the sensor output voltage at 25 °C, approximately 1.43 V for many STM32F1 parts.
Avg_Slope is the average sensor slope, approximately 4.3 mV/°C for many STM32F1 parts.
VSENSE is calculated from the raw ADC code after VDD compensation.

A 12-bit ADC has 4,096 quantization levels. At a 3.3 V reference, one ideal LSB is approximately 0.806 mV. The ADC/DAC resolution calculator is useful for checking LSB size, quantization limits, and the effect of reference voltage before comparing expected code changes with measured data.

If the MCU provides factory-programmed temperature calibration values such as TS_CAL1 and TS_CAL2, use them instead of generic V25 and Avg_Slope values. Two-point factory calibration usually provides a better starting point because it accounts for device-to-device variation.

3. Project Architecture: A 50 Hz Sampling Pipeline

The example uses a simple deterministic pipeline:

TIM3 generates a TRGO update event every 20 ms, producing a 50 Hz trigger rate.
ADC1 uses the timer event as the external trigger for its regular conversion group.
Each trigger starts a two-channel sequence: VREFINT first, then TempSensor.
DMA transfers both results into a two-element buffer in circular mode.
The conversion-complete callback toggles a GPIO and marks the new sample as ready.
The main loop estimates VDD, calculates VSENSE, converts it to temperature, and sends the result through UART.

The example target is the STM32F103C8T6, a 72 MHz Arm Cortex-M3 MCU with 12-bit ADCs, timers, DMA, and common serial interfaces. The same architecture applies to many other STM32 devices, but the internal channel definitions, calibration addresses, and HAL configuration can differ.

Using a timer rather than repeated software starts gives the ADC a consistent sampling interval. DMA keeps the two channel readings together and reduces timing variation caused by firmware execution.

4. STM32CubeMX Configuration

MCU or Board

The following settings are based on an STM32F103C8 device, such as a Blue Pill development board. Adapt the clock tree, ADC channels, and trigger source to the exact MCU used in your project.

RCC and Clock Tree

Use HSE with the PLL to obtain a 72 MHz system clock when appropriate for the board.
Keep the ADC clock within the datasheet limit. For an STM32F103 running PCLK2 at 72 MHz, a prescaler of 6 gives a 12 MHz ADC clock, below the 14 MHz maximum specified for this family.

ADC1

Enable scan conversion mode.
Set the regular sequence length to two conversions.
Configure Rank 1 as VREFINT and Rank 2 as TempSensor.
Disable continuous conversion; conversions will be started by the external timer trigger.
Select TIM3 TRGO as the external trigger.
Choose a sampling time that meets or exceeds the temperature sensor's minimum acquisition time.

For example, with a 12 MHz ADC clock, 239.5 sampling cycles correspond to approximately 19.96 µs, which is longer than the commonly specified 17 µs minimum for STM32F1 internal channels.

CubeMX normally generates the required internal-channel enable logic, but verify that the temperature-sensor/VREFINT path is enabled on your device. On STM32F1, this is controlled through the TSVREFE bit.

DMA

Add the ADC1 DMA channel.
Select circular mode.
Use halfword peripheral and memory alignment.
Enable memory increment.
Set the buffer length to two halfwords.

TIM3

Select the internal clock source.
Configure the prescaler and auto-reload values for a 20 ms update interval.
Set TRGO to Update Event.

At a 72 MHz timer clock, one valid example is:

Prescaler: 23
Auto-reload: 59,999

The timer update frequency is then:

72 MHz / (23 + 1) / (59,999 + 1) = 50 Hz

USART1

Configure 115200 baud, 8 data bits, no parity, and 1 stop bit.

GPIO

Configure one output, such as PB0, as a timing probe.
Toggle it in the ADC conversion-complete callback.

5. HAL Example Code

This example uses V25 = 1.43 V, Avg_Slope = 4.3 mV/°C, and a typical VREFINT value of 1.20 V. These values are commonly associated with STM32F1 devices but must be checked against the datasheet for the exact part.

/*
 * Demo: STM32 internal temperature sensor
 * ADC + DMA + TIM3 TRGO at 50 Hz
 * Target style: STM32F103; adjust constants and configuration for your MCU
 */

#include "main.h"
#include <stdio.h>

/* Datasheet parameters: verify for the exact MCU */
#define AVG_SLOPE_mV_per_C   (4.3f)
#define V_AT_25C_V           (1.43f)
#define VREFINT_TYP_V        (1.20f)

ADC_HandleTypeDef   hadc1;
DMA_HandleTypeDef   hdma_adc1;
TIM_HandleTypeDef   htim3;
UART_HandleTypeDef  huart1;

/* Rank 1 = VREFINT, Rank 2 = VSENSE */
static volatile uint16_t adc_buf[2];
static volatile uint8_t new_sample = 0;

static float vdd_V = 0.0f;
static float vsense_V = 0.0f;
static float temperature_C = 0.0f;

static char line[48];

void SystemClock_Config(void);
static void MX_GPIO_Init(void);
static void MX_DMA_Init(void);
static void MX_ADC1_Init(void);
static void MX_TIM3_Init(void);
static void MX_USART1_UART_Init(void);

int main(void)
{
  HAL_Init();
  SystemClock_Config();
  MX_GPIO_Init();
  MX_DMA_Init();
  MX_ADC1_Init();
  MX_TIM3_Init();
  MX_USART1_UART_Init();

  /* Calibrate the ADC before starting conversions. */
  HAL_ADCEx_Calibration_Start(&hadc1);

  /* Arm ADC + DMA first, then start the timer trigger. */
  HAL_ADC_Start_DMA(&hadc1, (uint32_t *)adc_buf, 2);
  HAL_TIM_Base_Start(&htim3);

  for (;;)
  {
    if (new_sample)
    {
      uint16_t vrefint_raw;
      uint16_t vsense_raw;

      /* Clear the flag, then take a local snapshot of the DMA buffer. */
      new_sample = 0;
      vrefint_raw = adc_buf[0];
      vsense_raw = adc_buf[1];

      if (vrefint_raw == 0U)
      {
        continue;
      }

      const float adc_fullscale = 4095.0f;

      /* Estimate VDD from the typical internal reference value. */
      vdd_V = (VREFINT_TYP_V * adc_fullscale) / (float)vrefint_raw;

      /* Convert the temperature-sensor ADC code into volts. */
      vsense_V = ((float)vsense_raw * vdd_V) / adc_fullscale;

      /* Convert VSENSE into degrees Celsius. */
      temperature_C =
          (((V_AT_25C_V - vsense_V) * 1000.0f) /
           AVG_SLOPE_mV_per_C) + 25.0f;

      int n = snprintf(line, sizeof(line), "%.2f\r\n", temperature_C);
      HAL_UART_Transmit(&huart1, (uint8_t *)line, (uint16_t)n, 50);
    }
  }
}

void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef *hadc)
{
  if (hadc->Instance == ADC1)
  {
    HAL_GPIO_TogglePin(GPIOB, GPIO_PIN_0);
    new_sample = 1;
  }
}

If the device provides a factory VREFINT calibration code measured at a known voltage, calculate VDD with the calibration value instead of the typical 1.20 V assumption:

VDD = (VREF_CAL_VOLTAGE × VREFINT_CAL_CODE) / ADC[VREFINT]

If TS_CAL1 and TS_CAL2 are available, scale the current ADC result to the calibration voltage and interpolate between the two temperature points. Follow the formula given in the reference manual or datasheet for that STM32 family.

6. Calibration and Accuracy Tips

Use the Correct Sampling Time

The internal temperature-sensor path has a relatively high source impedance and needs enough acquisition time to charge the ADC sample-and-hold capacitor. A sampling time below the datasheet minimum can create unstable or biased readings.

Compensate for VDD Variation

Read VREFINT in the same sequence as VSENSE. Using a fixed assumed supply voltage can turn ordinary regulator tolerance, USB voltage changes, or load transients into apparent temperature changes.

Prefer Factory Calibration

Factory-programmed VREFINT_CAL, TS_CAL1, and TS_CAL2 values are usually better than family-level typical constants because they account for some device-to-device variation.

Average Sensibly

Thermal behavior changes slowly. An 8- or 16-sample moving average is often enough to reduce visible jitter. Sampling at 10–50 Hz is normally adequate for thermal monitoring; very high sampling rates add processing and data without providing useful thermal bandwidth.

Calibrate in the Final Hardware

If absolute accuracy matters, compare the reading with a known-good external sensor placed close to the MCU package. Allow the system to reach thermal equilibrium, collect measurements at several operating points, and fit an offset or two-point correction.

Remember What Is Being Measured

The reading is die temperature. CPU activity, clock frequency, flash accesses, regulator losses, nearby power devices, copper area, airflow, and enclosure conditions all affect it. The value should not be expected to match room temperature.

7. PCB Implementation Considerations

Firmware compensation cannot correct every hardware problem. On a custom board, keep analog supply and reference decoupling close to the MCU, follow the manufacturer's grounding guidance, and prevent fast digital or switching-current return paths from disturbing the ADC reference network.

Board layout also changes the thermal result. A large copper area under and around the MCU can spread heat, while a nearby regulator, MOSFET, or high-current trace can warm the package. Test points for VDD, VDDA, the timing-probe GPIO, and relevant power rails make bring-up much easier.

When moving from a development board to a custom design, a small prototype PCB build gives you an opportunity to validate ADC noise, decoupling, trigger timing, thermal coupling, and sensor calibration before committing to production quantities.

8. Troubleshooting FAQ

Why is the temperature reading noisy or unstable?

Increase the ADC sampling time.
Average several readings.
Confirm that TIM3 TRGO is actually selected as the ADC trigger.
Check VDDA decoupling and the analog supply layout.
Verify that the DMA buffer order matches the configured ADC ranks.

Why does the reading drift when VDD changes?

The calculation is probably using a fixed reference voltage. Measure VREFINT during every sequence and use it to estimate the actual VDD.

Why do I get an obviously wrong result, such as −20 °C at room temperature?

Check whether VREFINT and TempSensor are reversed in the DMA buffer.
Verify that V25, Avg_Slope, and any calibration addresses match the exact MCU.
Confirm the ADC clock, resolution, and channel sampling time.
Make sure the internal sensor/VREFINT path is enabled.
Check whether the formula's slope direction matches the device documentation.

How do I verify the 50 Hz sampling rate?

Toggle a GPIO in HAL_ADC_ConvCpltCallback() and inspect it with an oscilloscope or logic analyzer. The pin changes state once per completed two-channel sequence, so transitions should occur every 20 ms. Because the pin alternates high and low, the complete square-wave period is 40 ms, corresponding to a displayed waveform frequency of 25 Hz.

Can I read the sensor without DMA?

Yes. Polling or interrupt-driven conversions can work, especially for a slow diagnostic measurement. DMA is useful because it keeps both channel results together, reduces CPU involvement, and supports a predictable timer-driven pipeline.

Why does `snprintf()` not print the floating-point value?

Some embedded C library configurations disable floating-point formatting to save flash. Enable float support in the linker settings or transmit a scaled integer value instead.

Should UART transmit at every 50 Hz sample?

It is acceptable for a short lab test at 115200 baud, but production firmware should avoid blocking communication in a time-sensitive loop. Consider decimating the log rate, buffering messages, or using DMA for UART transmission.

9. Wrap-Up

With timer-triggered ADC conversions, circular DMA, and VREFINT compensation, the STM32 internal temperature sensor becomes a practical monitor for thermal trends, system health, throttling, and safety logic.

For the most reliable result:

Use the datasheet sampling-time requirement.
Trigger measurements at a consistent rate.
Measure VREFINT alongside VSENSE.
Prefer factory calibration data where available.
Validate the result on the final PCB under realistic loads and airflow.

The internal sensor will not replace a precision ambient probe, but it can provide valuable information about what is happening inside the MCU and help firmware respond before thermal stress becomes a system failure.

How to Optimize HLS Designs for FPGAs (A Practical, Vendor-Agnostic Playbook)

ai pics — Mon, 22 Sep 2025 08:39:19 +0000

Optimizing High-Level Synthesis (HLS) for FPGAs is about turning C/C++ into RTL that meets your throughput, latency, area, and power targets—without breaking correctness. Below is a concise, field-tested checklist you can apply in Vitis HLS (Xilinx), Intel HLS, Catapult, etc. Examples use Vitis HLS-style pragmas, with notes for portability.

1) Know the Optimization Stack

Algorithm level – choose math/data representations that minimize work.

Loop & task level – expose parallelism (pipeline, unroll, dataflow).

Memory & I/O – feed the beast (partition, reshape, burst, stream).

Micro-architecture – bind operators/memories, balance latencies, share resources.

Closure – verify (C/COSIM), analyze (util/timing/II/latency), iterate.

2) Numerics & Code Structure
Use bit-accurate fixed types

Prefer ap_(u)int / ap_fixed (or vendor equivalents) over float/double when error budget allows.

Right-size widths aggressively to cut LUTs, FFs, and DSP usage.

include "ap_int.h"

include "ap_fixed.h"

using pix_t = ap_uint<10>; // example: 10-bit pixel
using coeff_t = ap_fixed<16,2>; // 2 integer bits, 14 fractional

Make dependencies obvious (or remove them)

Keep hot loops simple; hoist conditionals outside loops when possible.

Replace complex if/else trees on the critical path with tables or precomputed constants where sensible.

Use const, restrict (where safe), and pass-by-reference to help the compiler infer no-aliasing and enable bursting.

3) Loop-Level Optimization
Pipeline first

Goal: II=1 on the critical loop whenever feasible.

pragma HLS PIPELINE II=1

for (int i = 0; i < N; i++) {
// body with no loop-carried true deps
}

Tip: If HLS won’t reach II=1, check the synthesis log’s “stall” reason:

Memory port conflicts → partition/reshape arrays or widen the data path.

Loop-carried dependency (RAW/WAR/WAW) → restructure buffers or prove independence:

pragma HLS DEPENDENCE variable=buf inter false

Unroll to trade area for throughput

Partial unroll to match available memory banks/ports; full unroll only if you can feed it.

pragma HLS UNROLL factor=4

for (int k=0; k<K; k++) { ... }

Tile / block for locality

Break large loops into tiles that fit BRAM/URAM; combine with on-chip buffers to reduce DDR traffic.

for (int ii=0; ii<N; ii+=Ti)
for (int jj=0; jj<M; jj+=Tj)
compute_tile(ii, jj);

Help the estimator

Tripcounts improve latency reports and scheduling:

pragma HLS LOOP_TRIPCOUNT min=64 max=128

4) Task-Level Concurrency (DATAFLOW)

Use dataflow to run producer/consumer stages concurrently. Connect stages with hls::stream (or Intel channels).

include "hls_stream.h"

void stageA(hls::stream& out);
void stageB(hls::stream& in, hls::stream& out);
void stageC(hls::stream& in);

void top(hls::stream& in, hls::stream& out) {

pragma HLS DATAFLOW

static hls::stream s1("s1"), s2("s2");

pragma HLS STREAM variable=s1 depth=64

pragma HLS STREAM variable=s2 depth=64

stageA(s1);
stageB(s1, s2);
stageC(s2);
}

Tips

Choose FIFO depths to absorb burstiness and meet initiation intervals across stages.

Avoid reading/writing the same array from multiple tasks unless you bank/partition correctly.

5) Memory & Interface Tuning
Partition / reshape arrays to add ports

PARTITION creates true parallel banks (good for random access).

RESHAPE packs multiple elements per word (great for sequential access and burst width).

// Random parallel reads

pragma HLS ARRAY_PARTITION variable=buf cyclic factor=4 dim=1

// Wide sequential loads/stores (e.g., 512-bit DDR beats)

pragma HLS ARRAY_RESHAPE variable=line factor=16 dim=1

Burst DDR and align widths

Use m_axi (Vitis) and wide types (ap_uint<256/512>) to match DDR or NoC widths; ensure contiguous access patterns.

Add offset=slave & proper bundle= names for multiple ports.

void kernel(ap_uint<512>* in, ap_uint<512>* out, int N) {
#pragma HLS INTERFACE m_axi port=in offset=slave bundle=gmem0 depth=1024
#pragma HLS INTERFACE m_axi port=out offset=slave bundle=gmem1 depth=1024
#pragma HLS INTERFACE s_axilite port=N bundle=control
#pragma HLS INTERFACE s_axilite port=return bundle=control
// ...
}

Stream for high throughput and low latency

Use AXI4-Stream at the top and hls::stream internally for line-rate pipelines (video, radio, ML).

pragma HLS INTERFACE axis port=in_axis

pragma HLS INTERFACE axis port=out_axis

6) Resource Binding & Micro-Architecture
Bind operations and memories

Map multiplies to DSPs (throughput) or LUTs (save DSPs).

Choose BRAM vs URAM for large buffers; single-/dual-port appropriately.

pragma HLS RESOURCE variable=mul_op core=DSP48

pragma HLS BIND_STORAGE variable=tile type=ram_2p impl=bram

Control sharing vs. replication

Use UNROLL to replicate compute, or ALLOCATION/RESOURCE pragmas to limit operator instances for area.

pragma HLS ALLOCATION operation instances=mul limit=2

Latency balancing

For long adder trees or MAC chains, HLS will usually insert registers; you can constrain:

pragma HLS LATENCY min=1 max=6

7) Throughput vs. Latency vs. Fmax

II (Initiation Interval) controls throughput (samples/cycle).

Latency is total cycles from input to output.

Fmax comes from post-synthesis timing; shorten critical paths (reduce fan-out, balance trees, use DSPs).

Clocking note: Set the target period in tool constraints (e.g., Vitis HLS create_clock -period 5) rather than in code; adjust until timing is clean with margin.

8) Verification & Reporting

C-sim: Prove algorithm correctness fast.

C/RTL Co-sim: Validate that RTL matches C under realistic I/O.

Reports: Inspect

Achieved II and latency,

Stall reasons (dependencies/ports),

Resource map (LUT/FF/DSP/BRAM/URAM),

Interface burst efficiency.

Bit-exact testing for fixed-point: measure SNR/PSNR or error budgets vs. floating-point golden.

9) Example: Streaming FIR with One-Sample-per-Cycle

This version sustains II=1 by unrolling the tap MAC and fully partitioning coefficients and the shift register. It uses fixed-point, AXI-Stream I/O, and works nicely inside a DATAFLOW pipeline.

include "ap_fixed.h"

include "hls_stream.h"

using data_t = ap_fixed<16,8>;
using acc_t = ap_fixed<32,12>; // wider accumulator
const int N = 64;

struct axis_t {
data_t data;
bool last;
};

void fir64(hls::stream& in, hls::stream& out, const data_t coeff[N]) {

pragma HLS INTERFACE axis port=in

pragma HLS INTERFACE axis port=out

pragma HLS INTERFACE ap_ctrl_none port=return

pragma HLS ARRAY_PARTITION variable=coeff complete dim=1

static data_t shift_reg[N];

pragma HLS ARRAY_PARTITION variable=shift_reg complete dim=1

while (true) {

pragma HLS PIPELINE II=1

axis_t x = in.read();

// shift
for (int i = N-1; i > 0; --i) {

pragma HLS UNROLL

  shift_reg[i] = shift_reg[i-1];
}
shift_reg[0] = x.data;

// MAC
acc_t acc = 0;
for (int i = 0; i < N; ++i) {

pragma HLS UNROLL

  acc += (acc_t)shift_reg[i] * (acc_t)coeff[i];
}

axis_t y;
y.data = (data_t)acc;
y.last = x.last;
out.write(y);

if (x.last) break;  // simple frame terminator

}
}

DEV Community: ai pics

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STM32 Internal Temperature Sensor Reading (With DMA + Timer Trigger) — Complete Guide & Example Code

Table of Contents

1. What the Internal Temperature Sensor Measures

2. Measurement Flow and Conversion Equation

3. Project Architecture: A 50 Hz Sampling Pipeline

4. STM32CubeMX Configuration

MCU or Board

RCC and Clock Tree

ADC1

DMA

TIM3

USART1

GPIO

5. HAL Example Code

6. Calibration and Accuracy Tips

Use the Correct Sampling Time

Compensate for VDD Variation

Prefer Factory Calibration

Average Sensibly

Calibrate in the Final Hardware

Remember What Is Being Measured

7. PCB Implementation Considerations

8. Troubleshooting FAQ

Why is the temperature reading noisy or unstable?

Why does the reading drift when VDD changes?

Why do I get an obviously wrong result, such as −20 °C at room temperature?

How do I verify the 50 Hz sampling rate?

Can I read the sensor without DMA?

Why does snprintf() not print the floating-point value?

Should UART transmit at every 50 Hz sample?

9. Wrap-Up

How to Optimize HLS Designs for FPGAs (A Practical, Vendor-Agnostic Playbook)

include "ap_int.h"

include "ap_fixed.h"

pragma HLS PIPELINE II=1

pragma HLS DEPENDENCE variable=buf inter false

pragma HLS UNROLL factor=4

pragma HLS LOOP_TRIPCOUNT min=64 max=128

include "hls_stream.h"

pragma HLS DATAFLOW

pragma HLS STREAM variable=s1 depth=64

pragma HLS STREAM variable=s2 depth=64

pragma HLS ARRAY_PARTITION variable=buf cyclic factor=4 dim=1

pragma HLS ARRAY_RESHAPE variable=line factor=16 dim=1

pragma HLS INTERFACE axis port=in_axis

pragma HLS INTERFACE axis port=out_axis

pragma HLS RESOURCE variable=mul_op core=DSP48

pragma HLS BIND_STORAGE variable=tile type=ram_2p impl=bram

pragma HLS ALLOCATION operation instances=mul limit=2

pragma HLS LATENCY min=1 max=6

include "ap_fixed.h"

include "hls_stream.h"

pragma HLS INTERFACE axis port=in

pragma HLS INTERFACE axis port=out

pragma HLS INTERFACE ap_ctrl_none port=return

pragma HLS ARRAY_PARTITION variable=coeff complete dim=1

pragma HLS ARRAY_PARTITION variable=shift_reg complete dim=1

pragma HLS PIPELINE II=1

pragma HLS UNROLL

pragma HLS UNROLL

Why does `snprintf()` not print the floating-point value?