DEV Community: Debarshi(Deb).S

Gradius VibrantShader

Debarshi(Deb).S — Mon, 07 Sep 2026 23:03:56 +0000

Gradius VibrantShader Intel Hardware Benchmark — Performance Testing

https://modrinth.com/shader/gradius-vibrantshader

Shader Hardware Benchmark of my gradius vibrantshader

Performance tests for Gradius VibrantShader across different generations of Intel integrated graphics.

Resolution: 1920×1080

Minecraft: 26.2

Mod loader: Fabric

Renderer: Sodium + Iris

Minecraft settings: Default — no in-game settings were changed

Memory allocation: Default 4 GB

Optimization mods: Used alongside Sodium/Iris

CPU	Integrated GPU	Resolution	FPS
Intel Core i3 11th Gen G4	Intel UHD Graphics	1920×1080	48–55 FPS
Intel Core i5 12th Gen	Intel UHD 730	1920×1080	~36 FPS
Intel Core i3 12th Gen	Intel UHD Graphics	1920×1080	30–40 FPS
Intel Core i5 4th Gen	Intel HD 4600	1280×720	23–34 FPS

Test Conditions

All tests were performed using Minecraft's default in-game settings with no manual graphics configuration changes.

Minecraft 26.2
Fabric
Sodium
Iris
Additional optimization mods
4 GB default memory allocation
No manual graphics-quality tuning
No resolution scaling
No shader-specific performance configuration changes

Note: The HD 4600 test was performed at 1280×720, while the other listed systems were tested at 1920×1080. These results should therefore not be considered a direct GPU performance comparison.

Introducing (Heterogeneous intelligent Architecture Accelerator) HiAA

Debarshi(Deb).S — Thu, 03 Sep 2026 04:53:25 +0000

The modern CPU/GPU design has reached a point of diminishing returns. We pack megabytes of L2/L3 cache hierarchies, branch predictors, and dynamic out-of-order execution windows into silicon, only for AI training loops—which are entirely deterministic and predictable—to waste clock cycles waiting on cache-line evictions and memory bus bottlenecks.

Well so I’m building an architecture that eliminates the hardware scheduling tax completely, shifting the optimization burden directly to a smart software runtime-compiler. Here is the overview design of my HiAA SoC (Heterogeneous intelligent Architecture Accelerator) Chip

The Asymmetric ARM Processor (Custom ARMv9-A / AArch64)

To manage heavy, on-the-fly compilation, real-time DMA orchestration, and background multitasking without risking system instability, the 8-Core ARMv9 is decoupled into two hardware:

2x Compiler Engines (CE): Deep, high-frequency, wide out-of-order execution blocks (modeled on the Arm Cortex-X series). These are dedicated exclusively to running the smart compiler’s scheduling graphs, processing token dependencies, and organizing asynchronous operations.
6x Efficient Performance Units (EPU): Small, highly efficient in-order pipelines (modeled on the Arm Cortex-A series). They act as system traffic cops, handling basic OS multitasking, interface drivers, and state-machine handshakes.

The Heterogeneous Compute Engine (HCE)

Instead of standard hardware-managed caches,Heterogeneous Compute Engine (HCE) features 8x Synergistic Compute Elements (SCE), each packed with 1GB of direct Synergistic Memory (SM)as local scratchpad storage.

Synergistic Compute Element (SCE): In traditional chips, an NPU or TPU is a rigid, fixed-function "black box." If you aren't running AI workloads, that silicon sits completely dead. The SCE fixes this by discarding automated hardware caches and treating memory as a software-programmable scratchpad.

Because the 1GB Synergistic Memory (SM) is hardwired directly into the core execution pipeline, the smart compiler can dynamically repurpose the SCE grid on the fly based on workload pressure:

🧠 As a TPU / NPU: The compiler switches the SCE into "Tensor Mode." The internal registers morph into a 2D Systolic Array, streaming multi-dimensional matrix weights directly out of the local 1GB pool with zero instruction-fetch overhead.

🎮 As a GPU Parallel Compute Core: The SCE can execute unrolled SIMD loops for geometric transformations and vertex shading, drawing raw data straight from its independent 1GB memory channel.

🌐 As a DPU (Data/Packet Processor): When heavy data ingestion hits the board, the SCE acts as a localized packet router, sorting network strings and optimizing multi-board data transfers without ever interrupting the main ARM processor.

By giving the SCE a fluid, multi-paradigm design, to ensure that 100% of the silicon is active and working, maximizing performance-per-watt and keeping manufacturing costs incredibly low.

The Dual Vector Units (VU0 & VU1):

To maximize parallel throughput, I integrated two standalone Vector Processing Units (VU0 and VU1) directly into the HCE fabric. They act exactly like the co-processors.

📐 VU0 (Co-Processor Mode / Low-Latency Math): VU0 is hardwired with a direct, ultra-low-latency pipeline straight to the ARM CPU cluster. When the Compiler Engines hit a sudden, complex mathematical dependency—like calculating dynamic learning rates, scheduling multi-threaded token pointers, or handling activation that can't be easily arrayed—the ARM core drops the variables directly into VU0’s registers. VU0 executes the vector math instantly and returns the result to the CPU without context-switching.
🏎️ VU1 (Streaming Geometry & Tensor Transform Mode): VU1 is completely isolated from the ARM CPU. It sits on a dedicated high-bandwidth loop directly connected to the 8x Synergistic Compute Elements (SCE). Its sole purpose is running endless, unrolled microcode loops to execute massive floating-point matrix transformations, coordinate translations, or tensor formatting (like rearranging data shapes between neural network layers) and dumping the finished blocks straight into the MIC bus fabric.

Dynamic-Width LPDDR5X Hybrid Interface:

To make manufacturing affordable, I skip total expensive HBM packaging and utilize off-the-shelf, soldered LPDDR5X components on a mature process node (TSMC 12nm/16nm). To maximize power efficiency, the custom Memory Interface Controller (MIC) features dynamic hardware multiplexing:

Overlapping Latency: The Compiler's Job

Because this architecture strips out automatic hardware caches, training an AI model larger than our 16GB board pool requires Asynchronous Layer-by-Layer Streaming.

The compiler pre-calculates the exact execution time of every layer down to the individual clock cycle. While the TPU vector pipelines are calculating the back-propagation pass for Layer 12, the MIC uses a background DMA channel to pre-fetch the parameters for Layer 13 into a secondary buffer. The memory latency is entirely masked behind active compute.

Scalability via Raw Hardware Cables

For large-scale clustering, the SoC completely bypass slow PCIe buses and software network layers. The chip's internal Network-on-Chip (NoC) extends directly through physical Ultra-Short-Reach (USR) PHY ports on the edge of the die.

By linking boards together with_ high-bandwidth cables_, data packets transition from the memory pool of Board A to the execution core of Board B natively at the hardware level. The compiler treats the clustered nodes as a single,** unified distributed data-flow engine.**

Heterogeneous AI Super Cluster(HASC)

Debarshi(Deb).S — Wed, 26 Aug 2026 13:00:27 +0000

It's been 1 years working this research project Heterogeneous AI Super Cluster(HASC). A experimental computing platform can perform Quantum Simulations around 32-35 Qubits with ~15TFLOPS compute Power.

Achieved computing on PCHL, OpenCL/vulkan based custom AI distributed computing framework with multipal CPU architecture with model training system under low memory with PCHL's streaming system & for Quantum Research & development.

Designing PCHL Dual-State Computing Pipeline architecture in simulation and traditional model training workloads to efficiently distribute workloads under low resources.

Designed Custom Memory Engine Architecture (MEA) to pause and preserve computing workload states in the background enabling efficient context switching between different workloads under constrained memory resources with highly compressed state math
can be achievable under 1GB compressed state.

Designing Custom neural network architecture system highly modified version of transformer architecture redesigning for HASC,
researching on replacing the core architectural training process into something new.(experimental)

With the help of low-level Programming language PCHL (Parallel computing hybrid language) including Cell build for computing and use as a universal lang on HASC.

Currently PCHL runs on x86, Cell B.E.

future support on E.E ARM.

Note- Proper research and documentation still unavailable due to slow research.

PS3 RSX

Debarshi(Deb).S — Wed, 12 Aug 2026 04:00:15 +0000

Officially my PS3 RSX research journey started 🙂

Started as a normal Cell programming lesson on PS3 turned into a 3D acceleration development for PS3 linux RSX

After 20 years I'm finally working on bringing proper RSX graphics acceleration into PS3 Linux.

DDR3 Memory Engine Architecture

Debarshi(Deb).S — Tue, 11 Aug 2026 15:33:13 +0000

Just discovered that 1GB DDR3 auxiliary pool on PS4 pro can be use on any workload.

Introducing: DDR3 Memory Engine Architecture

The Challenge:
The PS4 Pro isolates its primary 8GB high-bandwidth GDDR5 pool for graphics and system allocation. However, the secondary 1GB DDR3 BGA chip on a completely separate, undocumented bus handled via a custom PCIe Endpoint window on the Belize Southbridge co-processor. While the outbound posted write path bursts past 1 GB/s (and settles at a stable 156 MB/s), the non-posted read path hits an immutable, hardwired serialization bottleneck clamped directly at ~11 MB/s with an average 85ms round-trip latency penalty.

So, instead of accepting the read bottleneck, added custom 8-queue in my DDR3 driver directly into the Linux 6.8.12 kernel, explicitly mapping it to tap into all 8 AMD Jaguar CPU cores simultaneously.

To bypass the silicon-level read throttle and I designed a hybrid memory-tiering architecture inspired by the iconic PS3 Cell Broadband Engine's SPE Local Store layout:

LZ4 Compression Engine (zswap): Implemented an early-boot kernel caching layer to shrink memory blocks at a 4:1 ratio, effectively quadrupling the operational bandwidth over the restricted physical bus width.

Double-Buffered "DMA" Streaming Pipeline: Built an asynchronous thread allocation strategy where background threads pre-fetch contiguous 4MB memory chunks sequentially via the block layer's read-ahead tracking while the core CUs (compute units) crunch live tensor layers directly out of the shared L2 cache—completely hiding the hardware latency loop.

The Real Impact-
By treating this 1GB DDR3 pool as a cold fallback storage vault for background assets & static tensor layers, we can isolate and hand nearly 100% of the ultra-fast 8GB GDDR5 RAM pool directly to active compute tasks, transforming normal Gaming consumer hardware into optimized nodes for Edge AI model inference & distributed training.

Still need to add support of GFX8.0 on PS4 pro that's another part

PS4 Pro Belize DDR3

Debarshi(Deb).S — Tue, 04 Aug 2026 08:27:30 +0000

Finally I did it,

So, I recently workin on reverse-engineering the Sony PlayStation 4 Pro memory subsystem under PS4Linux kernel, specifically targeting the auxiliary 1GB DDR3 DRAM managed by the Belize Southbridge co-processor.

On Orbis OS, this isolated 1GB pool is exclusively for OS asset swapping and background app parking. When running Linux, this memory remains completely unutilized because it is entirely separated from the APU's unified high-speed GDDR5 main memory controller.

So, I build a custom Linux Kernel module to hook onto this unmapped hardware and mount it natively as a zero-latency system swap device.

Engineering Roadblocks

Strict Bus Protocol: My early testing using direct memory mapping triggers immediate Input/output error exceptions. The Belize memory bus controller aggressively drops or faults any read/write transaction that isn't cleanly aligned to a strict 32-bit boundary so standard loops immediately stall the system.

ACPI/Device Tree Isolation: The PS4 have no standard PC like BIOS/ACPI tables, the initialization payload maps out the early E820 hardware boundaries. The memory space spanning 0x80000000 - 0xDFFFFFFF was explicitly flagged as SMAP_TYPE_RESERVED.

Kernel Validation blocks: On Linux kernels like v6.x, the virtual block layer (blk-mq) natively rejects non-PCI block driver allocations via add_disk() if it cannot identify an explicit struct device parent tracking node hierarchy inside sysfs.

So, the best part my 💡Multi-Layered Engineering Solution

Added Payload Carving modified the primary jailbreak kexec() loader payload source (linux_boot.c) to cleanly cut the rigid "Reserved" hardware block and declare the first 1GB slice (0x80000000 with a size of 0x40000000) as safe system MEMORY.

The blk_mq Parent Injection Bypass abandoned standard virtual device structures. Leveraged deep kernel internal abstractions (blk_mq_alloc_disk) to manually inject a custom pseudo-root device tracking parent inline (disk->part0.bd_device.parent).

Strict Word-Pacing IO Loops implemented a dedicated transaction wrapper utilizing ioread32 and iowrite32 streaming chunks to satisfy the co-processor's hardware bus constraints perfectly.

So the Output-
The driver compiles perfectly on my custom 6.8.12 debug kernel source. On boot, the kernel cleanly registers the device node at /dev/ps4pro_ddr3 as a true block storage format structure HELL YEAH

Btw I'm also a Kernel Contributor for PS4linux developer community so yeah u know..

My next Architecture in simple word-
run linux on 1gb DDR3 and use hole GDDR5 pool as a game memory on PS4pro like a true PS4 but on Linux I will see about that later....

DebLink utility console

Debarshi(Deb).S — Sat, 18 Jul 2026 21:27:11 +0000

Finally ported my Payload Laucher app into android now it's called Deblink.

If u don't know it's a simple application to sent payload to your Homebrew devices and it's now finally ported to native android application.

in future I will add SSH controller FTP server and File sharing Integrate with Croc file sharing

Plugin MC

Debarshi(Deb).S — Thu, 16 Jul 2026 03:49:37 +0000

🚀 PluginMC is officially live.

🌐 https://pluginagentmc.com

Every Minecraft server owner has ideas that could make their server unique.
The problem is that many don't know where to start, struggle to find reliable developers, or end up wasting time and money on projects that never get delivered as promised.

That's why we created PluginMC.
We're a Minecraft plugin development agency that connects server owners with experienced developers to build custom systems tailored to their vision.

Whether it's a unique progression system, custom bosses, economy mechanics, enchantments, or completely original gameplay ideas, our goal is simple:

Help server owners turn creative ideas into production-ready Minecraft systems.
Our showcase projects
⚔️ Multi-Phase Boss System
🪙 Mob Token Economy
✨ Custom Enchantment System
🌍 Community Progression Framework (In Development)

What we build

Custom Paper, Spigot, Folia & Bukkit plugins
Progression & RPG systems
Economy mechanics
Boss systems & custom events
Performance-focused server solutions
Long-term development & support
Every great Minecraft server starts with a unique idea.
We're here to help turn that idea into reality.

🌐 https://pluginagentmc.com

We connect server owners with experienced developers and manage the project from idea to delivery.

Minecraft #Java #PaperMC #Spigot #PluginDevelopment #GameDevelopment #JavaDeveloper #Startup #agency #Services

Vulkan Computing with FP16 on PS4 GPU

Debarshi(Deb).S — Sat, 11 Jul 2026 19:06:49 +0000

Finally Vulkan computing possible on PS4 GPU

vulkan compute array running on PS4 GPU(Gradius):
Using physical device index 0 found AMD Radeon Graphics (RADV GLADIUS) Output: { 0 4 12 }

This successful confirms that GPU buffer allocation, compute shader execution, and result readback through the Vulkan compute pipeline.

My Next goals:
• Matrix multiplication benchmarking
• Tiny transformer inference experiments via vulkan
• Vulkan-based neural network research on Gradius

After a lot of kernel, Mesa, and driver work, finally it's possible.
and the best part PS4 Pro shader cores are now can execute FP16 floating-point compute shaders correctly through Vulkan Compute.

My own Heterogeneous AI Super Cluster

Debarshi(Deb).S — Fri, 03 Jul 2026 08:41:44 +0000

Helloo everyone, I'm Deb 14 years old from India West Bengal working on a research project around 1 years workin on that called Heterogeneous AI Super Cluster training big LLM models, it can perform Quantum Simulations around 32-35 Qubits with 10TFLOPS compute Power it power my own Private AI model specially trained for designing rocket engines space rovers designing AI chips CPUs. with my own OpenCL based custom AI distributed computing framework with multipal CPU architecture with custom ai training system under low memory and for Quantum Research & development.

And with my own low-level Programming language PCHL parallel computing hybrid language including Cell it's build for computing on my cluster
it's still in development stage so I will tell about it more stay tune

but one thing I really proud to say I did in last few years that One PS4 pro can perform parallel computations with OpenCL kernels.
It supports floating-point math (including double precision), which is useful in scientific computing and AI.
can run custom compute tasks, neural networks, or image processing on the GPU.
Frameworks that use OpenCL can access this GPU. I did that few years ago.