DEV Community: Dibyaprakash Pradhan

How Wide Does a PCB Trace Need to Be for 1 A, 2 A, 3 A or 5 A?

Dibyaprakash Pradhan — Tue, 20 Oct 2026 12:11:32 +0000

The usual answer is a table, and most tables are the same IPC-2221 formula at different settings. That's a fine starting point for an outer-layer trace on an ordinary board. It's too generous for some boards, far too cautious for internal layers, and it says nothing about voltage drop, which is often the limit that bites first.

Short answer: on 1 oz copper on an outer layer, allowing a 10 °C rise, about 0.30 mm (12 mil) for 1 A, 0.78 mm (31 mil) for 2 A, 1.37 mm (54 mil) for 3 A and 2.77 mm (109 mil) for 5 A. Allow 20 °C and they shrink by about a third; use 2 oz copper and they halve. Then check the voltage drop: at 1 A, 100 mm of that 0.30 mm trace drops 175 mV.

The table

Width for a continuous current, from the IPC-2221 formula (I = k·ΔT^0.44·A^0.725, k = 0.048 outer, 0.024 internal). The first three columns are outer layers, the last is an internal layer.

Current	1 oz outer, 10 °C	1 oz outer, 20 °C	2 oz outer, 10 °C	1 oz internal, 10 °C
0.5 A	0.12 mm (5 mil)	0.08 mm (3 mil)	0.06 mm (2 mil)	0.30 mm (12 mil)
1 A	0.30 mm (12 mil)	0.20 mm (8 mil)	0.15 mm (6 mil)	0.78 mm (31 mil)
2 A	0.78 mm (31 mil)	0.51 mm (20 mil)	0.39 mm (15 mil)	2.03 mm (80 mil)
3 A	1.37 mm (54 mil)	0.90 mm (35 mil)	0.68 mm (27 mil)	3.56 mm (140 mil)
5 A	2.77 mm (109 mil)	1.82 mm (71 mil)	1.38 mm (54 mil)	7.19 mm (283 mil)
10 A	7.19 mm (283 mil)	4.72 mm (186 mil)	3.60 mm (142 mil)	18.71 mm (737 mil)

A coupon board with one 40 mm outer-layer trace per current, each at the 1 oz, 10 °C width from the table, beside a 0.25 mm signal trace for scale. Built and rendered in KiCad 9; it passes KiCad's design-rule check.

Going from 1 A to 5 A takes the trace from barely wider than a signal trace to over 2.7 mm. At 10 A the 1 oz outer width passes 7 mm, which is the point to stop widening traces and use a copper pour, heavier copper, or both.

How to read it: rise, copper weight, layer

Temperature rise is how much hotter than its surroundings the trace may run. It's a choice, not a property of the board. 10 °C is the cautious default; 20 °C shrinks every width by about a third.

Copper weight is thickness: 1 oz is about 35 µm, 2 oz is twice that. Capacity follows cross-section, so 2 oz roughly halves the width. On budget fabs the outer layers are 1 oz unless you ask.

Layer is where IPC-2221 is most conservative. Its formula halves the constant for internal layers, which makes an internal trace about 2.6 times as wide as an outer one for the same current.

What IPC-2152 changed

IPC-2221's external chart comes from US National Bureau of Standards tests in the 1950s, and its internal chart was never tested: it was derived from the external one. IPC-2152, published in 2009, replaced both with new measurements, and two findings matter for everyday boards.

First, internal traces aren't the poor relations IPC-2221 makes them: in the new tests internal and external traces carrying the same current ran at close to the same temperature rise, internal ones slightly cooler, so the 2.6× internal penalty is mostly margin. Second, the trace is only part of the story. Board thickness and copper planes near the trace change the temperature rise as much as the width does, which is why IPC-2152 gives a baseline chart (3 oz copper, still air, no planes) plus modifiers for copper weight, planes, board thickness and environment.

In practice: the IPC-2221 table is a safe outer-layer answer for a board in open air. Over or beside a solid plane, a trace runs cooler than the table says. In a sealed box, it runs hotter.

Wide enough for heat is not wide enough for voltage

The width tables size a trace so it doesn't get too hot. They don't look at how much voltage it loses on the way. Here's 100 mm of each heat-sized trace from the first column, with the copper at 35 °C:

Current	Width	Resistance	Voltage drop	Heat in the trace
1 A	0.30 mm	175 mΩ	175 mV	175 mW
2 A	0.78 mm	67 mΩ	135 mV	269 mW
3 A	1.37 mm	38 mΩ	115 mV	345 mW
5 A	2.77 mm	19 mΩ	95 mV	473 mW

175 mV is about 5% of a 3.3 V rail, gone before the current reaches the load. For a supply that feeds a regulator that may not matter; for the rail a microcontroller or sensor runs from, it often does. Widen the trace, or bring the load closer, until the drop is small enough.

And the ground path carries the same current back. A wide supply trace with a thin ground return, or a ground pour cut into islands, just moves the drop to the other side of the circuit.

When the table is wrong

Short necks are fine. Thermal modelling by Brooks and Adam shows a trace that narrows for a few millimetres to enter a pad runs cooler than a long trace of that width, because the wide copper on each side draws heat away. The benefit shrinks as the neck gets longer; the table is for long runs.
Pulsed and switching currents heat a trace by their RMS value, not their peak. A motor that draws 5 A at start-up for half a second doesn't need a 5 A continuous trace, but a regulator's switching loop needs a short, wide path for reasons that have nothing to do with heat.
Vias are the bottleneck. A power path that changes layer through one small via is limited by that via, not the trace. Use several.
Enclosures and hot neighbours raise the starting temperature. A 10 °C rise on a board already at 60 °C beside a regulator is a 70 °C trace.
Above about 10 A on 1 oz copper, the widths stop being practical traces. Use a pour, heavier copper on the power layers, or a bus bar.

Doing it for your own numbers

Every number above comes from the same code as PCBEditor's free trace width calculator and trace resistance calculator, so you can plug in your own current, copper, rise and length and get the same answers. In PCBEditor itself, stating a current in the description ("the motor rail carries 3 A") sizes that power net with the same IPC-2221 formula at a 10 °C rise; past 6 mm it lays 6 mm and tells you to use a pour, 2 oz copper or a bus bar instead. The full guide is on pcbeditor.com.

Which do you size by first, heat or voltage drop? I'd like to know how often the drop is what actually sets your power trace widths.

I Asked an AI to Design Six PCBs. Here's What a Pin-by-Pin Review Found.

Dibyaprakash Pradhan — Mon, 19 Oct 2026 07:14:10 +0000

"AI PCB design" demos tend to stop at a nice render. I wanted to know what happens after it: does the board actually work? So on 17 October 2026 I typed six one-paragraph prompts into PCBEditor (the browser EDA tool I work on), let it generate each board end to end, and then reviewed every one the boring way: exported KiCad board, BOM and datasheets side by side, pin by pin.

Short version: five of the six finished fully routed with zero DRC errors and exported Gerbers. Only one of those five was right the first time. The sixth, a 4-layer RP2040 board, didn't finish routing at all.

Update, 19 October: I re-ran the same six prompts on the next release. Four of the six came out right the first time. The results are near the end.

The six prompts

Each was one paragraph, with the parts and numbers I cared about spelled out. Here's the LiPo charger's, word for word:

Single-cell LiPo charger board: USB-C 5 V input, MCP73831 charger set to 500 mA, a charge status LED, a JST-PH 2-pin battery connector, and an AP2112K 3.3 V regulator output on a 3-pin header. 2-layer board.

The others: an ESP32-C3-MINI-1 board with a BME280 over I²C, USB-C, an LDO, a status LED and reset/boot buttons; an NE555 flasher alternating two LEDs at about 1 Hz from a 9 V battery; an Arduino Nano socket driving two DC motors through a DRV8833; an RP2040 with QSPI flash, a 12 MHz crystal and two 20-pin headers on four layers; and an ATtiny85 driving an SSD1306 OLED, with an ISP header and USB micro-B power.

A run takes a few minutes and goes through part research, netlist, placement, routing and a DRC pass, with a log of what it decided at each stage.

The LiPo charger, the one board that was right as generated: 2 kΩ on PROG for 500 mA, the charge LED on STAT, the regulator fed from the battery, 5.1 kΩ on both CC pins.

What the review found

None of these would have been caught by a design-rule check. All four boards passed one.

ESP32-C3: the reset button wasn't a reset button. I asked for "reset and boot buttons". BOOT was right, on GPIO9. "Reset" came out as a user button on GPIO4, with nothing on EN except its pull-up and capacitor. The planner read "reset button" as "a button".

555 flasher: one LED could never flash. The 555 itself was wired correctly (TRIG and THR tied, DIS between the timing resistors, RESET high). But the second LED had its cathode on ground and its resistor to 9 V, so it was simply always on. The timing was also off: 10 kΩ, 100 kΩ and 10 µF give 1.44 / (210 kΩ × 10 µF) = 0.69 Hz, not "about 1 Hz".

Nano motor driver: the Nano had no power. The prompt said "the Nano powered from the motor supply through its VIN pin". The VIN contact on the socket was unconnected, and the board's 5 V net hung off the Nano's +5V pin, which nothing on the board fed. Unplug the USB cable and the whole thing goes dark. The DRV8833 side was textbook, except VINT had 1 µF where the datasheet asks for 2.2 µF.

ATtiny85 OLED: wrong clock pin, no power, a duplicate header. The ATtiny85's I²C hardware (USI) uses PB0 for SDA and PB2 for SCL. SCL landed on PB1 and the push button on PB2. The USB micro-B connector was on the board but not wired to anything, and a second 4-pin header duplicated the OLED socket.

And one that wasn't the AI's mistake but it didn't catch: I asked for a 6-12 V motor supply on a DRV8833, which is rated for 10.8 V on VM (11.8 V absolute max). Nothing flagged it. That's on me as the designer, and it's exactly the kind of thing a tool should warn about.

Fixing by chat

Every fix was one plain-English message that named pins. For the 555:

D2 never flashes: its cathode is on GND, so it is always on. Connect D2's cathode to the 555 output (U1 pin 3, net LED1_CTL) instead of GND, keeping R4 from 9V to D2's anode. Also change R2 from 100k to 68k so the rate is about 1 Hz. Then reroute.

The editor rewired only the three affected nets and kept the other 58 traces where they were. 68 kΩ gives 1.44 / (146 kΩ × 10 µF) = 0.99 Hz. A second message added the 10 nF on pin 5.

The fix request on the right, with the edit log underneath: "Detecting D2 cathode tied to GND", then a reroute of only the nets that changed.

The lesson I didn't expect: re-check after every edit. On the ATtiny85 board, the message that moved SCL to PB2 and the button to PB3 also dragged the ISP header's MISO contact along with the button net, so the chip could no longer be programmed. It took a second message to put MISO back on PB1. The edit did what I asked; it also did something I didn't.

A layout problem the netlist can't show

The ESP32-C3 board had a correct netlist and a clean DRC, and a bad layout. The ESP32-C3-MINI-1's PCB antenna is the end of the module beyond its top row of pads, and Espressif wants it at the board edge with no copper underneath. The first layout put the module in the middle of the board, antenna over a resistor, the regulator and a ground pour covering the whole bottom layer.

Before: module mid-board, antenna end over parts and the bottom-layer ground pour. DRC: clean.

One message ("move U1 to the top board edge with the antenna end facing out, no copper under it") fixed it. The root cause was in the footprint data: its courtyard covered only the pad field, not the antenna, so placement treated the antenna as free board. That's been reported.

After: the antenna overhangs the top edge. 21 parts, 32.6 × 44.1 mm, two layers, all nets routed.

The one that failed

The RP2040 board was the stress test: a 7 × 7 mm QFN-56 at 0.4 mm pitch, QSPI flash, crystal, USB-C, a regulator and two 20-pin headers on four layers. Where it was wired, it was right: SD0-SD3 mapped correctly to the W25Q16, BOOTSEL through 1 kΩ on the flash chip-select like the Pico, 27 Ω USB series resistors. But:

GPIO26 to GPIO29 were left unconnected. The part check didn't recognise the RP2040's pin names GPIO26_ADC0 to GPIO29_ADC3 and concluded the chip has no GPIO26 to 29.
9 of 47 nets didn't route, and 2 DRC errors remained.
When I asked it to connect the four ADC pins, it refused the change rather than break existing routes, and the export held back the Gerbers.

Honestly, that's the behaviour I want from a tool when it can't do something: say so, name the nets, and don't hand me files that look finished.

Scorecard

Board	Parts	Chat edits	Result
LiPo charger	14	0	Routed, 0 DRC errors
ESP32-C3 sensor	21	2	Routed, 0 DRC errors
Nano motor driver	18	1	Routed, 0 DRC errors
ATtiny85 OLED	10	2	Routed, 0 DRC errors
555 flasher	11	2	Routed, 0 DRC errors
RP2040 (4-layer)	33	2, both refused or timed out	9 nets unrouted, 2 DRC errors

Re-run on the next release

The fixes for these went into PCBEditor 1.3.5. On 19 October I ran the same six prompts again, word for word, with no chat edits, and reviewed the exports the same way.

Board	17 October	19 October
LiPo charger	Right as generated	Right as generated
ESP32-C3 sensor	Reset button on GPIO4; antenna mid-board	Right as generated
555 flasher	One LED always on; 0.69 Hz	Right as generated
ATtiny85 OLED	SCL on PB1; USB not wired; duplicate header	Right as generated
Nano motor driver	Nano's VIN not wired	Nano's VIN still not wired
RP2040 (4-layer)	GPIO26-29 missing; 9 nets unrouted; 2 DRC errors	GPIO26-29 wired; 11 nets unrouted; 0 DRC errors

Four of six were right the first time, up from one. Checked against the datasheets:

ESP32-C3: the reset button is on EN, with the 10 kΩ pull-up and the capacitor, and BOOT is on GPIO9. The module sits at the top edge with a no-tracks, no-vias keep-out under the antenna.
555: the LEDs alternate. 10 kΩ, 68 kΩ and 10 µF give 0.99 Hz, and there's 10 nF on CONT.
ATtiny85: SDA is on PB0, SCL on PB2, the button on PB3 and MISO on PB1. The micro-B is wired (pin 1 to 5 V, pin 5 to GND, ID open), and there's only one OLED socket.
Nano: the DRV8833 now has 2.2 µF on VINT, and the run log caught the rating I'd missed: "U1 pin 12 (VM) is on VIN (11.6 V), above the 10.8 V recommended maximum". But the Nano's VIN contact was still unconnected, again with no message. It also added 1 kΩ pull-downs on the four driver inputs. They work, but they draw 5 mA from each Nano pin that's high, and the DRV8833 already has internal pull-downs.
RP2040: the part check now reads the GPIO26_ADC0 to GPIO29_ADC3 names. All four pins reach the header, along with GND, 3V3, VBUS, RESET and SWD. Routing is still the problem: 11 nets (13 connections) are unrouted on four layers. And this time the export didn't hold the Gerbers back. Open connections count as DRC warnings, not errors, and nothing in the exported files mentions them; only the run log does. The log also claimed there was no header contact left for GPIO26-29, which were already wired.

Two small mismatches remain. The 555's 10 nF control-pin capacitor sits on an electrolytic footprint. And the ATtiny85 board's BOM names a TE micro-B connector on a different maker's land pattern. Neither would stop the board working, but either would trip up an assembler.

So: better, and still not a replacement for the review. Every one of these turned up by working through the checklist below.

What I'd tell anyone trying AI PCB tools

Put the numbers in the prompt: part numbers, currents, frequencies, which pin does what. Anything you leave out gets decided for you.
Read the run log. It tells you what it left unconnected and why.
Review the schematic against the datasheets before you look at the copper. Power path, every reset/boot/enable strap, every special-function pin (I²C, ADC, USB, crystal, programming header), every rating against your supply.
Look at the layout for things DRC doesn't know about: antennas, connector orientation, decoupling distance.
After each chat edit, export and re-check, not just the pins you asked about.
Open the Gerbers in a viewer before you order.

The AI saved me the drafting on all six boards: parts lookup, symbols, footprints, placement, routing. It didn't save me the engineering. Every mistake above was found by reading a datasheet, and every fix was a sentence I wrote.

The full walkthrough, with the routed boards, 3D views, the DRC result and the export options, is at pcbeditor.com/ai-pcb-design.

Your Gerbers Passed the Upload Check. Here's What It Didn't Look At.

Dibyaprakash Pradhan — Sat, 17 Oct 2026 09:14:02 +0000

You upload a zip, the fab's page draws a board and shows a price. That proves one thing: their software could read your files. It can't prove the files describe the board you designed, because the files are all the fab has. A missing outline, holes that land beside their pads, a blank paste layer: all of them quote without complaint.

Before you pay, open the exact zip you're sending in a Gerber viewer and check seven things: the layer count, the board outline, the drill holes, the solder mask, the paste, the silkscreen and the board size. The two broken examples below came straight out of KiCad's own export, one checkbox each.

The reference: the zip KiCad 9 exported from a board that passes its design-rule check. The outline is yellow and the viewer measures 50.00 × 34.00 mm, which matches the design.

What an upload check can and can't tell you

A fab's upload step reads each file, works out which layer it is (from the X2 attributes KiCad writes, or from the file name), measures the board, counts holes and layers, and prices the job. Many fabs then review the files after you order and email questions if something looks odd. Both are useful. Neither knows what you meant, so neither can tell you that a layer is missing, that an outline should exist, or that the holes are 100 mm from where they should be.

1. Every layer you meant is in the zip

Count the copper layers first: a four-layer board needs four copper files, and a plot dialog with only the outer layers ticked produces a perfectly valid two-layer set. Then check each side that has solder mask and silkscreen has its own file, the outline is there, and there are drill files for plated and, if you have any, non-plated holes.

KiCad also writes a Gerber job file (.gbrjob) listing the layer count, thickness and every file's function. Some fabs read it. It's a list, not proof: the job file for the board in these pictures lists two paste layers, and both are empty (check 5).

2. The outline is there, closed, and drawn once

The outline (Edge.Cuts in KiCad, the profile in Gerber terms) is the only file that says where the board ends. Leave it out and every other layer still loads, which is why it's easy to miss.

The same export with Edge.Cuts unticked. Nothing looks wrong at a glance, but there's no board edge, and the only size anyone can measure is the copper's: 49.00 × 33.00 mm instead of 50 × 34.

Without it, the board size is a guess. The copper stops half a millimetre inside the edge, so a viewer reports 49 × 33 mm for a 50 × 34 mm board. A fab has the same problem and will either guess or ask, and asking costs a day.

An outline can also be present and still wrong. It must be closed (KiCad's design-rule check reports a malformed outline), drawn once, and include any cut-outs or slots as closed shapes inside it.

3. Every hole lands in its pad

Drill files are a separate format (Excellon) with their own origin and units. If the Gerbers and the drill file were written from different origins, the copper is right and the holes are somewhere else. In KiCad 9's own dialogs the two origins are one shared setting, so this happens when the files are exported separately: here kicad-cli plotted the Gerbers from the drill/place file origin and wrote the drill file in absolute coordinates, one flag each, as a script, an older KiCad or another tool can:

The board renders, but J1 and J2 have solid pads: their six holes, and the four vias, landed more than 100 mm away, off the board.

A smaller origin difference is worse, because the holes land partly in the pads and look almost right. Look at a through-hole part and at a via, and make sure the hole sits in the middle of the copper. While you're there, check mounting holes are in the non-plated file if they shouldn't be plated, and the tool sizes match the holes you designed.

4. The mask opens over every pad, and nowhere else

The solder mask file is a negative: what it draws is where the mask is removed. Turn on one side's copper and mask together and every pad should show an opening. Covered (tented) vias should have none; vias you want to probe should.

Gold is bare copper, where the mask opens: every pad has an opening. The four 0.3 mm vias stay covered, as this board's tenting setting asks.

On fine-pitch parts, look at the strip of mask between neighbouring pads. If it's thinner than your fab's minimum, it's dropped and the pads share one opening, which makes solder bridges more likely.

5. The paste layer isn't empty

Paste layers matter only if you order a stencil, and then they are the stencil: an opening on every SMD pad, none on through-hole pads. The board in these pictures has 27 SMD pads and empty paste files (we removed the paste to photograph bare copper). Both files are in the zip and both are listed in the job file, so a file count passes. Turn on the paste layers alone and there's nothing there, and a stencil cut from them would be a blank sheet of steel.

6. The silkscreen stays off the pads

Fabs clip silkscreen that falls on bare copper, so a designator printed across a pad comes back cut in half or missing. Check text is at least your fab's minimum height and line width, and that the bottom silkscreen reads mirrored when you look from the top. That's correct: you'll read it from underneath.

7. The size and stackup match the order form

The viewer's size readout should match your design, and the order form should match both: size, layer count, thickness and finish. A two-layer zip ordered as four layers, or a 1.6 mm design ordered at 0.8 mm, is a correct set of files and the wrong board.

Then check the design, not just the files

Everything above checks that the files say what the board file says. It doesn't check the board. Before you export, run your CAD tool's design-rule check with your fab's minimum trace, gap, drill and annular ring, not the defaults. If your fab runs an electrical test, KiCad can export an IPC-D-356 netlist so the tester knows which pads should connect.

The checklist

Open the zip you will upload. Not the export folder, and not the board file.
Count the layers. Copper equal to your stackup, mask and silkscreen per side, the outline, both drill files.
Find the outline. Closed, drawn once, cut-outs inside it, and the size matches your design.
Look through every hole. Each through-hole pad has a hole in it; vias sit inside their pads.
Read the solder mask. An opening over every pad, none over vias you meant to cover, no slivers thinner than your fab can make.
Check the paste, if you order a stencil: SMD pads only, and not empty.
Read the silkscreen. Nothing on pads, text above the fab's minimum, bottom side mirrored from the top.
Match the order form. Size, layer count, thickness and finish agree with the files.

Every image here is PCBEditor's free Gerber viewer opening files that kicad-cli 9.0 exported from one board; the broken sets come from export settings, not hand edits. The viewer reads the zip in your browser, with no sign-up. The full guide is on pcbeditor.com.

What's the Gerber mistake that cost you a board? I'm collecting the ones a viewer would have caught and the ones it wouldn't.

KiCad vs EasyEDA vs Altium in 2026: Pick by the Job, Not the Hype

Dibyaprakash Pradhan — Wed, 14 Oct 2026 10:58:01 +0000

"Which PCB software should I learn?" gets asked every week, and the answers usually come from whatever the person answering happens to use. So here's an attempt at a fairer version: what each of the three big options is good at, taken from each one's own published material, and which job it fits.

EasyEDA: the gentlest start

EasyEDA is free, runs in a browser (with desktop clients if you want them) and comes in two editions: Standard, aimed at students and education, and Pro, with larger designs, constraint-driven design, team features and a full offline mode. Both include SPICE simulation.

Its real advantage is what it's connected to: the LCSC parts catalogue and JLCPCB's fabrication and assembly. You place a part that's actually in stock, and the board, the bill of materials and the assembly files line up with what will be sent to you. For a first board that removes a whole class of mistakes. The trade-off is that the workflow is built around one supply chain.

KiCad: free, open, and serious

KiCad is free and open source (GPL-3.0), runs on Windows, macOS and Linux, and works completely offline. It stopped being "the hobbyist option" a while ago. Version 10, released in March 2026, added design variants, time-domain length tuning for high-speed nets, a graphical rule editor and importers for Allegro and PADS, on top of a good push-and-shove interactive router and built-in SPICE.

A two-layer board drawn in KiCad 9, routed with the external Freerouting autorouter and rendered with KiCad's own 3D models.

The cost is learning time. Libraries, footprint assignment and board setup take a while, and KiCad doesn't ship an autorouter. You route by hand with the interactive router or use an external one like Freerouting.

Altium: when the licence pays for itself

Altium Designer is a commercial Windows application sold by subscription, priced per seat, with a free trial; its own pricing page has the current tiers. What you pay for is depth: signal-integrity and constraint tools for high-speed design, managed libraries tied to supply-chain data, mechanical CAD integration, and collaboration for teams on the same product.

One person drawing boards with no gigabit interfaces won't use most of that. A team shipping DDR, PCIe or RF products to production usually will. Altium also has CircuitMaker, a free Windows tool on its engine for personal projects.

Which one for you

First board, ordering from JLCPCB: EasyEDA.
Free forever, any OS, offline, open source: KiCad.
A skill that carries into many jobs and open hardware: KiCad.
A team shipping high-speed or regulated products: Altium.
Altium's engine for personal projects, free, on Windows: CircuitMaker.

Switching later

Moving between them is rarely clean. KiCad imports Altium designs and EasyEDA imports several formats, but footprints, design rules and stackups usually need fixing afterwards, and libraries don't travel perfectly. Fabrication output does: all three export Gerber, drill, BOM and pick-and-place files, so the fab never cares which one you used.

A different first step

I work on PCBEditor, which isn't a fourth editor for the same job. It covers the step before: you describe the board in plain English, an AI chooses parts and intent, and deterministic algorithms build the netlist, place, route and check it. You can then export Gerbers, or open the native KiCad file and keep working in KiCad. If drawing the first version is the part that's stopping you, that's what it's for. The full comparison table is on pcbeditor.com.

Which one did you start with, and would you pick it again?

Via-in-Pad: The Space Saver That Quietly Drains Your Solder Joints

Dibyaprakash Pradhan — Tue, 13 Oct 2026 16:53:58 +0000

"Vias directly on SMD pads?" is one of the most-viewed PCB questions on Electrical Engineering Stack Exchange, and the answers there all say some version of "it depends". It does, but on one thing only: what happens to the hole.

The problem with an open hole

A plated hole is a capillary. During reflow, molten solder on the pad flows into the via and runs down the barrel. The joint above is left with less solder than the stencil gave it. On a big pad that's a weaker joint. On a small resistor or a fine-pitch lead it can be almost no joint at all, an intermittent connection you can't see.

Dog-bone fan-out, via-in-pad and QFN thermal vias on one real board. A top view can't show the fill: the middle panel's vias must be filled and capped.

It also causes a strange, specific failure: tombstoning. Put a via in one pad of an 0402 resistor and not the other, and the two ends wet differently. The side that keeps its solder pulls the part upright. If your small parts stand on end, and only on certain pads, look for vias in those pads.

When via-in-pad is the right call

Fine-pitch BGAs. Between closely spaced balls there's no room for a via and a trace. The inner balls go down through vias in their pads.
Boxed-in pads. On dense packages some inner pads are surrounded by others with no path out on the top layer. A via in the pad is the only exit.
Thermal pads. The exposed pad under a QFN or power part is usually stitched to inner ground with an array of vias to carry heat. That's normal practice; keep drills small and follow the part's recommended land pattern.
Very short high-speed connections, where removing the trace between pad and via removes a little inductance.

What to tell the fab

IPC-4761 names seven ways to protect a via, Type I to Type VII. Tenting and plugging (Types I to IV) are for ordinary vias that aren't in a pad. For a via under a solder joint you want Type VII: filled and capped, often sold as VIPPO (via-in-pad plated over). The hole is filled, sanded flat and plated over, so the pad solders as if there were no hole.

It costs extra (fill, cure, planarise, plate) and sometimes adds lead time, and some budget fabs don't offer it. Check before you design around it, and write it in your fabrication notes so it isn't missed.

The decision in four lines

Room for a via beside the pad on a short trace? Use that (a "dog-bone").
Thermal pad under a QFN or power part? Thermal vias in the pad are normal; follow the land pattern.
Fine-pitch BGA or a boxed-in pad? Via-in-pad, filled and capped, and tell the fab.
Small passive or ordinary fine-pitch lead? Don't put an open via in it.

How we ended up dealing with it

The router in the AI PCB tool I work on escapes dense parts with ordinary vias wherever there's a path. We only added via-in-pad when a real board, a chip-down nRF52840 in a fine-pitch package, had pads that were completely boxed in: no amount of clever routing gets a trace out of a pad that has no gap next to it. The router now launches only those pads through a via in their own centre, picks the smallest via that fits, and in review mode it asks before doing so, because the moment a board has signal vias in pads, the fab order has to change too.

That's the general lesson: via-in-pad isn't a layout trick, it's a manufacturing decision. The guide with cross-section diagrams of the three options and the full IPC-4761 table is on pcbeditor.com.

Have you had a via-in-pad board come back with bad joints? I'd like to know whether it was the via, the fill spec, or the fab.

AGND, DGND and Chassis Ground: The Three Grounding Questions Everyone Asks

Dibyaprakash Pradhan — Mon, 12 Oct 2026 12:21:27 +0000

Grounding advice has a reputation for contradicting itself. Split the plane; don't split the plane. Ground the chassis; don't make loops. Part of the problem is that three different questions get asked as if they were one. They have different answers, and knowing which one you're facing is most of the job.

1. The chip has AGND and DGND pins. Do I connect them?

ADCs, DACs and some sensors have separate AGND and DGND pins, and the names make it sound like an instruction to keep two grounds apart. It isn't. The pins are separate inside the package so the analog and digital currents don't share the chip's own tiny bond wires.

For most converters, Analog Devices' guidance (their tutorial MT-031 is the classic reference) is to connect both pins to the same low-impedance ground plane, right at the chip, with the shortest connections you can manage. The digital currents these chips draw are small, so tying DGND to the analog ground does far less harm than separating them, which would put the chip's two grounds at different voltages.

Always check the converter's own datasheet and evaluation board layout first. That's the exception that matters.

2. Should I split the ground plane into analog and digital?

Usually not, and this is the one people find hardest to believe. A return current follows the path directly under its own trace. Cut a slot in the plane and the current has to detour around the gap, making a loop that radiates and picks up exactly the noise you were trying to avoid.

A real mixed-signal layout. Top: analog left, digital right, the converter on the boundary, and one chassis point (a plated hole with 1 nF and 1 MΩ to ground) by the USB connector. Bottom: one ground plane, unbroken under the analog side.

What you separate is the parts, not the plane. Put the analog circuitry on one side, the digital and switching circuitry on the other, with the converter on the boundary. Route analog traces only over the analog area and digital traces only over the digital area. The plane stays whole, and the noisy return currents stay on their own side because that's where their traces are.

The partition only works if traces respect it. A single clock line routed through the analog area brings its return current with it. If a signal has to cross, cross at the converter.

3. Should circuit ground connect to the metal chassis?

Usually at one point, near the connectors where cables enter. The chassis is a shield and the place static discharge and cable noise end up, and the goal is to send that energy to the chassis where it comes in, without it travelling through your circuit first.

One connection, close to the I/O connectors.
Cable shields bonded to the chassis at the entry, ideally all the way round, not via a long pigtail wire.
If you need DC isolation between circuit and chassis, a capacitor at that point, often with a high-value resistor in parallel to bleed off static charge.
Not several scattered connections, which push current through the enclosure between them.

For mains-powered equipment in a metal case there's a safety requirement on top: the chassis is bonded to protective earth as your product's safety standard specifies. That's not a layout choice, and it's never the thing to remove to fix a hum.

Bonus: the isolated supply

An isolated DC/DC converter exists so that its two sides don't share a ground. Connecting them on the board throws away the reason you bought it. Draw the isolation barrier as a clear line, with no copper, pour or trace crossing it, and keep the spacing the converter and your safety requirements ask for. IPC-2221's conductor spacing table is a floor; safety standards often want more.

A short layout check

Continuous ground plane under analog and digital areas, no slots under fast traces.
Converter AGND and DGND to the plane right at the chip.
Analog traces over the analog area only, digital over digital.
Decoupling at every power pin with a short path to the plane.
Circuit ground meets the chassis once, near the connectors.
Nothing crosses an isolation barrier except the isolator.

The full guide, with a diagram of the partitioned board and the chassis connection, is on pcbeditor.com.

Which grounding rule have you had to break, and why? The exceptions are the interesting part.

Can You Trust an AI-Designed PCB? What to Check Before You Order

Dibyaprakash Pradhan — Sun, 11 Oct 2026 17:58:58 +0000

An AI tool can hand you a placed and routed board in minutes. The useful question isn't whether it looks right. It's which parts of it were decided by a language model and which were computed, because those two kinds of output fail in different ways and need different checks.

This is the system card for PCBEditor, which turns a plain-English description into a placed, routed, design-rule-checked PCB with standard fabrication files. It explains how the work is split between the model and the deterministic engines, what that means for what you should check, and ends with a checklist to run before you send a board to a fab. PCBEditor is a hosted application, so no model weights come with this card.

The 3D view: the board as an assembly, with the parts' 3D models in place.

1. Know which decisions came from the language model

PCBEditor splits the job in two:

Judgement, by a language model: choosing parts, proposing a topology, drafting the netlist. This is reasoning over prior art, which is what language models are good at. The system is model-agnostic and runs on hosted APIs (currently AWS Bedrock); no model is fine-tuned.
Measurement, by deterministic engines: placement, multi-layer routing, design-rule checks and export. A language model has no way to measure whether a trace clears a pad by 0.15 mm, so it is never asked to. Routing is done by Sadie, an autorouter written in Rust (multi-layer A*, rip-up and reroute, Hammerstad–Jensen impedance modelling, graph-based connectivity proof).

What this means for your review: put your attention on the model's decisions, the parts and the connections. Mistakes there look plausible on screen: a wrong pinout or a missing pull-up resistor passes every geometric check. The geometry is computed, so check it with tools rather than by eye.

2. Expect the same board twice, but only from the same netlist

The model stage can return a different draft on a different run, and certainly on a different model version. The layout stage doesn't: the same netlist and the same rules give the same board. A review you did yesterday still describes the board you have today, even if the model behind stage one has been updated.

What this means for your review: once you have checked a schematic, keep it and build from it. Generating again from the same prompt gives you a new draft, and a new draft needs a new review.

3. Verify the board outside the tool that made it

The output is standard fabrication data: Gerber (RS-274X), Excellon drill, pick-and-place and BOM, plus a native KiCad .kicad_pcb file. That means you can check it with software you already trust:

Open the .kicad_pcb file in KiCad and run its design-rule check with your fab's rules.
Load the Gerbers and drill file into a Gerber viewer and look at every layer, the board outline and the holes.

A result you can only verify inside the vendor's own tool isn't verified.

The routing view: copper on each layer in its own colour, with vias and pads.

4. Read the unrouted list, not a percentage

When a board can't be fully routed, PCBEditor names the specific nets it couldn't complete instead of reporting a completion percentage. A figure like "94% routed" hides which connections are missing; a list of net names tells you exactly where to look.

What to do with it: most unroutable boards are placement problems. Move the parts at the ends of the named nets, give dense parts more room around them, and route again.

5. Know where it is weakest, and plan around it

Dense fine-pitch BGAs are the hardest case. They need escape routing before a general router can help, and this is where you are most likely to see unrouted nets today. Plan for more layers or via-in-pad on those parts.
It is not a signal-integrity suite. Controlled-impedance nets are handled during routing, but demanding high-speed or RF designs still need dedicated signal-integrity analysis.
AI output is a first draft. The reliable workflow is AI drafts, a human reviews. Confirm the schematic before it becomes copper.
The part library is smaller than in long-established desktop tools. For unusual parts, check the footprint against the datasheet's land pattern.

The exploded stackup: layers pulled apart so traces and vias can be inspected layer by layer.

6. Use it where it fits

PCBEditor is built for prototyping, learning and small-to-moderate board designs, particularly where no desktop CAD is available: a Chromebook, a tablet or a locked-down machine. It is not a replacement for a professional EDA suite on complex production hardware, and it is not a replacement for engineering review.

7. Know where your design data goes

Designs are processed on PCBEditor's servers. Prompts and design intent are sent to a hosted model provider as part of generation. Footprint and symbol data come from the KiCad libraries, which the KiCad project licenses under CC-BY-SA-4.0. The privacy policy has the details.

Checklist before you order

Check every part choice and pinout against its datasheet, especially power, ground, enable and boot pins.
Confirm the schematic before generating copper. Generating again means reviewing again.
Make sure the unrouted list is empty.
Open the .kicad_pcb file in KiCad and run the design-rule check with your fab's rules.
Look at the Gerbers and drill file in a viewer: layer count, board outline and holes.
Compare minimum trace width, spacing, drill size and annular ring with your fab's capability sheet.
Give high-speed or RF nets a separate signal-integrity review.
Order a small prototype run before a production run.

Links

Originally published as PCBEditor's system card on Hugging Face.

Getting Off the Arduino: What the Uno Was Doing That Your PCB Now Has To

Dibyaprakash Pradhan — Sun, 11 Oct 2026 08:31:13 +0000

The project works. It's an Uno, a breadboard and a nest of jumper wires, and every time you pick it up one of them comes loose. The next step is obvious: put it on a printed circuit board. And that's usually where projects stall, because it feels like a different skill.

It's less of a jump than it looks. Most of what goes wrong comes from one thing: forgetting what the Arduino board was doing for you.

Three ways off the Uno

There isn't one right answer here, and choosing deliberately saves a lot of grief.

A shield. Your circuit on a board that plugs onto the Uno's headers. Fastest, and the Uno keeps doing USB, power and programming.
A module on your board. Sockets for a Nano or a Pro Mini on your own PCB. Smaller, and you still don't design the microcontroller circuit.
A bare ATmega328P. The chip itself on your board, with everything around it. Smallest and cheapest per board, and the most to get right.

If it's your first PCB, the module route gets you a real board with the fewest new things to learn. Plenty of finished products are a module on a carrier board.

What the Uno was hiding

Around its ATmega328P, an Uno carries:

Everything the Uno does around its chip, as a KiCad schematic that passes its electrical rules check.

A 16 MHz clock (custom boards usually use a crystal with two 22 pF capacitors to ground)
A 10 kΩ reset pull-up and a reset button
Decoupling: 100 nF at VCC, at AVCC (tied to VCC) and at AREF
A regulator to make 5 V
A second chip that turns USB into serial, plus a 100 nF capacitor from DTR to reset, which is how the IDE resets the chip at the start of each upload

Shield and module routes keep all of that. The bare-chip route means putting every item on your board.

The one people leave off is decoupling. A bare ATmega328P on a breadboard often runs fine without capacitors at its power pins, so they don't make it onto the PCB either, and then the board resets whenever a motor or relay switches.

Draw the schematic before anything else

The breadboard hides mistakes that a PCB makes permanent, so write every connection down as a schematic first, wire by wire. Use the chip's real pins, not the Arduino names: D13 is PB5 (pin 19 on the 28-pin DIP), A0 is PC0 (pin 23), the serial pins D0/D1 are PD0/PD1 (pins 2 and 3). Every pin should be on exactly one net. A pin on two nets is a short.

A handful of layout rules that matter on a first board

Connectors, buttons and anything you plug in go on the board edges.
The crystal and its capacitors sit right at the XTAL pins, nothing routed under them.
Each decoupling capacitor sits at the pin it serves.
Two layers, one of them mostly ground pour.
Power traces wider than signal traces.
Mounting holes placed before routing, not after.
Label connectors, polarity and pin 1 on the silkscreen.
0805 parts or through-hole if you'll hand-solder.

Doing it with AI, honestly

I build an AI PCB tool, so here's how I'd use one for this, including what to check.

Describe precisely. Parts, packages, connections. The less it has to guess, the better.
Review the plan before anything is built. Wrong parts are cheapest to fix here.
Check the schematic. One net per pin, power and ground where they belong, LEDs the right way round.
Let it place and route, then read the report. You want zero unrouted nets and a design-rule check with zero errors.
Open the Gerbers in a viewer the tool didn't make.
Order five boards, not fifty.

On a small real example (a 2-pin power header and three LED-and-resistor branches, described in one paragraph), our tool placed and routed all five nets and the design-rule check came back with 0 errors and 0 warnings. The guide on the site shows the actual board and the actual log rather than a mock-up, because "it routed" is a claim you should be able to check.

The point isn't that the tool is never wrong. Each step has a check you can do yourself.

Getting code onto it

A bare ATmega328P usually arrives without the Arduino bootloader. Burn it once through a 6-pin ISP header (an Uno running the Arduino as ISP example works as the programmer), then upload sketches through a USB-to-serial adapter on a 6-pin serial header, with that 100 nF capacitor from DTR to reset doing the auto-reset. Or skip the bootloader and upload everything over ISP.

The full guide, with the Uno-to-standalone diagram, the pin map and the AI example, is on pcbeditor.com.

What made your first Arduino-to-PCB move go wrong? I'm collecting the failures that aren't on this list.

How to Read a Circuit Board: What All Those Little Markings Mean

Dibyaprakash Pradhan — Sat, 10 Oct 2026 17:59:02 +0000

"What do the PCB markings mean?" is, by a wide margin, the most-viewed PCB question I could find on Electrical Engineering Stack Exchange. That makes sense. Every board you'll ever repair, modify or reverse-engineer is covered in small white letters and symbols, and nobody explains them because the people who know them learned them by osmosis.

There are really only three kinds of marking: what a part is, which way round it goes, and facts about the board itself.

What a part is: reference designators

Every part gets a label: a letter or two for its type and a number, like R12 or U3. The same label appears in the schematic and the bill of materials, which is where the actual value lives. The letters follow common conventions:

1 designator, 2 pin-1 mark, 3 square pin-1 pad, 4 diode cathode, 5 LED cathode, 6 capacitor plus, 7 input polarity, 8 header pin names, 9 test point, 10 revision, 11 date code (year and week), 12 94V-0, 13 fiducial.

R resistor, C capacitor, L inductor, FB ferrite bead
D diode (LEDs are often D too), Q transistor
U (or IC) integrated circuit, Y or X crystal or oscillator
J and P connectors, SW switch, K relay, F fuse, T transformer
TP test point, JP jumper, BT battery, FID fiducial

The numbers say nothing about value or importance. They're assigned when the design is annotated, often left to right across the schematic, so R1 and R2 can be on opposite corners of the board.

Which way round it goes

Some parts only work one way. The board shows which, and the part carries a matching mark.

Chips: a dot, notch or cut corner marks pin 1, matching a dot or notch on the chip.
Through-hole parts: the square pad is pin 1; the rest are round.
Diodes: a bar on the outline marks the cathode, matching the band on the diode.
Electrolytic capacitors: the board marks the positive pad with a plus sign or shades the negative half; the stripe on the can is the negative lead.

And the one that catches people: tantalum capacitors are marked the other way. On a tantalum, the bar is the positive end. Fit one backwards and it can fail violently. Trust the board's plus sign, not just the stripe.

Facts about the board

REV B, V1.2: the design revision. Check it before trusting a schematic you found online.
A four-digit number like 2641: usually a date code, year and week of manufacture, though the order varies.
94V-0: the UL 94 flammability rating of the board material; V-0 is the strictest of the vertical-burn ratings.
Small copper dots in the corners: fiducials, targets for the pick-and-place machine's camera.
A random alphanumeric string: some low-cost fabs print their order number on the silkscreen unless you tell them where to put it.

Markings on the parts themselves

SMD resistors usually carry a code: 103 is 10 × 10³ = 10 kΩ, 4701 is 4.7 kΩ. Small SMD ceramic capacitors usually carry nothing at all, so you measure them. Tiny transistors and chips carry a two- or three-character marking code instead of a part number; search for the code plus the package name ("SOT-23") to find candidates.

Using all this

When I'm tracing an unfamiliar board, I start at the connectors (J) and the power parts (a U with an L and some large Cs around it is usually a regulator) and follow the copper. Test points are there so a probe can reach important nets, and they're often labelled with the net name. A burned part with an unreadable body still has its reference designator next to it, which tells you its type, and its neighbours usually tell you its job.

The full guide, with an annotated board diagram and the complete designator table, is on pcbeditor.com.

What's the strangest marking you've found on a board? I'd like to add the odd ones to the guide.

Your Custom ESP32 Board Probably Fails on the PCB, Not in the Firmware

Dibyaprakash Pradhan — Fri, 09 Oct 2026 08:31:36 +0000

The first custom ESP32 board most people make works on the bench and misbehaves everywhere else. The Wi-Fi range is half what the dev board had. The chip resets the moment it tries to connect. Or it never boots at all, and the serial monitor shows nothing. Everyone's first instinct is the firmware. On a custom board it is almost always the PCB.

I build an AI PCB tool, so I spend a lot of time looking at ESP32 boards, generated and hand-drawn, and the same five mistakes show up again and again. Here they are, in the order they tend to bite.

1. Copper under the antenna

An ESP32 module has its antenna printed on its own little board, and that antenna only works if your board leaves it alone. Copper near it, on any layer, detunes it. Every module datasheet has a keep-out drawing for exactly this, and Espressif's layout advice is always the same: put the module on an edge of your board so the antenna sits at or past the edge, with nothing under or around it.

A routed two-layer ESP32-S3 board in KiCad: the antenna sits on the board edge with no copper beside or under it, and USB and power come in from the opposite edge.

The way this goes wrong is innocent. You pour ground on both layers because a ground pour is good practice, and the pour fills straight under the antenna. The board works next to the router and drops out two rooms away. Draw a keep-out zone over the antenna area on every copper layer before you pour, and the pour can't fill it.

The same goes for what surrounds the board: a metal case, a battery or a big connector next to the antenna does the same damage. If the product has a metal enclosure, plan for a module with an external antenna connector from the start.

2. A 3.3 V rail that sags when the radio talks

An ESP32 draws little current on average and short, sharp peaks when it transmits. Espressif recommends a supply that can deliver at least 500 mA. A regulator that copes with the average sags on the peaks, the brownout detector trips, and the board resets every time it tries Wi-Fi. That looks exactly like a firmware bug.

What fixes it: a regulator rated for 500 mA or more (from USB 5 V, something like an AP2112K-3.3 works), bulk capacitance of around 10 µF plus a 100 nF ceramic right at the module's 3V3 pin, and a short, wide path from regulator to module. A 100 mm, 0.25 mm trace on 1 oz copper is about 0.2 Ω, which is 0.1 V gone at 500 mA, before the module's own capacitor.

If you're running from one Li-ion cell, remember the cell sits between 4.2 V and 3.0 V, so an ordinary LDO stops regulating long before the cell is empty.

3. EN without its delay

The EN pin starts the chip when it goes high. If it rises together with a slowly ramping supply, the chip can start before its power is stable. Espressif's reference design adds an RC delay: 10 kΩ pull-up to 3.3 V and 1 µF to ground. Add a reset button from EN to ground and a BOOT button on the boot strap (GPIO0 on the ESP32 and ESP32-S3, GPIO9 on the C3). Two buttons cost nothing and save the day you need to recover a board with broken firmware.

The same board's schematic, drawn with KiCad's own symbols and passing its electrical rules check.

4. A strapping pin pulled the wrong way

Strapping pins are ordinary GPIOs that the chip reads at reset to decide how to boot. You can use them after boot, but whatever you connect must not pull them the wrong way during reset.

Original ESP32: GPIO0, GPIO2, GPIO5, GPIO12, GPIO15
ESP32-S3: GPIO0, GPIO3, GPIO45, GPIO46
ESP32-C3: GPIO2, GPIO8, GPIO9

The classic trap is GPIO12 on the original ESP32. It sets the flash voltage at boot. Put a pull-up or a sensor on it that holds it high at reset, and a module with 3.3 V flash simply won't boot. No error, no output, nothing.

5. USB-C with one CC resistor

The ESP32-S3 and C3 have native USB on fixed pins (GPIO19/20 on the S3, GPIO18/19 on the C3), so no USB-to-serial chip is needed. Route D+ and D− as a short pair over solid ground and put an ESD array at the connector.

The USB-C part people get wrong is power. A USB-C sink needs a separate 5.1 kΩ resistor from CC1 to ground and another from CC2 to ground. Leave them off and C-to-C chargers won't turn on VBUS. Share one resistor between both pins and e-marked cables make some chargers refuse power, which is exactly the bug the first Raspberry Pi 4 boards shipped with.

A ten-point check before you order

Antenna at or past the board edge, keep-out on every layer matching the datasheet.
Nothing in the keep-out: no pour, trace, via, part or mounting hole.
Module ground pad stitched to the plane with several vias.
Bulk and 100 nF capacitors at the 3V3 pin; regulator rated 500 mA or more.
EN pull-up, delay capacitor and reset button; BOOT button on the strap.
No strapping pin held the wrong way at reset.
USB D+/D− short and paired, ESD at the connector.
One 5.1 kΩ resistor per CC pin.
Regulator and any switcher away from the antenna.
Design-rule check clean against your fab's limits.

None of these needs special tools. They need you to look at the board with the right list in hand. The full guide, with diagrams of the layout and of the EN, boot and USB-C circuits, is on pcbeditor.com.

Which of these has bitten you? I'd like to hear about the ESP32 board failures that weren't on this list.

How to Evaluate AI PCB Software: 11 Questions to Ask Any Vendor

Dibyaprakash Pradhan — Thu, 08 Oct 2026 09:13:24 +0000

Most "AI PCB software" content is either a vendor telling you their tool is great, or a skeptic telling you AI can't do hardware. Neither helps you when you're actually trying to pick a tool. What helps is a checklist you can run against anyone — the vendor included.

Here are the eleven questions I'd ask, with what a good answer looks like before I say what ours is.

Does it export standard Gerber files?

A real answer names the formats: Gerber RS-274X, Excellon drill, pick-and-place (CPL) and a BOM. If a tool only offers its own project format, or a PDF, or an image of a board, your fab cannot build it. Ask for a sample output and open it in a free Gerber viewer before you trust it.

PCBEditor exports Gerber, Excellon drill, pick-and-place and BOM — the same file set you'd send from any desktop EDA, with no export tier or paywall.

Can it generate fabrication-ready files, or just a picture of a board?

"Fabrication-ready" means a fab house can accept the output as-is: correct layer mapping, a drill file that matches the copper, no approximated geometry. Many AI demos produce a convincing rendering with no manufacturable data underneath. The test is simple — send the output to a fab quote tool and see whether it parses.

The board is built by a deterministic engine working in real units, so what you export is measured geometry, not an approximation of one.

Can I run DRC in my own CAD tool afterwards?

This is the question that separates an open tool from a trap. You should be able to take the output into KiCad, Altium, or your own flow and re-run design-rule checks independently. If a vendor's results can only be verified inside the vendor's own software, you have no way to audit them.

Output is standard fabrication data, so you can re-check it in whatever tool you already trust. An AI result that can't be independently verified isn't a result.

Does it explain why it placed a component or picked a part?

Ask for the reasoning, not just the outcome. A tool that can say "this regulator because of the input range and thermal budget, this capacitor here because it's the supply pin" is one you can argue with and correct. A black box that emits a board gives you nothing to review — and reviewing is the whole job.

Part choice and intent come from a language model that states its reasoning, so you can read it, disagree with it, and change it before anything becomes copper.

Which AI router is best for BGA-heavy boards?

Be skeptical of any single answer here, including ours. Fine-pitch BGA work is the hardest case in autorouting — it needs escape routing before a general router can help, and it's where every tool is weakest. The right question to a vendor isn't "can you do BGA" but "show me a BGA board you finished, and tell me which nets you couldn't route."

Dense fine-pitch parts are the area we're actively working on, and where you're most likely to see unrouted nets today. We'd rather say that than claim otherwise.

What about DFM — will it actually manufacture?

Design for manufacturability is separate from design-rule checking. Ask whether the tool enforces your fab's real capabilities — minimum trace and space, annular ring, drill sizes — rather than generic defaults. Then confirm with your fab before a first run, every time, whoever produced the design.

Rules are enforced during routing rather than flagged afterward, and the checks run against the constraints for the board you're building — but confirming against your chosen fab's capability sheet is still the right final step.

Is the result reproducible?

Run the same design twice. If you get two different boards, the layout is coming from a language model, and it'll keep drifting every time the model is updated. For hardware you want the same input to produce the same output, so a review you did yesterday still describes the board you have today.

Routing is deterministic: same design in, same board out, and it doesn't change when the model behind the judgement half is swapped or upgraded.

Can it route a multi-layer PCB automatically, or just two layers?

A board with real density needs more than two copper layers — internal ground or power planes for noise control, extra signal layers for escape routing on fine-pitch parts. Ask whether layer count is fixed at two, or whether the tool actually places vias and routes across an internal stackup, not just a single top/bottom pass.

Layer count is something you choose — 2, 4, 6, 8 and up — and the deterministic router places vias and routes across the full stackup, including stitching internal ground and power planes, not just a top/bottom trace pass.

Does it actually reduce board respins?

This is the question that matters most to a budget. Most AI PCB demos only check whether traces are far enough apart — a design-rule check. The boards that come back wrong are usually wrong somewhere DRC can't see: a shorted input, an enable pin wired backwards, a USB connector that backfeeds power. Logic-level mistakes that pass a clean DRC and still don't work.

DRC catches geometry. Separately, every generated board runs an electrical-integrity audit on the final netlist, checking for the failure modes that cause real respins — shorted connector contacts, enable pins wired to the wrong polarity, USB backfeed — before you export anything.

Can I import an existing design, or only start from scratch?

A tool that only exports is a one-way street: useful for a first draft, useless for the board you already have half-finished. Ask whether you can bring an existing project in, not just take a new one out.

PCBEditor reads and writes native KiCad .kicad_pcb files and imports Gerber archives, so an existing KiCad board can be opened and continued here. Altium, Cadence and OrCAD files are not imported.

If it gets a part or connection wrong, do I start over or can I fix it?

AI output is a first draft, and first drafts have mistakes. The real question is what fixing one costs you: do you edit the one part or connection that's wrong, or does any change mean throwing away the board and starting the whole generation over?

Corrections happen by chat, targeted at what you ask for — swap a part, fix a connection, reroute one section — without regenerating the whole board. It's still worth checking the change only touched what you asked for, the same discipline as reviewing any edit.

Run this against whoever you're evaluating

None of this is specific to one vendor. Ask it of us, ask it of whoever else you're considering, and weight the answers by what actually matters for the board you're building this week — a BGA-heavy design cares about question five more than question nine; a respin-burned team cares about question nine more than anything else on the list.

The honest version of this page lives at pcbeditor.com/evaluate-ai-pcb-software, kept current as the questions people actually ask keep changing.

Can ChatGPT Design a PCB? What Its Netlist Gets Wrong Once You Try to Build It

Dibyaprakash Pradhan — Sun, 04 Oct 2026 07:57:27 +0000

Search "ChatGPT PCB design" and you find two camps. One says it can do everything. The other says it is useless. Both are wrong, and the useful answer sits in a specific place: the netlist.

The short answer

ChatGPT cannot design a manufacturable PCB on its own. It can help you choose parts, explain a topology and draft a netlist in text. It cannot place components, route copper, run a design rule check or produce Gerber files, because it has no geometry engine and no rule checker.

ChatGPT is good at the half of PCB design that is judgement, and structurally unable to do the half that is geometry. Knowing which is which saves a lot of wasted effort.

What ChatGPT is genuinely good at

Picking parts. Describe what the circuit must do and it will suggest a regulator, a microcontroller or a sensor family worth considering.
Explaining. It can explain a topology, sanity-check a power budget, or talk you through why a decoupling capacitor belongs close to a supply pin.
Drafting. It can draft a rough netlist in text form, which is a reasonable starting point for a design you intend to verify yourself.

If you are learning electronics, that is a patient engineer who never gets tired of "why". Use it.

The four things it cannot do

ChatGPT has no geometry engine. It cannot place components on a board with real dimensions, or produce copper that respects clearance.
It cannot route a multi-layer board. Routing is a search problem over physical space with hard constraints, not a text-generation problem.
It cannot run a design rule check. Without one there is no way to know whether the result is manufacturable.
It cannot output fabrication files. Gerber, Excellon drill and pick-and-place data are exact formats that a fab will reject if they are approximated.

None of that is controversial once you have tried it. The part people underestimate is the one ChatGPT can do.

The netlist looks finished. It usually is not.

A netlist is a list of which pin connects to which. It is text, so a language model produces it fluently, and it reads like the hard part is done.

I build an AI PCB tool, and language models draft netlists in our pipeline every day. The numbers below come from the models we run, not from ChatGPT itself. But none of these failures depend on which model you use. They come from asking any text generator to recall pin-level facts.

1. The same pin on two nets. In 4 of 6 boards we sampled, the model's netlist listed at least one pin on two different nets. That is a short circuit. The pattern was always the same: a power pin listed on its rail, then listed again on a signal net.

+3V3     -> ..., U1.1, ...
QSPI_CS  -> U1.1, U2.1

On an ESP32 board it was the pull-up resistor: R6.2 on both +3V3 and EN. Read as prose, each line looks reasonable. Only a check that asks "does any pin appear twice?" catches it.

2. Pinouts from memory. A battery charger IC, the MCP73831, came back as an 8-pin part with a "VPROG" pin. The real part is a 5-pin SOT-23-5. The model described a plausible chip that does not exist, with total confidence. A wrong pin map produces a board that cannot work, and nothing about the text tells you so.

3. The value field names the wrong thing. Asked for an Arduino Nano soldered to a board, the model wrote the Nano's value as "ATmega328P", the chip the Nano carries. Anything downstream that trusts that field builds the board around a bare 32-pin chip instead of the module. It is a reasonable sentence and the wrong part.

4. Same prompt, different circuit. Temperature 0 does not make a hosted model repeatable. Two identical runs of the same prompt gave us 48 nets and then 50 on one board, and 13 and then 11 on another. If you re-ask ChatGPT for the netlist, expect a slightly different circuit, and check the one you actually build.

Every one of these is a pin-level fact that has to be looked up, in a symbol library or a datasheet. Generating it is the wrong operation, and a better model does not change the operation.

How to use ChatGPT for PCB design anyway

This is the workflow that holds up:

Let it choose. Describe the board, ask for parts and the reason for each. This is the judgement half, and it is good at it.
Ask for the netlist, then distrust it. Treat it as a draft.
Check every pin against the datasheet, not against the model's memory. Especially power, enable, reset and anything on a module.
Check that each pin is on exactly one net. A ten-line script does this. It catches the most common short.
Hand the result to a tool that has geometry and rules: placement, routing, DRC and Gerber export are computed, not written.

What we built around that split

The split we landed on in PCBEditor is simple to say: AI decides intent, algorithms verify physics.

A language model chooses the parts and what the board is for.
Pins come from library data (KiCad's symbol library and the part's land pattern), never from the model's memory.
Nets are formed by rules over those pins, so the same parts give the same circuit every time.
Placement is constrained, routing is a deterministic router with no AI in it, and DRC is a rule engine.

The test we hold it to: if we swap the model tomorrow, the boards must still be correct. That is only true if correctness lives in code.

It is not magic, and this week proved it. A board passed routing and DRC with zero errors and was still electrically wrong: an amplifier's inputs were tied together. Routing and DRC check geometry, not whether the circuit works. So we added checks for exactly that: two outputs driving one net, a chip's own inputs shorted, a regulator bypassed. The lesson is the same one as above. Anything that must be true needs a check that measures it.

Quick answers

Can ChatGPT generate a schematic?
It can describe a schematic and produce a netlist in text form. It cannot produce a verified schematic with real footprints and pin mappings, because it has no component library to check against.

What is ChatGPT actually good for in hardware design?
Part selection, explaining trade-offs, reviewing a design decision, and drafting a first-pass netlist you intend to verify. Those are judgement tasks, which is what language models are good at.

Will a newer model fix this?
It will get better at the judgement half. Placement, routing, DRC and fabrication output need a geometry engine and a rule checker, and pin maps need a lookup. A newer model doesn't give you any of those, however good it is. GPT-6 Astra is a different question: it can drive KiCad on your desktop, which is new, but when it presses Auto-Route it is still KiCad's router doing the work. More on that in GPT-6 Astra for PCB design.

What should I use for the rest?
A tool that keeps AI for judgement and uses deterministic algorithms for placement, routing and DRC. That is the split this whole post argues for, and it is the one PCBEditor is built on.

A longer version of the can/cannot split, kept up to date, lives at pcbeditor.com/ai-pcb-design/chatgpt-for-pcb-design.

Have you built a board from a ChatGPT netlist? I would like to know what it got wrong for you, and whether you caught it before or after the boards arrived.