DEV Community: Dibyaprakash Pradhan

ESP32-P4 vs P4X: What Chip Revision v3.x Changes on Your PCB

Dibyaprakash Pradhan — Wed, 04 Nov 2026 11:04:22 +0000

Espressif's current ESP32-P4 parts end in X, the development boards are now called P4X, and a board laid out for the first P4 silicon does not simply take the new chip. Three parts of the circuit changed between chip revision v1.x and v3.x, and the firmware has to be rebuilt. Here is each change with Espressif's values, drawn in KiCad 9.

Short answer: "P4X" is the ESP32-P4 at chip revision v3.x: Espressif's datasheet lists ESP32-P4NRW16X and ESP32-P4NRW32X, both v3.x, and its P4X development boards carry v3.1 or later. On the PCB, three things change from v1.x: pin 54 goes from NC to VDD_HP_1 and needs the 1.1 V core supply with a 0.1 µF capacitor; the external DC/DC's feedback gets two 499 kΩ resistors and a 22 pF capacitor; and the 1 MΩ pull-down on USB_DP is no longer needed. Firmware must be built with ESP-IDF v5.5.3 or later (or v6.0) for v3.x.

What the X means

The ESP32-P4 datasheet (pre-release v0.7) now lists two parts, ESP32-P4NRW16X and ESP32-P4NRW32X, with 16 MB and 32 MB of PSRAM in the package, and gives both as chip revision v3.x. Espressif's chip revision v3.x user guide names the same two as its related products. The development boards follow: Espressif's documentation gives one difference between the ESP32-P4X-Function-EV-Board and the ESP32-P4-Function-EV-Board, the main chip, which is chip revision v3.1 or later on the P4X board.

What the X itself stands for, Espressif does not write down. The datasheet's nomenclature explains every other letter (N for normal-temperature PSRAM, R for PSRAM, W for 16-line 1.8 V PSRAM, the number for the PSRAM size in MB) and stops there. The same datasheet also says that several chip revisions can be on the market under the same part number. So read the X as "the v3.x part" when you order, and confirm the revision on the chip itself.

The three board changes at a glance

What	v1.0 / v1.3	v3.0 and later	What to do
Pin 54	NC (no connection)	VDD_HP_1, a digital supply pin (0.99 to 1.3 V)	Feed it from ESP_VDD_HP; Espressif uses a 0 Ω (R39) and 0.1 µF (C39) at the pin
DC/DC feedback (FB_DCDC)	R1, R2 and C2 as empty pads	R1 = R2 = 499 kΩ, C2 = 22 pF across R1	Fit all three; Espressif says they must be populated
1 MΩ on USB_DP	Fitted, to stop a current surge on VDD_USBPHY when CHIP_PU goes low	Not needed (the fault is fixed)	Optional; you may keep it so one layout suits both
Firmware	ESP-IDF builds for v1.x	ESP-IDF v5.5.3 or later, or v6.0 or later, built for v3.x	Rebuild; one image cannot serve both revisions

The DC/DC feedback: 499 kΩ, 499 kΩ, 22 pF

The P4's high-performance core does not run from your 3.3 V rail. Its four VDD_HP pins take 0.99 to 1.3 V (1.1 V typical) from an external step-down converter, and the chip controls that converter itself through two pins: EN_DCDC (pin 79) switches it on once the firmware starts, and FB_DCDC (pin 78) goes to the converter's feedback pin. Espressif's example is a TLV62569 with 4.7 µF in, a 2.2 µH inductor and 22 µF out.

On v1.x, the feedback resistors and capacitor were optional. Espressif's v1.x schematic shows R1, R2 and C2 as TBD(NC) with a note not to mount them by default, and the guidelines asked designers to keep the pads anyway.

On v3.0 and later, Espressif writes that the feedback resistor and feedback capacitor must be populated: R1 = 499 kΩ from the DC/DC output (ESP_VDD_HP) to FB_DCDC, R2 = 499 kΩ from FB_DCDC to ground, and C2 = 22 pF across R1. With its own TLV62569 values unchanged, that is the whole DC/DC difference. If you use another converter, pick it from Espressif's verified list (ETA3485, SY8088, RY3420, BL8028, LP3219 or TLV62569), take its input and inductor from its own datasheet, and place it close to the P4.

In download mode, or with no firmware, EN_DCDC is at 0; once the firmware starts, the P4 drives it, and in sleep it can use it to switch the supply off. Wire it straight to the converter's EN pin, as Espressif's reference schematic does.

Pin 54 becomes VDD_HP_1

On v1.0 and v1.3, pin 54 of the QFN104 package is NC. From v3.0 it is VDD_HP_1, one of the four high-performance supply pins: VDD_HP_0 is pin 26, VDD_HP_1 pin 54, VDD_HP_2 pin 76 and VDD_HP_3 pin 91. All four take the same ESP_VDD_HP rail.

Espressif's v3.0 reference schematic feeds pin 54 from ESP_VDD_HP through a 0 Ω resistor (R39) and puts a 0.1 µF capacitor (C39) right at the pin, the same 0.1 µF each VDD_HP pin gets; pin 26 also has the 10 µF bulk capacitor. On a layout, that means a trace or plane connection from the core supply to pin 54 and a decoupling capacitor beside it, at a pin that used to have nothing.

The 1 MΩ on USB_DP

On v1.0 and v1.3, Espressif adds a 1 MΩ pull-down on USB_DP to stop a large transient current on VDD_USBPHY when CHIP_PU is pulled low. In v3.0 and later that is fixed, and Espressif allows the 1 MΩ to stay for design compatibility. A related v1.x fix also goes away: on v1.0 and v1.3, VDD_USBPHY leaks current in low-power modes and Espressif recommends a MOSFET to switch it off. In v3.0 that is fixed too.

Will a v3.x chip work on my v1.x board?

Not without changes. Two of the three are part changes: fit R1, R2 and C2 on the pads Espressif told you to keep, and the 1 MΩ on USB_DP can stay. Pin 54 is the problem. A v1.x layout had no reason to route it, so on most boards the pad connects to nothing, and v3.x needs it on the core supply with a capacitor beside it. That is a layout change: plan a new board revision.

The datasheet allows several revisions under one part number. If your board is laid out for one revision only, check the manufacturing code on parts as they arrive, and on modules and development boards ask which chip revision is inside.

Which revision is on my board?

The manufacturing code line in the chip marking gives the revision. From Espressif's errata, chip revision identification:

Chip revision	Manufacturing code
v1.0	X C XX
v1.3	X E XX
v3.0	X F XX
v3.1	X G XX
v3.2	X H XX or X J XX

In software the revision is in eFuse: the major number in EFUSE_RD_MAC_SPI_SYS_2_REG bits 23, 5 and 4, the minor number in bits 3 to 0. esptool reads it and prints the chip revision when it connects.

Firmware: ESP-IDF v5.5.3 and the revision option

Chip revision v3.x needs ESP-IDF v5.5.3 or later, or v6.0 or later. Those versions add one option to sdkconfig, CONFIG_ESP32P4_SELECTS_REV_LESS_V3: n, the default, builds for v3.x; y builds for v1.x. A project started on an in-between ESP-IDF version may still carry CONFIG_ESP32P4_SELECTS_REV_LESS_V3=y, and then the firmware either fails to download to a v3.x chip or fails to boot after flashing. Set it to n and rebuild. Espressif is explicit that the two revisions cannot share one firmware image.

Drawing an ESP32-P4 in KiCad

KiCad 9.0.9's standard library has symbols for the ESP32-C3, ESP32-S2, ESP32-S3 and the PICO chips, and none for the ESP32-P4, so you will draw your own or bring one in. Build it from the current datasheet, not from a v1.x design:

Pin 54 is VDD_HP_1 with the power-input pin type. A symbol made for v1.x marks it NC, and KiCad's electrical rule check says nothing about an unconnected NC pin, so the mistake survives until the board does not boot.
Give FB_DCDC and EN_DCDC their own nets to the converter's FB and EN pins. Neither goes to your 3.3 V rail.
Put R1, R2 and C2 on the schematic with values, not as do-not-populate parts, and keep C39 beside pin 54 in the layout.

The two figures above were drawn that way: KiCad's own TLV62569DBV, resistor, capacitor and inductor symbols, Espressif's values and reference designators, and KiCad's DNP flag on the parts Espressif leaves unmounted.

The full guide, with Espressif's power checklist for the rest of a v3.x board (VDD_LDO, VDD_USBPHY, VDD_BAT, CHIP_PU timing) and the sources, is on pcbeditor.com.

AI and PCB Design: A Complicated Relationship That's Finally Settling

Dibyaprakash Pradhan — Mon, 02 Nov 2026 08:55:00 +0000

AI and PCB design have had a complicated couple of years.

First came the pitch: describe a board in a sentence, get Gerbers back. Then came the backlash, mostly from people who design boards for a living, and they had a point. A language model can recite everything about trace widths and clearances. It cannot measure either. Ask one to check a board and it sounds just as sure of itself whether the board is right or wrong.

What is settling now is less exciting than the pitch and more useful than the backlash: a division of labour. AI drafts and edits. Exact checks measure. You decide whether the board is the one you meant. Each side has stopped being asked to do the other's job.

I work on PCBEditor, a browser PCB tool built around that split, so this is one view from inside it. Below is how the split looks on a real board, and a checklist for the part that is still yours.

The short answer

You can verify much of a PCB automatically: design-rule violations, unrouted nets, overlapping parts, shorted connector pins, wrong enable levels and miswired USB connectors are all checked exactly. What no check catches yet is a circuit that is electrically valid but not what you meant, such as a reset button wired to a spare GPIO. That still needs a datasheet review.

The backlash had a point

The skeptics' real objection was never "AI can't learn electronics". It was that reciting a rule and applying it are different things. A model can explain why USB D+ and D- should run side by side. It cannot look at a layout and tell you that, on this board, they run 600 µm apart.

We saw the same thing when we asked a model to act as a rule checker on a board summary: it reported different error counts for the same board on different runs. A count that changes while the board doesn't is not a check.

So the first part of the settlement is to take counting away from the model.

Job 1: exact checks measure

A design-rule check verifies geometry against manufacturing limits: clearances, widths, drills, edges. A design review also asks whether the circuit is right: connections, pin functions, supply levels and whether the board matches what was asked for. A board can pass DRC and still not work.

So a useful AI PCB review checks more than geometry. PCBEditor's Review my design checks four groups and sorts every finding into "must fix" and "worth a look":

Design rules. Clearance between copper, trace width, annular ring, drill-to-drill and hole-to-copper spacing, board-edge margin, unrouted connections, and parts whose courtyards overlap (two parts on one spot cannot both be soldered, so that one counts as must-fix).
Electrical faults that pass a clean DRC. The final netlist is audited for mistakes geometry cannot see: connector contacts shorted together, enable pins held at the wrong level, a USB port that back-feeds the supply, a USB connector whose contacts carry the wrong signals, socket rows that do not match the module plugged into them, and nets that reach only one pin.
Signal and power details. Pairs such as USB D+ and D- that are not routed side by side, ground areas on different layers that are not stitched together, and a summary of every power path from its source to the parts it feeds.
Your request. An AI model compares what you asked for with the parts on the board and names any requested function that has no part, such as a missing regulator or sensor. This is the one judgement in the report, and it is shown separately from the checks.

Each rule or electrical finding comes with a fixed explanation of why it matters and what to do, and the example that triggered it. Those findings and their counts come from the checkers, not from a model, so the same board gives the same answer every time.

Review my design on an ESP32-C3 sensor board, 18 October 2026. The counts come from the design-rule and electrical checks.

On this board the review found a real problem we had noticed by eye: the regulator U3 and capacitor C6 sit so close that their courtyards overlap, so one of them cannot be placed. It also flagged the USB pair, which was routed 600 µm apart where it should run side by side, and a leftover net from an earlier edit that reaches a single pin. Those are exactly the findings a model is bad at and a checker is good at.

Job 2: AI drafts and edits

This is where language models really help: reading what you asked for, choosing parts, drafting the connections, and turning a plain-English request into a change on the board. In the review, AI does two things: the comparison with your request, and the fixes you ask for.

Fixing works the way asking does. Switch to Build and describe the change, naming the parts and pins ("move C6 away from U3"), or use Fix DRC with AI for rule violations. Then review again, because every edit can move something else.

Job 3: you judge what the board is for

This part has not moved to software, which is why the relationship is settling rather than settled. Checks prove what they check. A board that matches its own netlist perfectly can still have the wrong netlist.

Here is the kind of thing only you will catch, from one of our own test boards in October. A prompt asks for an ESP32-C3 board with reset and boot buttons. BOOT comes out right, on GPIO9. The "reset button" comes out as a user button on GPIO4, with nothing on EN. That is a perfectly valid circuit, because a button from a GPIO to ground is exactly what a user button looks like, so no check objects. It just isn't what you asked for.

The datasheet settles it. Espressif's schematic checklist says CHIP_EN enables the chip when high and resets it when low, must not be left floating, and usually gets 10 kΩ and 1 µF. So the review step is: find EN, check the pull-up and the capacitor, and check that the reset button pulls that net low. The fix is one sentence asking for SW1 to move to EN, keeping the 10 kΩ pull-up and 1 µF capacitor.

Layout context is the other place you are needed. A rule check has no idea which end of a module is the antenna. Espressif's layout guide wants a module's PCB antenna outside the base board, or at least its feed point as close to the board edge as possible, with a clearance area around it.

What is still open

Settling is not the same as solved. Three things still need a person:

Intent. A circuit that is electrically valid but not what you meant. Only a review against the datasheets finds it.
Layout context that isn't a rule. Antenna keepouts, which way a connector faces, room for the plug.
Dense, fine-pitch boards. A 0.4 mm-pitch QFN with flash and USB on four layers still needs a person to guide placement.

How to review an AI-generated PCB

Run the design-rule and electrical checks first, then read the schematic against the datasheets: power from the connector to every chip, every reset, boot and enable pin, special-function pins such as I²C and USB, supply voltages against part ratings, and required capacitors. Then check the layout for antenna keepouts and connector orientation, and re-check after every edit.

In the editor, that is five steps:

Open the board. Generate it from a description, draw it, or import a KiCad board, then switch to the PCB view.
Press Review my design. It runs the checks and changes nothing.
Read must-fix first. These stop the board from being built or working. "Worth a look" items are judgement calls.
Fix in plain English. Describe the change, naming the parts and pins.
Review again. Every edit can move something else, so run the review after each one.

Then work through the rest by hand.

Schematic

Power: every rail from the connector to each chip, input protection, regulator input range and dropout.
Ratings: every supply against every part's absolute maximum, and series parts (diodes, fuses) against the load current.
Straps: reset, boot and enable pins, each with its pull-up or pull-down and capacitor.
Special-function pins: I²C, SPI, UART, USB, ADC, crystal and programming header on the pins that have that hardware.
Function: every output traced to the load it drives, and every timing or current-setting value recomputed from the datasheet formula.
Required parts: decoupling and bulk capacitors at the datasheet values, not just present.
Connectors: pinout against the cable or module, including unused contacts such as a USB ID pin.
Parts list: every part number matches its value and its land pattern.

Layout

Antennas at the board edge with their keepout clear of copper on every layer.
Connectors on the edge, facing out, with room for the plug.
Decoupling capacitors next to the pins they serve; differential pairs routed together.
Design-rule check against your fab's rules, then the Gerbers opened in a viewer.

Can a chat assistant do the review?

A general chat assistant is a good second pair of eyes on a schematic image or a netlist: it will spot a missing pull-up, a capacitor without a ground, or a part used outside its typical circuit, and it explains datasheet details well. It is not a checker. It cannot measure a clearance, it does not trace every pin, and as above, it can report different error counts for the same board on different runs. That is why Review my design gets its numbers from the checkers and uses AI only to explain and fix.

If you use one, ask narrow questions you can verify, not "is this correct?". Give it the netlist and the datasheet's pin table and ask "which net drives EN, and what else is on it?". Then check the answer against the datasheet yourself.

Where it lands

The relationship isn't settling because AI got perfect at electronics. It is settling because nobody needs it to be. The AI drafts and edits, the checks measure and give the same answer every run, and you decide whether the board is the one you meant. That last job is still the one that decides whether the board works, and it is the one the checklist above is for.

The full guide, with the review result and the checklist, is at pcbeditor.com/ai-pcb-review.

PCB Builder: Three Ways to Start a Circuit Board in the Browser, and What It Won't Do for You

Dibyaprakash Pradhan — Sat, 31 Oct 2026 17:34:56 +0000

"PCB builder" is what most people type before they know the word EDA: they want to build a circuit board in the browser and export files a manufacturer will accept. I work on PCBEditor, one of the tools that does this, so the examples are real boards from it, mistakes included.

Short answer: an online PCB builder takes you from an idea to manufacturing files with nothing to install. You describe the board or draw the circuit; it places the parts, routes the copper and checks the design rules; you export Gerber, drill, pick-and-place and BOM files and upload them to a fab. You don't need to know PCB design to use one; you do need to know what your circuit should do.

Three ways to start

Describe what the board should do. Write the requirement in plain language, a sensor node, a motor driver, a power supply, and get a schematic, a placed board and routed copper to review and change. Fastest if you know the function but not the parts. Put the numbers in. The board in this post started as:

I2C OLED display board: a 0.96 inch 128x64 SSD1306 OLED module on a 4-pin header (GND, VCC, SCL, SDA), driven by an ATtiny85 over I2C with 4.7k pull-ups, a 6-pin ISP programming header, one push button, powered from 5 V USB micro-B. 2-layer board.

Draw the circuit yourself. Place components and wire them up directly. Everything you draw feeds the same board generation, so a hand-drawn schematic is a real input rather than a separate mode you get stuck in.

Start from files you already have. Import Gerbers to view, measure and modify an existing board. Useful when you are working from something a previous engineer left behind.

What goes into a finished board

If you have not built one before, these are the stages a board passes through. The builder handles all of them, and you can intervene at any point rather than accepting what comes out.

Schematic. What connects to what. Every board starts here, whether you wrote it or generated it.
Footprints. The physical pad geometry each part needs. Taken from a standards-based library where one exists rather than invented.
Placement. Where parts sit. Thermal, connector position and signal length all matter, and a bad placement cannot be rescued by routing.
Routing. The copper between pads, across as many layers as the board needs.
Design rules. Clearances, widths, annular rings and drill sizes checked against what a fab can actually make.
Manufacturing files. Gerber, Excellon drill, pick-and-place and BOM: the package a fab needs to quote and build.

The ATtiny85 OLED board after two chat edits: SCL on PB2, the USB micro-B powering the board, the ISP header complete. 10 parts on 31.5 × 26.7 mm.

What the builder got wrong on that board

The first version of the OLED board came back placed and routed, and it could not have worked:

SCL was on PB1. The ATtiny85's I2C hardware needs SCL on PB2.
The USB connector was not wired. Nothing powered the board.
A second 4-pin header duplicated the OLED socket.

One chat edit fixed all three, but it took MISO off the ISP header, and a second edit put it back. A routed board is not a working board, and after every change you re-check the whole board, not only the part you asked about.

Do I need to know PCB design already?

No, though you will get more out of it if you understand your circuit. The builder makes the mechanical decisions (footprints, placement, routing, clearances) and explains what it did, so a first board is achievable without learning a desktop tool first.

What it will not do is design a circuit you cannot describe. If you are unsure what the board should contain, start with a similar reference design and change it.

What it cannot judge for you is whether the circuit matches the datasheets. Before you order, check power on every chip, and that pins with a special job (I2C, USB, programming, reset) sit on pins that have that hardware.

Can I get it manufactured?

Yes. Exports are standard Gerber X2, Excellon drill, pick-and-place and BOM, the same files any fab expects, with presets for JLCPCB, PCBWay and OSH Park so board constraints match the process before you order. Nothing is paywalled behind an export.

One export dialog for every fab format: Gerber X2, Excellon drill, pick-and-place (CPL), BOM, IPC-D-356, IPC-2581, ODB++, assembly and fabrication PDFs, a STEP model and a KiCad board, in one zip.

The export includes a KiCad board too, so a board can start in the browser and be finished in KiCad.

The page this post is based on is at pcbeditor.com/pcb-builder. It is free to start, and you don't need an account to open the editor. The full walk from schematic to the first power-up is in How to Make a PCB: Ten Steps, Shown on Real Boards.

What did your first board get wrong? In our six-board test, four boards passed every automated check with a circuit mistake still in them, so I'd like to know which mistakes made it all the way to real boards.

How to Make a PCB: Ten Steps, Shown on Real Boards (Mistakes Left In)

Dibyaprakash Pradhan — Wed, 28 Oct 2026 20:10:58 +0000

Making a printed circuit board takes ten steps: write down the circuit, draw it, check it, give every part a footprint, lay out the board, route it, check it again, export the files, order, and assemble. Each step below is shown on a real board generated in PCBEditor (the browser PCB tool I work on). The mistakes are left in, because seeing a mistake once is the fastest way to stop making it.

Short answer: to make a PCB, draw the circuit as a schematic and give each part a footprint (its pad layout). Then place the parts on a board outline, connect them with copper traces and run a design-rule check. Export the Gerber and drill files, check them in a viewer, and upload the zip to a PCB manufacturer, which makes the bare boards in a few days. Then solder the parts on, or order assembly with a parts list and a pick-and-place file. All of the design steps can be done free in a browser.

1. Write down what the board must do

Before drawing anything, write one paragraph: what the board does, what powers it (USB, a battery, a 12 V adapter) and how much current it draws, the main parts by part number, the connectors, and the size it must fit. Every number you leave out gets decided for you later, by you or by a tool, often badly. This paragraph is also exactly what an AI PCB tool needs as a prompt. The board in the next two steps started as this one:

Single-cell LiPo charger board: USB-C 5 V input, MCP73831 charger set to 500 mA, a charge status LED, a JST-PH 2-pin battery connector, and an AP2112K 3.3 V regulator output on a 3-pin header. 2-layer board.

2. Draw the schematic

The schematic is the circuit as a diagram: every part as a symbol, every connection as a wire or a shared net name. Draw it in a circuit diagram maker or an EDA tool, or describe it and let the AI draw a first version. If the symbols are new to you, the schematic symbols chart covers the common ones.

The generated schematic of the LiPo charger: USB-C input with 5.1 kΩ CC pull-downs, the MCP73831 with 2 kΩ on PROG (500 mA) and its charge LED on STAT, and the AP2112K 3.3 V regulator fed from the battery, out to a 3-pin header.

3. Check it against the datasheets

A schematic can be tidy and still wrong. Before any layout, check the parts that decide whether the board works:

Power from the connector to every chip, and every supply against every part's absolute maximum rating.
Reset, boot and enable pins, each with the pull-up or pull-down and capacitor the datasheet asks for.
Special-function pins (I²C, SPI, UART, USB, ADC, crystal, programming header) on pins that have that hardware.
Decoupling capacitors at the values the datasheet gives, one per supply pin.

This is where most mistakes hide. In our six-board test, four boards passed every automated check with a schematic mistake still in them: a reset button on a spare GPIO, an LED that could never flash. The whole review is in I Asked an AI to Design Six PCBs.

4. Give every part a footprint

A footprint is the pattern of copper pads the part is soldered to, plus its outline and courtyard (the keep-clear area around it). It must match the exact package you will buy: a resistor in 0603 and one in 0805 are the same symbol on two different footprints. Most parts have one in the KiCad libraries. For the rest, build one from the datasheet's land pattern with a footprint generator.

Pin 1 on the symbol must be pad 1 on the footprint. Transistors and regulators come in several pin orders in the same package. A footprint that fits the package but numbers its pads differently from the symbol gives you a board that cannot work, and no design-rule check will notice.

5. Set the outline, layers and rules

Draw the board outline, choose the layer count (two is enough for most boards) and enter the design rules your manufacturer can build: minimum trace width and spacing, minimum drill and via size, copper-to-edge distance. Then size the traces that carry real current; the trace width calculator gives the width for a current and a temperature rise.

6. Place the parts

Placement decides most of how a board performs. Put connectors on the edges, facing out. Put decoupling capacitors next to the pins they serve, and keep a radio module's antenna at the board edge with no copper under it. Then place the rest to keep the important connections short. The ESP32 board below passed every rule check in its first layout and still had its antenna over a ground pour. A review caught it, and one move fixed it.

The first layout: the module in the middle, with its antenna end (above the top row of pads) over R1, the regulator and a ground pour that covers the whole bottom layer. It passed DRC. The review caught it.

After the move: 21 parts on 32.6 × 44.1 mm, two layers, every net routed, 0 DRC errors. The module sits on the top edge so its antenna overhangs the board.

7. Route the traces

Routing turns each connection into copper. Route power first and wide, then the sensitive signals (crystal, USB pair, analog inputs) short and direct, then everything else. Fill the spare area with a ground pour. An autorouter does the bulk well once placement is good. Check what it did with critical signals, though.

The LiPo charger routed on two layers: 14 parts on 32.5 × 34.5 mm, USB-C on the top edge, the battery connector bottom left and the 3.3 V output header bottom right.

8. Run the design-rule check and a review

The design-rule check (DRC) compares the copper against your manufacturer's limits: clearances, widths, drills, unrouted connections, overlapping parts. Fix every error. Then review what DRC cannot see: the circuit, the connector orientation, the antenna keep-out.

The design-rule check on a motor driver board: 0 errors and 1 warning (a courtyard overlap), with the board's net classes, trace widths and clearances in the panel on the right.

A clean DRC is where the review starts, not where it ends. The first version of that motor driver board had zero DRC errors and the Arduino Nano's VIN pin unconnected, so the board went dark the moment the USB cable came out. DRC checks the copper against the netlist; it can't tell that the netlist is missing a connection.

9. Export and check the Gerbers

Export the Gerber files (one per layer) and the drill files, usually as one zip. If you want the boards assembled, also export the BOM and the pick-and-place file. Before uploading, open the zip in a Gerber viewer and look at each layer. It is the file the fab will build from, and the place where a missing outline or holes off the pads show up.

One export for every fab format: Gerber X2, Excellon drill, pick-and-place (CPL), BOM, IPC-D-356, IPC-2581, ODB++, assembly and fabrication PDFs, a STEP model and a KiCad board, in one zip.

10. Order, assemble and power up

Upload the zip to a PCB manufacturer and pick the options. The standard ones suit most boards: FR-4, 1.6 mm thick, 1 oz copper, HASL or ENIG finish, green solder mask. Budget prototype services usually make a minimum of five boards. For assembly, the same services can solder the parts from your BOM and pick-and-place file, or you solder them yourself, smallest parts first.

The first power-up:

Inspect the board under good light for solder bridges, especially on fine-pitch chips.
With a multimeter, check that no supply rail is shorted to ground.
Power it from a bench supply with a low current limit, not straight from a battery or adapter.
Measure each rail before you plug in modules or programme the microcontroller.

The assembled charger in the 3D view: USB-C receptacle, JST-PH battery connector, the 3-pin output header, and the charger and regulator between them.

Making a PCB at home

Simple boards can be made at home. Transfer the copper layout onto copper-clad board, with laser-printer toner ironed on or a photoresist film, etch away the bare copper in ferric chloride or a similar etchant, and drill the holes. It works for single-sided and simple double-sided boards with wide traces. You get no solder mask, no silkscreen and no plated holes, and the etchant stains, corrodes and must be disposed of properly. Ordered prototypes are now cheap and fast enough that most people etch only when they need a board the same day.

How many layers, and which software?

Two layers are enough for most hobby and small product boards, including microcontroller boards with USB. Four layers help with dense parts such as fine-pitch QFN or BGA chips, high-speed signals and boards that need a solid ground plane under every signal.

For software, any PCB design (EDA) tool will do: KiCad is free and runs on the desktop; PCBEditor runs in the browser and can also generate a first draft from a description. Both export the Gerber, drill and assembly files a fab needs.

The full guide, with every step and the figures at full size, is at pcbeditor.com/how-to-make-a-pcb.

What was the mistake on your first board? Of the six test boards, the one that taught me most was the ESP32: a clean design-rule check, and an antenna sitting over a ground pour.

Schematic Symbols for Beginners: Every Common One, Drawn by KiCad

Dibyaprakash Pradhan — Tue, 27 Oct 2026 06:41:34 +0000

Most symbol charts online are redrawn by hand, and a few get the details wrong. Every chart below is a real schematic sheet instead: KiCad 9 plotted it from its own symbol libraries, unchanged. Under each symbol is its common name and the name to search for in KiCad. The notes cover what actually trips people up when they read or draw a schematic: which end is which, what the arrows mean, and which pin is which.

Short answer: a schematic symbol is the drawing that stands for one part in a circuit diagram. A resistor is a box (IEC) or a zigzag (ANSI), a capacitor two plates, a diode a triangle against a bar, and a transistor a circle with an arrow on one lead. Each symbol carries a reference designator: a letter for the kind of part (R resistor, C capacitor, D diode, Q transistor, U chip) and a number. Its pins are numbered to match the pads of the part's footprint on the PCB.

Resistors

The plain resistor has two drawings: the IEC box and the ANSI zigzag. Both mean a fixed resistor and neither has a polarity. A diagonal arrow across the body means a variable resistor. A potentiometer has three pins, the two ends and the wiper, and KiCad numbers the wiper 2. A trimmer is a potentiometer you set once with a screwdriver, which is why its wiper ends in a flat bar rather than an arrow.

Three resistors respond to something other than current. In the NTC thermistor, the ϑ marks temperature and the two opposed arrows mean resistance falls as temperature rises (KiCad's PTC version draws both arrows pointing the same way). The photoresistor (LDR) has light arrows pointing in. The varistor (MOV) clamps voltage spikes. Its bent diagonal stroke is the IEC mark for a resistance that changes non-linearly, and the U beside it says the change follows voltage.

Capacitors, inductors and crystals

A capacitor is two plates. If one is marked +, the capacitor is polarized (electrolytic or tantalum) and must be fitted the right way round. In the ANSI drawing the curved plate is the negative one. An inductor is a row of loops; two straight lines alongside mean an iron core. A ferrite bead, which filters high-frequency noise off a supply line, is a small block drawn across the wire.

The transformer is two windings either side of a core. In KiCad's symbol the primary is pins 1 and 2 and the secondary 3 and 4. A crystal is a quartz block between two plates; the crystal for a microcontroller's clock usually sits beside it with a small capacitor from each pin to ground.

Diodes and LEDs

Every diode is a triangle pointing at a bar. Current flows the way the triangle points, from anode to cathode, and the bar is the cathode: the same end as the band printed on the part. The bar's ends tell you the type: bent ends for a Zener, which holds a fixed reverse voltage, and S-shaped hooks for a Schottky, which drops less voltage forward. KiCad's D_TVS draws a bidirectional TVS (two diodes back to back) for clamping spikes either way.

Arrows leaving the symbol mean light out (an LED). Arrows entering mean light in (a photodiode).

The classic mistake: an LED drawn backwards does not light. The cathode bar must face the lower voltage for an LED or a rectifier, and the higher voltage for a Zener or TVS doing its job. Check the footprint's cathode mark against the symbol before you order boards.

Transistors and MOSFETs

A bipolar transistor has a base, a collector and an emitter. The arrow is on the emitter and shows conventional current: out for NPN, in for PNP. A MOSFET has a gate, a drain and a source. KiCad's MOSFET symbols draw the channel, the arrow (pointing in for N-channel, out for P-channel) and the body diode that almost every power MOSFET has between source and drain. A phototransistor has no base pin, because light drives it.

Same symbol, different pin order. The symbol never tells you the package's pin order. SOT-23 MOSFETs are commonly gate 1, source 2, drain 3, and small SOT-23 bipolar transistors base 1, emitter 2, collector 3, but other parts in the same package differ. Check that the symbol's pin numbers match the footprint's pads for the exact part number.

Ground, power and batteries

Ground and supply symbols are not parts: each one is a net name. Every GND symbol on a sheet is the same net, so you rarely draw a ground wire across the page. GNDA (analog ground) looks the same but is a separate net, which is the point: analog and digital grounds stay apart until you join them in one place on purpose. Earth (three shrinking bars) and protective earth (the circled version) are for mains-connected equipment. Supply rails such as +5V and VCC work the same way as ground: the name is the net.

A battery cell is a long thin plate (positive) and a short thick one (negative). Several cells drawn in a stack mean a multi-cell battery.

Switches, relays and fuses

A push button closes only while it is pressed. An SPST switch (single pole, single throw) is a plain on–off switch. An SPDT switch connects its common, pin 2 in KiCad's symbol, to one of two outputs. A relay is a coil and a switch drawn in one box, with a dashed line showing the coil moves the contact. Relays use standard numbers: the coil is A1–A2, the common contact 11, normally closed 12 and normally open 14.

A fuse is a box with the wire running through it. The resettable fuse (polyfuse, a PTC that resets when it cools) adds the same bent stroke as the varistor: a part whose resistance changes non-linearly, here sharply as it heats.

Motors, speakers, lamps and antennas

A motor is an M in a circle; a DC motor marks its + pin, which sets the direction it turns. A speaker is a small box with a cone. A buzzer is a half-disc whose + pin matters for the self-oscillating kind. A microphone is a circle with a bar on one side, a lamp a circle with a cross, and an antenna a short fork.

Logic gates and op amps

These are the ANSI (distinctive-shape) symbols: a flat-backed D for AND, a curved shield for OR, a triangle for NOT, and an extra curved line for XOR. A small circle on an output inverts it, which turns AND into NAND and OR into NOR. KiCad draws each one here as a real single-gate chip from the 74LVC1G family, so you can also see the supply pins (VCC on pin 5, GND on pin 3). The IEC style draws every gate as a rectangle with a label inside instead: & for AND, ≥1 for OR, 1 for a buffer or inverter, =1 for XOR.

An op amp is a triangle with two inputs: + is non-inverting, − is inverting.

The letters: reference designators

Every symbol gets a reference designator, and the same designator is printed on the board next to the part, so R7 on the schematic is R7 on the silkscreen. The ones KiCad's libraries use, most of them following IEEE 315 and ASME Y14.44 practice:

Letter	Part	Letter	Part
R	Resistor	Q	Transistor
RV	Potentiometer, trimmer, varistor	U	Chip, logic gate, op amp
C	Capacitor	J	Connector
L	Inductor	SW	Switch
D	Diode, LED	K	Relay
Y	Crystal	F	Fuse
T	Transformer	BT	Battery

IEC or ANSI?

Two standards cover most schematics. IEC 60617, common in Europe and Asia, draws a resistor as a box, and logic gates as labelled rectangles. ANSI/IEEE 315, common in North America, draws a resistor as a zigzag and logic gates with distinctive shapes. Capacitors, diodes and transistors look much the same in both. Neither style is more correct, but mixing them on one sheet confuses readers, so pick one per project. In KiCad the IEC resistor is R, the ANSI one R_US.

How the symbols connect

A dot is a connection. Wires that meet at a dot are joined. Wires that cross without a dot are not.
Names connect too. Two wires with the same net label, or two power symbols with the same name, are one net even if no line joins them.
An X on a pin means not connected on purpose, so the electrical rule check does not report it.
Pin numbers become pads. When the schematic becomes a board, pin 1 of a symbol connects to pad 1 of its footprint. A mismatch there is the most expensive mistake a correct-looking schematic can hide.

The full chart, with the rest of the reference designators and the sources, is at pcbeditor.com/schematic-symbols. If you want to draw your own next, the circuit diagram maker runs in the browser.

Chart images are rendered from the KiCad symbol libraries and, like the libraries, are shared under CC BY-SA 4.0.

Which symbol confused you most when you started? For me it was ground: three different-looking symbols, and it took a while to learn that the name, not the drawing, is what connects them.

I gave Claude a PCB design tool over MCP: here is what it built

Dibyaprakash Pradhan — Sat, 24 Oct 2026 14:24:39 +0000

I build PCBEditor, a browser PCB tool that designs boards from a description, so read this with that in mind. We have just put an MCP server in front of it, and before writing any docs I wanted to see what an AI assistant actually does with it when nobody is steering. So on 20 October I connected Claude Code to the server, typed one sentence, and let it run without me. The step-by-step version, with every tool and the responses it returns, is at pcbeditor.com/mcp/guide.

The setup

One command adds the server:

claude mcp add --transport http pcbeditor https://api.robodib.com/mcp

Claude Code then sees 16 tools: design_board, get_job, answer_question, edit_board, route_board, run_drc, review_board, get_board, export_board, import_kicad and a few for parts and designs. A design runs as a job on the server: design_board returns a job ID, and get_job waits up to 45 seconds per call for it to move.

What I typed:

Design a 4-layer ESP32-S3 board with USB-C and a LiPo charger.

Claude wrote a spec first

It did not pass my sentence through. Its first design_board call carried a full specification it had written itself. An excerpt:

Charging: single-cell LiPo charger with power path / load sharing so the board runs from USB while charging and from the battery when unplugged (e.g. TI BQ24074, or MCP73831 plus a P-MOSFET and Schottky load-sharing circuit). Charge current about 500 mA, set by resistor. [...] 3.3V rail: low-dropout regulator rated at least 600 mA with low quiescent current (e.g. AP2112K-3.3 or RT9080/ME6211 class) fed from the power-path output

It also asked for ESD protection on the USB lines, a battery-voltage divider to an ADC pin, an RC delay on the enable button, two header rows and a 4-layer stack with a solid ground plane, and it switched on the slower extra quality pass. That is a better brief than most people write, and better than mine.

Then our server tripped five times

The first job ended after 44 seconds with "The run ended without a board." So did the next four. The progress lines showed why: the pipeline had found problems in the circuit and was "Awaiting your choice on the circuit problems before layout...", but that choice never reached Claude as a question. That is a bug in our MCP layer, and it is on our list.

Claude's reaction was the interesting part. It looked up the pin maps of the module and the charger with get_part, rewrote the description naming each charger and USB pin by its library name, and tried again. On the sixth run the question came through:

The circuit cannot work as wired: [...] U2 (LiPo charger with power path) pin 4 (~{CE}) is held high (net VBUS), which keeps U2 shut down: it runs with this pin low; U2 (LiPo charger with power path) pin 6 (EN1) is held low (net GND), which keeps U2 shut down: it runs with this pin high. How should I continue?

Claude answered in its own words with a list of corrections. The server ignored the free text and asked the same question again (bug number two), so Claude picked "Build it with these circuit problems listed" and said it would fix the problems with edits afterwards. The job finished at the 113-second mark: 36 parts, 708 traces, 134 vias, four layers.

Claude read the netlist

Here is where it earned its keep. It called get_board with detail: full, which returns every net with the pads it connects, and compared it with what a BQ24074 power-path charger needs. It found three mistakes that our design-rule check had passed, because they are not copper problems:

The ESP32-S3 module's 3V3 pin was on its own net, fed through a 1 kΩ resistor (R12) from the 3.3 V rail. In Claude's words, "it would brown out immediately."
The charger's temperature-sense pin was pulled up to 3V3 through 10 kΩ, which Claude said "would block charging."
The charger's input-current-limit pin (ILIM) sat on the not-connected net.

I checked all three against the board data it read. They were real.

It also disagreed with one of our checks. The question had said EN1 low "keeps U2 shut down." Claude pointed out that with EN2 high and EN1 low, the BQ24074 takes its input current limit from the ILIM resistor, which is what the design intends, and that setting EN1 high would put the charger in suspend. That matches the EN1/EN2 table in TI's datasheet. Our check was wrong, and Claude kept the pins as they were.

The fixes went in as precise edit_board instructions, pad by pad:

Re-net these pads exactly (pad -> net), then re-route affected nets:

U1.2 -> 3V3 (module supply pin must be directly on the 3V3 rail). Net U1_3V3 is removed.

The server applied them and rerouted: "pins re-netted: U1.2 → 3V3, U1.4 → SIG_IO4, U2.7 → GPIO2, U2.12 → U2_ILIM, R4.1 → U2_ILIM, R4.2 → GND and 8 more." A second pass wired the header pins the first build had left on the not-connected net. Then it asked review_board to check the charger wiring pin by pin. The review's AI-written part was the least reliable thing in the session: it called the 12 Mbps USB link 480 Mbps and said the charger's exposed pad had no thermal vias, and when Claude asked for four, the server answered that all four were already there.

The board after Claude's fixes, opened in PCBEditor's editor: 35 parts on 73.8 × 54.6 mm, four layers, every net routed. Claude's last edit request is in the chat panel on the right.

Where it stopped

Two design-rule errors would not go away: inner-layer traces passing 0.151 and 0.156 mm from the USB-C connector's shield holes, where the rule is 0.25 mm. Claude tried several edits. Our edit guard threw one away because it "would take DRC errors from 2 to 4". Another came back with "Nothing changed on the board". After the third, Claude stopped and told me:

Two DRC errors remain that the tool wouldn't fix after three attempts, so I haven't exported any fab files.

That is exactly what I want an agent to do with a board that is not ready. export_board would have refused anyway: it will not hand out fab files while there are DRC errors the user has not accepted. But Claude did not try to accept them on my behalf.

Its summary also listed the board size, 73.8 × 54.6 mm against the 60 × 30 mm it had asked for, the loosely coupled USB pair, and a note to check the polarity of my JST battery lead before plugging it in. The whole session took about 18 minutes: 6 design jobs, 9 edits, 25 waits on get_job, and a board I could open in the browser and fix in a few minutes by hand.

What I took away

The split works. Claude was good at the things a language model is good at: writing a brief, reading a netlist against what a datasheet expects, writing exact change requests, and knowing when to stop. The server did the things it should not do: wiring from pin maps, routing, measuring clearances.

Checks pass wrong boards. All three wiring mistakes passed the design-rule check, because DRC measures copper, not intent. The first design_board result even said the board was DRC-clean while the saved board had two errors. If your agent does not read the netlist, you have to.

Our MCP layer has gaps. Circuit-problem stops that do not arrive as questions, free-text answers that are ignored, a check that misread the BQ24074's enable pins, a "DRC-clean" message on a board with two errors, a board larger than asked for. All of these are now on the list, found in one afternoon by letting an agent use the product the way it wanted to.

An agent that refuses to export is a feature. I would rather get "not ready, here is why" than a zip.

If you want to try the same thing, the guide walks through connecting Claude, ChatGPT or Gemini, the first prompt, answering the designer's questions, checking, editing and exporting, with the responses you should expect: pcbeditor.com/mcp/guide.

How Wide Does a PCB Trace Need to Be for 1 A, 2 A, 3 A or 5 A?

Dibyaprakash Pradhan — Tue, 20 Oct 2026 12:11:32 +0000

The usual answer is a table, and most tables are the same IPC-2221 formula at different settings. That's a fine starting point for an outer-layer trace on an ordinary board. It's too generous for some boards, far too cautious for internal layers, and it says nothing about voltage drop, which is often the limit that bites first.

Short answer: on 1 oz copper on an outer layer, allowing a 10 °C rise, about 0.30 mm (12 mil) for 1 A, 0.78 mm (31 mil) for 2 A, 1.37 mm (54 mil) for 3 A and 2.77 mm (109 mil) for 5 A. Allow 20 °C and they shrink by about a third; use 2 oz copper and they halve. Then check the voltage drop: at 1 A, 100 mm of that 0.30 mm trace drops 175 mV.

The table

Width for a continuous current, from the IPC-2221 formula (I = k·ΔT^0.44·A^0.725, k = 0.048 outer, 0.024 internal). The first three columns are outer layers, the last is an internal layer.

Current	1 oz outer, 10 °C	1 oz outer, 20 °C	2 oz outer, 10 °C	1 oz internal, 10 °C
0.5 A	0.12 mm (5 mil)	0.08 mm (3 mil)	0.06 mm (2 mil)	0.30 mm (12 mil)
1 A	0.30 mm (12 mil)	0.20 mm (8 mil)	0.15 mm (6 mil)	0.78 mm (31 mil)
2 A	0.78 mm (31 mil)	0.51 mm (20 mil)	0.39 mm (15 mil)	2.03 mm (80 mil)
3 A	1.37 mm (54 mil)	0.90 mm (35 mil)	0.68 mm (27 mil)	3.56 mm (140 mil)
5 A	2.77 mm (109 mil)	1.82 mm (71 mil)	1.38 mm (54 mil)	7.19 mm (283 mil)
10 A	7.19 mm (283 mil)	4.72 mm (186 mil)	3.60 mm (142 mil)	18.71 mm (737 mil)

A coupon board with one 40 mm outer-layer trace per current, each at the 1 oz, 10 °C width from the table, beside a 0.25 mm signal trace for scale. Built and rendered in KiCad 9; it passes KiCad's design-rule check.

Going from 1 A to 5 A takes the trace from barely wider than a signal trace to over 2.7 mm. At 10 A the 1 oz outer width passes 7 mm, which is the point to stop widening traces and use a copper pour, heavier copper, or both.

How to read it: rise, copper weight, layer

Temperature rise is how much hotter than its surroundings the trace may run. It's a choice, not a property of the board. 10 °C is the cautious default; 20 °C shrinks every width by about a third.

Copper weight is thickness: 1 oz is about 35 µm, 2 oz is twice that. Capacity follows cross-section, so 2 oz roughly halves the width. On budget fabs the outer layers are 1 oz unless you ask.

Layer is where IPC-2221 is most conservative. Its formula halves the constant for internal layers, which makes an internal trace about 2.6 times as wide as an outer one for the same current.

What IPC-2152 changed

IPC-2221's external chart comes from US National Bureau of Standards tests in the 1950s, and its internal chart was never tested: it was derived from the external one. IPC-2152, published in 2009, replaced both with new measurements, and two findings matter for everyday boards.

First, internal traces aren't the poor relations IPC-2221 makes them: in the new tests internal and external traces carrying the same current ran at close to the same temperature rise, internal ones slightly cooler, so the 2.6× internal penalty is mostly margin. Second, the trace is only part of the story. Board thickness and copper planes near the trace change the temperature rise as much as the width does, which is why IPC-2152 gives a baseline chart (3 oz copper, still air, no planes) plus modifiers for copper weight, planes, board thickness and environment.

In practice: the IPC-2221 table is a safe outer-layer answer for a board in open air. Over or beside a solid plane, a trace runs cooler than the table says. In a sealed box, it runs hotter.

Wide enough for heat is not wide enough for voltage

The width tables size a trace so it doesn't get too hot. They don't look at how much voltage it loses on the way. Here's 100 mm of each heat-sized trace from the first column, with the copper at 35 °C:

Current	Width	Resistance	Voltage drop	Heat in the trace
1 A	0.30 mm	175 mΩ	175 mV	175 mW
2 A	0.78 mm	67 mΩ	135 mV	269 mW
3 A	1.37 mm	38 mΩ	115 mV	345 mW
5 A	2.77 mm	19 mΩ	95 mV	473 mW

175 mV is about 5% of a 3.3 V rail, gone before the current reaches the load. For a supply that feeds a regulator that may not matter; for the rail a microcontroller or sensor runs from, it often does. Widen the trace, or bring the load closer, until the drop is small enough.

And the ground path carries the same current back. A wide supply trace with a thin ground return, or a ground pour cut into islands, just moves the drop to the other side of the circuit.

When the table is wrong

Short necks are fine. Thermal modelling by Brooks and Adam shows a trace that narrows for a few millimetres to enter a pad runs cooler than a long trace of that width, because the wide copper on each side draws heat away. The benefit shrinks as the neck gets longer; the table is for long runs.
Pulsed and switching currents heat a trace by their RMS value, not their peak. A motor that draws 5 A at start-up for half a second doesn't need a 5 A continuous trace, but a regulator's switching loop needs a short, wide path for reasons that have nothing to do with heat.
Vias are the bottleneck. A power path that changes layer through one small via is limited by that via, not the trace. Use several.
Enclosures and hot neighbours raise the starting temperature. A 10 °C rise on a board already at 60 °C beside a regulator is a 70 °C trace.
Above about 10 A on 1 oz copper, the widths stop being practical traces. Use a pour, heavier copper on the power layers, or a bus bar.

Doing it for your own numbers

Every number above comes from the same code as PCBEditor's free trace width calculator and trace resistance calculator, so you can plug in your own current, copper, rise and length and get the same answers. In PCBEditor itself, stating a current in the description ("the motor rail carries 3 A") sizes that power net with the same IPC-2221 formula at a 10 °C rise; past 6 mm it lays 6 mm and tells you to use a pour, 2 oz copper or a bus bar instead. The full guide is on pcbeditor.com.

Which do you size by first, heat or voltage drop? I'd like to know how often the drop is what actually sets your power trace widths.

I Asked an AI to Design Six PCBs. Here's What a Pin-by-Pin Review Found.

Dibyaprakash Pradhan — Mon, 19 Oct 2026 07:14:10 +0000

"AI PCB design" demos tend to stop at a nice render. I wanted to know what happens after it: does the board actually work? So on 17 October 2026 I typed six one-paragraph prompts into PCBEditor (the browser EDA tool I work on), let it generate each board end to end, and then reviewed every one the boring way: exported KiCad board, BOM and datasheets side by side, pin by pin.

Short version: five of the six finished fully routed with zero DRC errors and exported Gerbers. Only one of those five was right the first time. The sixth, a 4-layer RP2040 board, didn't finish routing at all.

Update, 19 October: I re-ran the same six prompts on the next release. Four of the six came out right the first time. The results are near the end.

The six prompts

Each was one paragraph, with the parts and numbers I cared about spelled out. Here's the LiPo charger's, word for word:

Single-cell LiPo charger board: USB-C 5 V input, MCP73831 charger set to 500 mA, a charge status LED, a JST-PH 2-pin battery connector, and an AP2112K 3.3 V regulator output on a 3-pin header. 2-layer board.

The others: an ESP32-C3-MINI-1 board with a BME280 over I²C, USB-C, an LDO, a status LED and reset/boot buttons; an NE555 flasher alternating two LEDs at about 1 Hz from a 9 V battery; an Arduino Nano socket driving two DC motors through a DRV8833; an RP2040 with QSPI flash, a 12 MHz crystal and two 20-pin headers on four layers; and an ATtiny85 driving an SSD1306 OLED, with an ISP header and USB micro-B power.

A run takes a few minutes and goes through part research, netlist, placement, routing and a DRC pass, with a log of what it decided at each stage.

The LiPo charger, the one board that was right as generated: 2 kΩ on PROG for 500 mA, the charge LED on STAT, the regulator fed from the battery, 5.1 kΩ on both CC pins.

What the review found

None of these would have been caught by a design-rule check. All four boards passed one.

ESP32-C3: the reset button wasn't a reset button. I asked for "reset and boot buttons". BOOT was right, on GPIO9. "Reset" came out as a user button on GPIO4, with nothing on EN except its pull-up and capacitor. The planner read "reset button" as "a button".

555 flasher: one LED could never flash. The 555 itself was wired correctly (TRIG and THR tied, DIS between the timing resistors, RESET high). But the second LED had its cathode on ground and its resistor to 9 V, so it was simply always on. The timing was also off: 10 kΩ, 100 kΩ and 10 µF give 1.44 / (210 kΩ × 10 µF) = 0.69 Hz, not "about 1 Hz".

Nano motor driver: the Nano had no power. The prompt said "the Nano powered from the motor supply through its VIN pin". The VIN contact on the socket was unconnected, and the board's 5 V net hung off the Nano's +5V pin, which nothing on the board fed. Unplug the USB cable and the whole thing goes dark. The DRV8833 side was textbook, except VINT had 1 µF where the datasheet asks for 2.2 µF.

ATtiny85 OLED: wrong clock pin, no power, a duplicate header. The ATtiny85's I²C hardware (USI) uses PB0 for SDA and PB2 for SCL. SCL landed on PB1 and the push button on PB2. The USB micro-B connector was on the board but not wired to anything, and a second 4-pin header duplicated the OLED socket.

And one that wasn't the AI's mistake but it didn't catch: I asked for a 6-12 V motor supply on a DRV8833, which is rated for 10.8 V on VM (11.8 V absolute max). Nothing flagged it. That's on me as the designer, and it's exactly the kind of thing a tool should warn about.

Fixing by chat

Every fix was one plain-English message that named pins. For the 555:

D2 never flashes: its cathode is on GND, so it is always on. Connect D2's cathode to the 555 output (U1 pin 3, net LED1_CTL) instead of GND, keeping R4 from 9V to D2's anode. Also change R2 from 100k to 68k so the rate is about 1 Hz. Then reroute.

The editor rewired only the three affected nets and kept the other 58 traces where they were. 68 kΩ gives 1.44 / (146 kΩ × 10 µF) = 0.99 Hz. A second message added the 10 nF on pin 5.

The fix request on the right, with the edit log underneath: "Detecting D2 cathode tied to GND", then a reroute of only the nets that changed.

The lesson I didn't expect: re-check after every edit. On the ATtiny85 board, the message that moved SCL to PB2 and the button to PB3 also dragged the ISP header's MISO contact along with the button net, so the chip could no longer be programmed. It took a second message to put MISO back on PB1. The edit did what I asked; it also did something I didn't.

A layout problem the netlist can't show

The ESP32-C3 board had a correct netlist and a clean DRC, and a bad layout. The ESP32-C3-MINI-1's PCB antenna is the end of the module beyond its top row of pads, and Espressif wants it at the board edge with no copper underneath. The first layout put the module in the middle of the board, antenna over a resistor, the regulator and a ground pour covering the whole bottom layer.

Before: module mid-board, antenna end over parts and the bottom-layer ground pour. DRC: clean.

One message ("move U1 to the top board edge with the antenna end facing out, no copper under it") fixed it. The root cause was in the footprint data: its courtyard covered only the pad field, not the antenna, so placement treated the antenna as free board. That's been reported.

After: the antenna overhangs the top edge. 21 parts, 32.6 × 44.1 mm, two layers, all nets routed.

The one that failed

The RP2040 board was the stress test: a 7 × 7 mm QFN-56 at 0.4 mm pitch, QSPI flash, crystal, USB-C, a regulator and two 20-pin headers on four layers. Where it was wired, it was right: SD0-SD3 mapped correctly to the W25Q16, BOOTSEL through 1 kΩ on the flash chip-select like the Pico, 27 Ω USB series resistors. But:

GPIO26 to GPIO29 were left unconnected. The part check didn't recognise the RP2040's pin names GPIO26_ADC0 to GPIO29_ADC3 and concluded the chip has no GPIO26 to 29.
9 of 47 nets didn't route, and 2 DRC errors remained.
When I asked it to connect the four ADC pins, it refused the change rather than break existing routes, and the export held back the Gerbers.

Honestly, that's the behaviour I want from a tool when it can't do something: say so, name the nets, and don't hand me files that look finished.

Scorecard

Board	Parts	Chat edits	Result
LiPo charger	14	0	Routed, 0 DRC errors
ESP32-C3 sensor	21	2	Routed, 0 DRC errors
Nano motor driver	18	1	Routed, 0 DRC errors
ATtiny85 OLED	10	2	Routed, 0 DRC errors
555 flasher	11	2	Routed, 0 DRC errors
RP2040 (4-layer)	33	2, both refused or timed out	9 nets unrouted, 2 DRC errors

Re-run on the next release

The fixes for these went into PCBEditor 1.3.5. On 19 October I ran the same six prompts again, word for word, with no chat edits, and reviewed the exports the same way.

Board	17 October	19 October
LiPo charger	Right as generated	Right as generated
ESP32-C3 sensor	Reset button on GPIO4; antenna mid-board	Right as generated
555 flasher	One LED always on; 0.69 Hz	Right as generated
ATtiny85 OLED	SCL on PB1; USB not wired; duplicate header	Right as generated
Nano motor driver	Nano's VIN not wired	Nano's VIN still not wired
RP2040 (4-layer)	GPIO26-29 missing; 9 nets unrouted; 2 DRC errors	GPIO26-29 wired; 11 nets unrouted; 0 DRC errors

Four of six were right the first time, up from one. Checked against the datasheets:

ESP32-C3: the reset button is on EN, with the 10 kΩ pull-up and the capacitor, and BOOT is on GPIO9. The module sits at the top edge with a no-tracks, no-vias keep-out under the antenna.
555: the LEDs alternate. 10 kΩ, 68 kΩ and 10 µF give 0.99 Hz, and there's 10 nF on CONT.
ATtiny85: SDA is on PB0, SCL on PB2, the button on PB3 and MISO on PB1. The micro-B is wired (pin 1 to 5 V, pin 5 to GND, ID open), and there's only one OLED socket.
Nano: the DRV8833 now has 2.2 µF on VINT, and the run log caught the rating I'd missed: "U1 pin 12 (VM) is on VIN (11.6 V), above the 10.8 V recommended maximum". But the Nano's VIN contact was still unconnected, again with no message. It also added 1 kΩ pull-downs on the four driver inputs. They work, but they draw 5 mA from each Nano pin that's high, and the DRV8833 already has internal pull-downs.
RP2040: the part check now reads the GPIO26_ADC0 to GPIO29_ADC3 names. All four pins reach the header, along with GND, 3V3, VBUS, RESET and SWD. Routing is still the problem: 11 nets (13 connections) are unrouted on four layers. And this time the export didn't hold the Gerbers back. Open connections count as DRC warnings, not errors, and nothing in the exported files mentions them; only the run log does. The log also claimed there was no header contact left for GPIO26-29, which were already wired.

Two small mismatches remain. The 555's 10 nF control-pin capacitor sits on an electrolytic footprint. And the ATtiny85 board's BOM names a TE micro-B connector on a different maker's land pattern. Neither would stop the board working, but either would trip up an assembler.

So: better, and still not a replacement for the review. Every one of these turned up by working through the checklist below.

What I'd tell anyone trying AI PCB tools

Put the numbers in the prompt: part numbers, currents, frequencies, which pin does what. Anything you leave out gets decided for you.
Read the run log. It tells you what it left unconnected and why.
Review the schematic against the datasheets before you look at the copper. Power path, every reset/boot/enable strap, every special-function pin (I²C, ADC, USB, crystal, programming header), every rating against your supply.
Look at the layout for things DRC doesn't know about: antennas, connector orientation, decoupling distance.
After each chat edit, export and re-check, not just the pins you asked about.
Open the Gerbers in a viewer before you order.

The AI saved me the drafting on all six boards: parts lookup, symbols, footprints, placement, routing. It didn't save me the engineering. Every mistake above was found by reading a datasheet, and every fix was a sentence I wrote.

The full walkthrough, with the routed boards, 3D views, the DRC result and the export options, is at pcbeditor.com/ai-pcb-design.

Your Gerbers Passed the Upload Check. Here's What It Didn't Look At.

Dibyaprakash Pradhan — Sat, 17 Oct 2026 09:14:02 +0000

You upload a zip, the fab's page draws a board and shows a price. That proves one thing: their software could read your files. It can't prove the files describe the board you designed, because the files are all the fab has. A missing outline, holes that land beside their pads, a blank paste layer: all of them quote without complaint.

Before you pay, open the exact zip you're sending in a Gerber viewer and check seven things: the layer count, the board outline, the drill holes, the solder mask, the paste, the silkscreen and the board size. The two broken examples below came straight out of KiCad's own export, one checkbox each.

The reference: the zip KiCad 9 exported from a board that passes its design-rule check. The outline is yellow and the viewer measures 50.00 × 34.00 mm, which matches the design.

What an upload check can and can't tell you

A fab's upload step reads each file, works out which layer it is (from the X2 attributes KiCad writes, or from the file name), measures the board, counts holes and layers, and prices the job. Many fabs then review the files after you order and email questions if something looks odd. Both are useful. Neither knows what you meant, so neither can tell you that a layer is missing, that an outline should exist, or that the holes are 100 mm from where they should be.

1. Every layer you meant is in the zip

Count the copper layers first: a four-layer board needs four copper files, and a plot dialog with only the outer layers ticked produces a perfectly valid two-layer set. Then check each side that has solder mask and silkscreen has its own file, the outline is there, and there are drill files for plated and, if you have any, non-plated holes.

KiCad also writes a Gerber job file (.gbrjob) listing the layer count, thickness and every file's function. Some fabs read it. It's a list, not proof: the job file for the board in these pictures lists two paste layers, and both are empty (check 5).

2. The outline is there, closed, and drawn once

The outline (Edge.Cuts in KiCad, the profile in Gerber terms) is the only file that says where the board ends. Leave it out and every other layer still loads, which is why it's easy to miss.

The same export with Edge.Cuts unticked. Nothing looks wrong at a glance, but there's no board edge, and the only size anyone can measure is the copper's: 49.00 × 33.00 mm instead of 50 × 34.

Without it, the board size is a guess. The copper stops half a millimetre inside the edge, so a viewer reports 49 × 33 mm for a 50 × 34 mm board. A fab has the same problem and will either guess or ask, and asking costs a day.

An outline can also be present and still wrong. It must be closed (KiCad's design-rule check reports a malformed outline), drawn once, and include any cut-outs or slots as closed shapes inside it.

3. Every hole lands in its pad

Drill files are a separate format (Excellon) with their own origin and units. If the Gerbers and the drill file were written from different origins, the copper is right and the holes are somewhere else. In KiCad 9's own dialogs the two origins are one shared setting, so this happens when the files are exported separately: here kicad-cli plotted the Gerbers from the drill/place file origin and wrote the drill file in absolute coordinates, one flag each, as a script, an older KiCad or another tool can:

The board renders, but J1 and J2 have solid pads: their six holes, and the four vias, landed more than 100 mm away, off the board.

A smaller origin difference is worse, because the holes land partly in the pads and look almost right. Look at a through-hole part and at a via, and make sure the hole sits in the middle of the copper. While you're there, check mounting holes are in the non-plated file if they shouldn't be plated, and the tool sizes match the holes you designed.

4. The mask opens over every pad, and nowhere else

The solder mask file is a negative: what it draws is where the mask is removed. Turn on one side's copper and mask together and every pad should show an opening. Covered (tented) vias should have none; vias you want to probe should.

Gold is bare copper, where the mask opens: every pad has an opening. The four 0.3 mm vias stay covered, as this board's tenting setting asks.

On fine-pitch parts, look at the strip of mask between neighbouring pads. If it's thinner than your fab's minimum, it's dropped and the pads share one opening, which makes solder bridges more likely.

5. The paste layer isn't empty

Paste layers matter only if you order a stencil, and then they are the stencil: an opening on every SMD pad, none on through-hole pads. The board in these pictures has 27 SMD pads and empty paste files (we removed the paste to photograph bare copper). Both files are in the zip and both are listed in the job file, so a file count passes. Turn on the paste layers alone and there's nothing there, and a stencil cut from them would be a blank sheet of steel.

6. The silkscreen stays off the pads

Fabs clip silkscreen that falls on bare copper, so a designator printed across a pad comes back cut in half or missing. Check text is at least your fab's minimum height and line width, and that the bottom silkscreen reads mirrored when you look from the top. That's correct: you'll read it from underneath.

7. The size and stackup match the order form

The viewer's size readout should match your design, and the order form should match both: size, layer count, thickness and finish. A two-layer zip ordered as four layers, or a 1.6 mm design ordered at 0.8 mm, is a correct set of files and the wrong board.

Then check the design, not just the files

Everything above checks that the files say what the board file says. It doesn't check the board. Before you export, run your CAD tool's design-rule check with your fab's minimum trace, gap, drill and annular ring, not the defaults. If your fab runs an electrical test, KiCad can export an IPC-D-356 netlist so the tester knows which pads should connect.

The checklist

Open the zip you will upload. Not the export folder, and not the board file.
Count the layers. Copper equal to your stackup, mask and silkscreen per side, the outline, both drill files.
Find the outline. Closed, drawn once, cut-outs inside it, and the size matches your design.
Look through every hole. Each through-hole pad has a hole in it; vias sit inside their pads.
Read the solder mask. An opening over every pad, none over vias you meant to cover, no slivers thinner than your fab can make.
Check the paste, if you order a stencil: SMD pads only, and not empty.
Read the silkscreen. Nothing on pads, text above the fab's minimum, bottom side mirrored from the top.
Match the order form. Size, layer count, thickness and finish agree with the files.

Every image here is PCBEditor's free Gerber viewer opening files that kicad-cli 9.0 exported from one board; the broken sets come from export settings, not hand edits. The viewer reads the zip in your browser, with no sign-up. The full guide is on pcbeditor.com.

What's the Gerber mistake that cost you a board? I'm collecting the ones a viewer would have caught and the ones it wouldn't.

KiCad vs EasyEDA vs Altium in 2026: Pick by the Job, Not the Hype

Dibyaprakash Pradhan — Wed, 14 Oct 2026 10:58:01 +0000

"Which PCB software should I learn?" gets asked every week, and the answers usually come from whatever the person answering happens to use. So here's an attempt at a fairer version: what each of the three big options is good at, taken from each one's own published material, and which job it fits.

EasyEDA: the gentlest start

EasyEDA is free, runs in a browser (with desktop clients if you want them) and comes in two editions: Standard, aimed at students and education, and Pro, with larger designs, constraint-driven design, team features and a full offline mode. Both include SPICE simulation.

Its real advantage is what it's connected to: the LCSC parts catalogue and JLCPCB's fabrication and assembly. You place a part that's actually in stock, and the board, the bill of materials and the assembly files line up with what will be sent to you. For a first board that removes a whole class of mistakes. The trade-off is that the workflow is built around one supply chain.

KiCad: free, open, and serious

KiCad is free and open source (GPL-3.0), runs on Windows, macOS and Linux, and works completely offline. It stopped being "the hobbyist option" a while ago. Version 10, released in March 2026, added design variants, time-domain length tuning for high-speed nets, a graphical rule editor and importers for Allegro and PADS, on top of a good push-and-shove interactive router and built-in SPICE.

A two-layer board drawn in KiCad 9, routed with the external Freerouting autorouter and rendered with KiCad's own 3D models.

The cost is learning time. Libraries, footprint assignment and board setup take a while, and KiCad doesn't ship an autorouter. You route by hand with the interactive router or use an external one like Freerouting.

Altium: when the licence pays for itself

Altium Designer is a commercial Windows application sold by subscription, priced per seat, with a free trial; its own pricing page has the current tiers. What you pay for is depth: signal-integrity and constraint tools for high-speed design, managed libraries tied to supply-chain data, mechanical CAD integration, and collaboration for teams on the same product.

One person drawing boards with no gigabit interfaces won't use most of that. A team shipping DDR, PCIe or RF products to production usually will. Altium also has CircuitMaker, a free Windows tool on its engine for personal projects.

Which one for you

First board, ordering from JLCPCB: EasyEDA.
Free forever, any OS, offline, open source: KiCad.
A skill that carries into many jobs and open hardware: KiCad.
A team shipping high-speed or regulated products: Altium.
Altium's engine for personal projects, free, on Windows: CircuitMaker.

Switching later

Moving between them is rarely clean. KiCad imports Altium designs and EasyEDA imports several formats, but footprints, design rules and stackups usually need fixing afterwards, and libraries don't travel perfectly. Fabrication output does: all three export Gerber, drill, BOM and pick-and-place files, so the fab never cares which one you used.

A different first step

I work on PCBEditor, which isn't a fourth editor for the same job. It covers the step before: you describe the board in plain English, an AI chooses parts and intent, and deterministic algorithms build the netlist, place, route and check it. You can then export Gerbers, or open the native KiCad file and keep working in KiCad. If drawing the first version is the part that's stopping you, that's what it's for. The full comparison table is on pcbeditor.com.

Which one did you start with, and would you pick it again?

Via-in-Pad: The Space Saver That Quietly Drains Your Solder Joints

Dibyaprakash Pradhan — Tue, 13 Oct 2026 16:53:58 +0000

"Vias directly on SMD pads?" is one of the most-viewed PCB questions on Electrical Engineering Stack Exchange, and the answers there all say some version of "it depends". It does, but on one thing only: what happens to the hole.

The problem with an open hole

A plated hole is a capillary. During reflow, molten solder on the pad flows into the via and runs down the barrel. The joint above is left with less solder than the stencil gave it. On a big pad that's a weaker joint. On a small resistor or a fine-pitch lead it can be almost no joint at all, an intermittent connection you can't see.

Dog-bone fan-out, via-in-pad and QFN thermal vias on one real board. A top view can't show the fill: the middle panel's vias must be filled and capped.

It also causes a strange, specific failure: tombstoning. Put a via in one pad of an 0402 resistor and not the other, and the two ends wet differently. The side that keeps its solder pulls the part upright. If your small parts stand on end, and only on certain pads, look for vias in those pads.

When via-in-pad is the right call

Fine-pitch BGAs. Between closely spaced balls there's no room for a via and a trace. The inner balls go down through vias in their pads.
Boxed-in pads. On dense packages some inner pads are surrounded by others with no path out on the top layer. A via in the pad is the only exit.
Thermal pads. The exposed pad under a QFN or power part is usually stitched to inner ground with an array of vias to carry heat. That's normal practice; keep drills small and follow the part's recommended land pattern.
Very short high-speed connections, where removing the trace between pad and via removes a little inductance.

What to tell the fab

IPC-4761 names seven ways to protect a via, Type I to Type VII. Tenting and plugging (Types I to IV) are for ordinary vias that aren't in a pad. For a via under a solder joint you want Type VII: filled and capped, often sold as VIPPO (via-in-pad plated over). The hole is filled, sanded flat and plated over, so the pad solders as if there were no hole.

It costs extra (fill, cure, planarise, plate) and sometimes adds lead time, and some budget fabs don't offer it. Check before you design around it, and write it in your fabrication notes so it isn't missed.

The decision in four lines

Room for a via beside the pad on a short trace? Use that (a "dog-bone").
Thermal pad under a QFN or power part? Thermal vias in the pad are normal; follow the land pattern.
Fine-pitch BGA or a boxed-in pad? Via-in-pad, filled and capped, and tell the fab.
Small passive or ordinary fine-pitch lead? Don't put an open via in it.

How we ended up dealing with it

The router in the AI PCB tool I work on escapes dense parts with ordinary vias wherever there's a path. We only added via-in-pad when a real board, a chip-down nRF52840 in a fine-pitch package, had pads that were completely boxed in: no amount of clever routing gets a trace out of a pad that has no gap next to it. The router now launches only those pads through a via in their own centre, picks the smallest via that fits, and in review mode it asks before doing so, because the moment a board has signal vias in pads, the fab order has to change too.

That's the general lesson: via-in-pad isn't a layout trick, it's a manufacturing decision. The guide with cross-section diagrams of the three options and the full IPC-4761 table is on pcbeditor.com.

Have you had a via-in-pad board come back with bad joints? I'd like to know whether it was the via, the fill spec, or the fab.

AGND, DGND and Chassis Ground: The Three Grounding Questions Everyone Asks

Dibyaprakash Pradhan — Mon, 12 Oct 2026 12:21:27 +0000

Grounding advice has a reputation for contradicting itself. Split the plane; don't split the plane. Ground the chassis; don't make loops. Part of the problem is that three different questions get asked as if they were one. They have different answers, and knowing which one you're facing is most of the job.

1. The chip has AGND and DGND pins. Do I connect them?

ADCs, DACs and some sensors have separate AGND and DGND pins, and the names make it sound like an instruction to keep two grounds apart. It isn't. The pins are separate inside the package so the analog and digital currents don't share the chip's own tiny bond wires.

For most converters, Analog Devices' guidance (their tutorial MT-031 is the classic reference) is to connect both pins to the same low-impedance ground plane, right at the chip, with the shortest connections you can manage. The digital currents these chips draw are small, so tying DGND to the analog ground does far less harm than separating them, which would put the chip's two grounds at different voltages.

Always check the converter's own datasheet and evaluation board layout first. That's the exception that matters.

2. Should I split the ground plane into analog and digital?

Usually not, and this is the one people find hardest to believe. A return current follows the path directly under its own trace. Cut a slot in the plane and the current has to detour around the gap, making a loop that radiates and picks up exactly the noise you were trying to avoid.

A real mixed-signal layout. Top: analog left, digital right, the converter on the boundary, and one chassis point (a plated hole with 1 nF and 1 MΩ to ground) by the USB connector. Bottom: one ground plane, unbroken under the analog side.

What you separate is the parts, not the plane. Put the analog circuitry on one side, the digital and switching circuitry on the other, with the converter on the boundary. Route analog traces only over the analog area and digital traces only over the digital area. The plane stays whole, and the noisy return currents stay on their own side because that's where their traces are.

The partition only works if traces respect it. A single clock line routed through the analog area brings its return current with it. If a signal has to cross, cross at the converter.

3. Should circuit ground connect to the metal chassis?

Usually at one point, near the connectors where cables enter. The chassis is a shield and the place static discharge and cable noise end up, and the goal is to send that energy to the chassis where it comes in, without it travelling through your circuit first.

One connection, close to the I/O connectors.
Cable shields bonded to the chassis at the entry, ideally all the way round, not via a long pigtail wire.
If you need DC isolation between circuit and chassis, a capacitor at that point, often with a high-value resistor in parallel to bleed off static charge.
Not several scattered connections, which push current through the enclosure between them.

For mains-powered equipment in a metal case there's a safety requirement on top: the chassis is bonded to protective earth as your product's safety standard specifies. That's not a layout choice, and it's never the thing to remove to fix a hum.

Bonus: the isolated supply

An isolated DC/DC converter exists so that its two sides don't share a ground. Connecting them on the board throws away the reason you bought it. Draw the isolation barrier as a clear line, with no copper, pour or trace crossing it, and keep the spacing the converter and your safety requirements ask for. IPC-2221's conductor spacing table is a floor; safety standards often want more.

A short layout check

Continuous ground plane under analog and digital areas, no slots under fast traces.
Converter AGND and DGND to the plane right at the chip.
Analog traces over the analog area only, digital over digital.
Decoupling at every power pin with a short path to the plane.
Circuit ground meets the chassis once, near the connectors.
Nothing crosses an isolation barrier except the isolator.

The full guide, with a diagram of the partitioned board and the chassis connection, is on pcbeditor.com.

Which grounding rule have you had to break, and why? The exceptions are the interesting part.