DEV Community: Lindy kellams

Why Is an RC Filter's Cutoff Frequency -3 dB?

Lindy kellams — Mon, 21 Sep 2026 06:02:45 +0000

Why Is an RC Filter's Cutoff Frequency -3 dB?

Alternative titles

RC Filters at Cutoff: Why the Signal Is 0.707, Not 0.5
What the -3 dB Point Actually Means in a First-Order RC Filter
From RC to 159 Hz: Understanding the First-Order Filter Transition

Short description / excerpt

The familiar RC cutoff formula gives a frequency, but the -3 dB label explains what that frequency means. Using a 10 kΩ resistor and 100 nF capacitor, this article connects the calculation to amplitude, power, low-pass and high-pass behaviour, and real circuit limits.

Recommended tags

electronics, embedded, engineering, beginners

Article

An RC filter is often introduced with one compact equation:

fc = 1 / (2πRC)

Put 10 kΩ and 100 nF into that equation and the result is 159.15 Hz. That part is easy to calculate. The more useful question is what the number means in a circuit.

Why is the point called “-3 dB”? Why not call it the frequency where the signal is half? And why do low-pass and high-pass filters share the same cutoff expression even though they pass opposite parts of the spectrum?

The answer is in the word transition. A first-order RC filter does not behave like an on/off switch. Its cutoff frequency is the conventional marker in a gradual change from passband to attenuation.

Start with one concrete RC value

For a resistor of 10 kΩ and a capacitor of 100 nF:

R = 10,000 Ω
C = 100 × 10^-9 F

fc = 1 / (2π × 10,000 × 100 × 10^-9)
   = 159.154943... Hz

So a sensible engineering display is 159.15 Hz. This is the same cutoff frequency whether the parts are wired as a basic RC low-pass or a basic RC high-pass. The response around that point is different, but the RC time scale is the same.

The key number at cutoff is 1/√2

For an ideal first-order RC low-pass, the output magnitude is:

|HLP(f)| = 1 / √(1 + (f / fc)^2)

At f = fc, the ratio f / fc is 1. Substituting it gives:

|HLP(fc)| = 1 / √(1 + 1^2)
          = 1 / √2
          ≈ 0.70710678

The high-pass magnitude is:

|HHP(f)| = (f / fc) / √(1 + (f / fc)^2)

At the same frequency, it also becomes 1 / √2. In other words, a low-pass has fallen to about 70.7% of its passband voltage amplitude at cutoff, while a high-pass has risen to about 70.7% of its passband amplitude.

That is why the same fc is meaningful for both topologies.

Why 0.707 becomes -3 dB

Decibels for a voltage or amplitude ratio are calculated as:

20 log10(Vout / Vin)

At cutoff, the amplitude ratio is 1 / √2:

20 log10(1 / √2) = -3.0103 dB

Engineers usually shorten that to -3 dB. The approximation is close enough for the label, but the distinction matters when explaining it.

“-3 dB” does not mean the voltage amplitude is half. Half voltage would be approximately -6.02 dB. At the cutoff of this RC filter, voltage amplitude is about 0.707 of the passband value.

Power is proportional to voltage squared when impedance is unchanged. Squaring the cutoff amplitude ratio gives:

(1 / √2)^2 = 1 / 2 = 0.5

So at the -3 dB point, the power is half of the passband power for the same impedance. This is the origin of the common “half-power point” phrase.

Reading the low-pass response

In a low-pass RC circuit, low frequencies see little attenuation. At frequencies well below 159.15 Hz in this example, the output is close to the input. At 159.15 Hz, the magnitude is 0.707. Above that, the capacitor increasingly shunts the output toward ground and the output falls gradually.

Far above cutoff, an ideal first-order low-pass rolls off at roughly -20 dB per decade. That is a slope, not a vertical edge. A 1 kHz component is attenuated more than a 200 Hz component, but neither disappears simply because it is above 159 Hz.

Reading the high-pass response

A high-pass RC circuit tells the complementary story. Very low frequencies are attenuated because the series capacitor presents a large reactance. At 159.15 Hz, the output has reached 0.707 of its high-frequency passband amplitude. At much higher frequencies, the capacitor’s reactance becomes small and the output approaches the input.

Far below cutoff, the ideal high-pass magnitude changes at about +20 dB per decade as frequency rises. Again, cutoff is the center of a transition, not a brick wall.

A useful way to check the intuition

It helps to calculate a few frequencies rather than treating fc as a magic boundary. For the 159.15 Hz low-pass:

At 15.9 Hz, one tenth of cutoff, the amplitude is close to 0.995.
At 159.15 Hz, it is 0.707.
At 1.59 kHz, ten times cutoff, it is close to 0.0995.

The high-pass has those endpoint magnitudes reversed: close to 0.0995 at one tenth of cutoff and close to 0.995 at ten times cutoff. These values make the gradual transition visible.

You can vary R, C, topology, and a frequency probe with the free CircuitClarity RC Filter Cutoff Calculator. Watching the response update is a useful complement to the equation.

The ideal formula is a starting point

The formula assumes an ideal source and an ideal load. In a physical circuit, the source resistance can become part of the effective R, and the next stage’s input impedance can load the output. Resistor and capacitor tolerances shift the actual cutoff. Capacitor ESR and parasitic capacitance or inductance matter more as frequency rises.

Those effects do not invalidate fc = 1 / (2πRC). They explain why it is best used as the nominal design value, followed by a check of the full circuit and the component data.

The -3 dB point is therefore not a failure threshold. It is a clear, reproducible reference: the frequency where a first-order RC filter’s amplitude is 1 / √2, its same-impedance power ratio is one half, and its transition is well underway.

Why Your Voltage Divider Output Changes When You Connect a Load

Lindy kellams — Sat, 19 Sep 2026 10:16:50 +0000

Why Your Voltage Divider Output Changes When You Connect a Load

Alternative titles

Voltage Dividers Are Not Voltage Regulators: Understanding the Loading Effect
The Missing Resistor in Your Voltage Divider Calculation
Why a 3.33 V Divider Can Become a 2.5 V Node

Short description / excerpt

A voltage divider can produce the expected voltage in a textbook calculation and still shift when another circuit connects to its output. This worked example shows why the load becomes part of the divider, how to calculate the new output, and when a divider is appropriate in a real design.

Article

A voltage divider gives 3.33 V on paper.

You connect something to the output.

Now the voltage is closer to 2.5 V.

Why?

The formula was not wrong. The circuit changed.

This is the voltage-divider loading effect: the thing connected to the output is not invisible. If it draws current, it changes the effective resistance seen by the divider and therefore changes the output voltage.

The ideal voltage divider

The familiar two-resistor divider has an input voltage, a top resistor R1, and a bottom resistor R2 connected to ground. The output is measured at the node between the two resistors:

Vin ── R1 ──┬── Vout
            │
            R2
            │
           GND

With no external load, the output is:

Vout = Vin × R2 / (R1 + R2)

This equation assumes that the output measurement draws negligible current. That assumption is often useful, but it is still an assumption.

A worked 5 V example

Take the following values:

Vin = 5 V
R1 = 10 kΩ
R2 = 20 kΩ

The unloaded output is:

Vout = 5 × 20 / (10 + 20)
     = 100 / 30
     = 3.333 V approximately

The current through the series divider is:

I = 5 / (10 kΩ + 20 kΩ)
  = 166.7 µA approximately

So far, the result is exactly what we expect.

What changes when a load is connected?

Now connect a load resistor of 20 kΩ from Vout to ground:

Vin ── R1 ──┬── Vout
            ├── R2 ── GND
            └── RL ── GND

The important detail is the connection location. Both R2 and RL connect between the same two nodes: Vout and ground. That means they are in parallel, not in series.

The load therefore becomes part of the voltage-divider calculation.

Replace the lower branch with an equivalent resistance

The parallel equivalent of R2 and RL is:

Req = R2 || RL
    = (R2 × RL) / (R2 + RL)

For two 20 kΩ resistors:

Req = 20 kΩ || 20 kΩ
    = 10 kΩ

The loaded circuit is now equivalent to a 10 kΩ top resistor in series with a 10 kΩ lower branch. Reapplying the divider equation:

Vout_loaded = 5 × 10 / (10 + 10)
            = 2.5 V

The output did not move because the original formula stopped working. It moved because the lower resistance changed from 20 kΩ to 10 kΩ.

The current through R1 is now 250 µA. At the output node, that current splits between R2 and RL. Since both branches are 20 kΩ and both have 2.5 V across them, each branch carries 125 µA.

Quantifying the loading error

Comparing the ideal and loaded results:

loading error = (3.333 - 2.5) / 3.333 × 100%
              ≈ 25%

A 25% shift is large enough to break many designs that looked correct when only the unloaded formula was considered.

Why this matters in real circuits

The load does not have to be an obvious resistor. It can be the input network of another circuit, a measurement instrument, a sensor interface, a bias network, or an ADC input. In each case, the next stage has some finite input impedance and may also have leakage or bias currents. From the divider's point of view, that next stage is part of the load.

For a high-impedance measurement input, the loading may be small compared with R2. For a lower-impedance input, it may be significant. The right question is not simply “What voltage does the divider formula give?” It is “What impedance does the next stage present to this node?”

A common mistake

The most common mistake is to calculate Vout from R1 and R2, then connect a load without recalculating. A related mistake is to treat the load as if it were in series with R2 because it appears later in the signal path. Topology matters more than drawing order: components sharing the same two nodes are parallel.

A useful design intuition

There is another way to see the same result. Before a load is attached, the divider can be viewed from its output node as a Thevenin source. Its open-circuit voltage is the ideal 3.333 V, and its source resistance is:

Rth = R1 || R2
    = 10 kΩ || 20 kΩ
    = 6.667 kΩ approximately

When a load is connected to that source, the load and Rth form another divider. A 20 kΩ load is not enormously larger than 6.667 kΩ, so it causes a noticeable drop. This viewpoint is useful when evaluating a divider as the source for a later stage: a low source resistance makes the node less sensitive to loading, but lowering both divider resistors also increases the continuous current drawn from Vin.

That tradeoff is why simply making every resistor smaller is not a complete design rule. Smaller values can reduce the percentage error from a given input impedance, but they consume more power and may be inappropriate for a battery-powered circuit. A buffer can provide a high input impedance and a low output impedance when the application needs both low loading and useful drive capability.

The same reasoning applies to a multimeter or oscilloscope probe. The instrument has a specified input resistance, so it can be modeled as another load. If that resistance is many times larger than R2, the measurement error may be small. If it is comparable to R2, the measurement is part of the circuit and must be included.

When is a voltage divider appropriate?

A divider is useful when the output is a signal or reference that will feed a high-impedance input and only a small current is required. It is also useful for sensing, setting bias levels, and creating a simple threshold reference when the tolerance and source impedance are acceptable.

It is not a good general-purpose replacement for a regulated supply. A divider's output changes with its input, resistor tolerance, temperature, and load current. If a downstream circuit needs a stable voltage or meaningful power, consider a buffer, voltage regulator, or another circuit designed for that job.

If you want to experiment with different resistor and load values, the CircuitClarity Voltage Divider Calculator shows both the ideal divider and the loaded result so the effect is visible as the circuit changes.

The useful habit is simple: whenever something connects to a divider output, add that connection to the circuit model before trusting the number.

Recommended DEV tags

electronics embedded engineering beginners

3 Common STM32 Timer Mistakes That Give You the Wrong PWM Frequency

Lindy kellams — Sat, 05 Sep 2026 04:20:38 +0000

The symptom: PSC and ARR look right, but the frequency is wrong

STM32 timer math is compact enough to fit in one line, yet small assumptions can move a PWM output far from its target. Before changing firmware at random, check the timer clock, the register offsets, and the way you chose PSC and ARR. The examples below use an up-counting, edge-aligned time base.

Mistake #1: forgetting both “+1” terms

For this mode, the project calculator uses:

counterClock = timerClock / (PSC + 1)
PWM frequency = timerClock / ((PSC + 1) × (ARR + 1))
period = 1 / PWM frequency
duty = CCR / (ARR + 1) × 100%

The register values are zero-based. PSC=71 means a divide-by-72 prescaler, not divide-by-71. Likewise, an up-counter that runs from 0 through ARR=999 has 1,000 timer ticks per period. Using timerClock / (PSC × ARR) introduces two independent off-by-one errors and is especially misleading when either register is zero.

Mistake #2: using the wrong timer input clock

The CPU frequency is not automatically the input clock of every timer. Start at the clock tree: identify the APB bus, its prescaler, and the effective clock routed to the specific timer instance. Some STM32 families apply a timer-clock multiplication rule when an APB prescaler is not 1; other families and timer domains have different details. Treat that as a device-specific rule, not a universal STM32 constant.

The calculator's timerClock field means this effective input clock in hertz. If you enter the APB peripheral clock when the timer receives another value, the arithmetic can be internally correct and still disagree with the pin waveform. The exact reference manual for the MCU and its clock configuration is the authority.

Mistake #3: guessing PSC and ARR

PSC and ARR are a pair. Many integer pairs can produce the same frequency, but they do not provide the same counter rate or duty-cycle resolution.

PSC sets the counter clock after prescaling.
ARR sets the number of counter ticks in a period.
CCR sets the compare point. With PWM mode 1, edge alignment and active-high polarity, CCR / (ARR + 1) is the ideal duty calculation.
Both PSC and ARR must fit the selected timer width, and CCR must be within the useful range for ARR.

Choosing a pair is therefore a design decision, not a guessing game. A larger ARR generally gives more discrete compare values for duty control. The target-frequency solver in the calculator searches valid integer pairs, minimizes relative frequency error, and reports that error; it is still your responsibility to check the timer's actual capabilities and clock setup.

Worked example: 72 MHz timer clock, 1 kHz PWM

Suppose the clock tree and reference manual establish a 72,000,000 Hz timer input. Use PSC=71, ARR=999, and CCR=250.

Counter clock = 72,000,000 / (71 + 1) = 1,000,000 Hz.
Period ticks = 999 + 1 = 1,000.
PWM frequency = 1,000,000 / 1,000 = 1,000 Hz; period = 1 ms.
Ideal duty = 250 / 1,000 × 100 = 25%.

The same formula gives useful cross-checks:

Timer clock	PSC	ARR	CCR	Counter clock	PWM frequency	Duty
72 MHz	71	999	250	1 MHz	1 kHz	25%
72 MHz	719	999	500	100 kHz	100 Hz	50%
80 MHz	79	999	750	1 MHz	1 kHz	75%

These are arithmetic examples, not measurements. Startup timing, preload and update events, oscillator tolerance, output polarity, interrupts, DMA and board effects can change what an instrument observes.

Verify instead of guessing

I develop and maintain the STM32 Timer & PWM Calculator. It calculates counter clock, period, PWM frequency and ideal edge-aligned duty from timer clock, width, PSC, ARR and CCR, and includes a target-frequency solver with an error value.

To reproduce the worked example, enter 72000000 Hz, choose 16-bit, enter PSC 71, ARR 999, and CCR 250, then select Calculate. Check for 1 MHz counter clock, 1 kHz PWM frequency, 1 ms period and 25% duty. This is a repeatable arithmetic check, not an official STM32 configuration wizard or a hardware verification report.

A short debugging checklist

Check the effective timer input clock in the MCU clock tree.
Keep both PSC + 1 and ARR + 1 terms.
Confirm the timer width and register ranges.
Decide whether your chosen ARR provides enough duty resolution.
Check CCR against ARR and the selected PWM polarity/mode.
Compare the calculated result with the exact device reference manual.
Measure the final waveform separately when hardware behavior matters.

References and disclosure

ST's AN4776 timer cookbook gives official timer and PWM configuration examples. STM32F1 users can also consult the timer and RCC chapters of RM0008. Other STM32 families require their matching manuals.

AI assisted with drafting and language editing. The equations and numerical examples were independently recomputed from the stated model. No hardware measurements, user testimonials or performance guarantees are claimed.