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[Design]Mastering SSD Battery & Thermal Limits: The Implementation of Autonomous Power State Transition (APST)

hk0816 — Sat, 14 Nov 2026 23:56:05 +0000

🚀 Mastering SSD Battery & Thermal Limits: The Implementation of Autonomous Power State Transition (APST)

The Autonomous Power State Transition (APST) is a critical feature in modern NVMe SSDs, drastically extending battery life in laptops and minimizing thermal output and power consumption in data centers. It allows the SSD to autonomously step down to lower power states (Deep Sleep) when host I/O activity stops, without waiting for explicit commands from the OS.

However, simply cutting the power is a recipe for disaster. Embedded firmware engineers must solve two critical challenges:

Zero Data Loss (Fail-Safe): How can we guarantee that all volatile data in the DRAM cache is safely flushed to the NAND flash before power-gating the circuits?
Quality of Service (QoS): How do we ensure that waking up from a deep sleep doesn't exceed the host's maximum allowed latency, causing I/O timeouts?

In this article, based on the ESCR (Embedded Software Coding Reference) v3.0 and ESTR (Embedded Software Test Reference) guidelines, we present a robust, production-grade C implementation and its corresponding Unity test suite that safely orchestrates APST while perfectly balancing extreme power savings and strict QoS constraints.

💻 C Implementation (ESCR v3.0 Compliant)

This firmware module tracks the continuous idle time and autonomously decides whether to transition to a lower power state (PS1, PS2, PS3). It rigorously implements saturation arithmetic to prevent timer overflows and strictly mandates a cache flush before entering non-operational states.

#include <stdint.h>
#include <stdbool.h>
#include <stddef.h>

/* [ESCR] Elimination of Magic Numbers: Define constants clearly with 'U' suffix */
#define NVME_POWER_STATE_PS0        (0U)         /* Active: Full operational state */
#define NVME_POWER_STATE_PS1        (1U)         /* Light Sleep: Clock gating */
#define NVME_POWER_STATE_PS3        (3U)         /* Deep Sleep: Power gating (Non-operational) */
#define NVME_MAX_POWER_STATES       (4U)         /* Total supported states (PS0 to PS3) */
#define PM_IDLE_TIME_MAX_US         (0xFFFFFFFFU)/* Saturation limit for idle time */

/* Physical characteristic descriptor for each power state */
typedef struct {
    uint16_t max_power_mw;       /* Maximum power consumption (milliwatts) */
    uint32_t exit_latency_us;    /* Time required to wake up to PS0 (microseconds) */
    bool     is_non_operational; /* true: Deep Sleep (Cache flush required), false: Operational */
} PowerStateSpec_t;

/* APST Management Context */
typedef struct {
    bool     is_apst_enabled;
    uint8_t  current_ps;                                /* Current power state */
    uint32_t idle_time_us;                              /* Continuous idle time (us) */
    uint32_t max_allowed_latency_us;                    /* Host-defined QoS wakeup limit (us) */
    uint32_t idle_threshold_us[NVME_MAX_POWER_STATES];  /* Idle time threshold for each state */
} ApstManager_t;

/* Hardware specification table for each state (ROM constants) */
static const PowerStateSpec_t s_ps_specs[NVME_MAX_POWER_STATES] = {
    { 5000U,    0U, false }, /* PS0: 5.0W, 0us wakeup, Active */
    { 1500U,   50U, false }, /* PS1: 1.5W, 50us wakeup, Light Sleep */
    {  500U,  500U, false }, /* PS2: 0.5W, 500us wakeup, Medium Sleep */
    {   10U, 5000U, true  }  /* PS3: 10mW, 5ms wakeup, Deep Sleep (Power gated) */
};

/* [ESCR] Information Hiding: Use 'static' to restrict external access */
static ApstManager_t s_apst_mgr;

/* --- External HAL/FW Function Mocks --- */
/* Safely evicts all dirty data from volatile cache to NAND flash */
extern bool Cache_FlushAllDirtyData(void);
/* Instructs the Hardware PMU to transition to the target power state */
extern bool HAL_PmuSetPowerState(uint8_t target_ps);
/* Enables hardware interrupts to wake the CPU upon PCIe activity */
extern void HAL_EnableWakeupInterrupt(void);

/**
 * @brief Periodically updates the idle timer and transitions power states autonomously.
 * 
 * @param[in] elapsed_us Time elapsed since the last call (microseconds).
 * @return true: Successfully maintained or transitioned state, false: Hardware/Flush failure.
 */
bool PM_UpdateIdleAndTransition(uint32_t elapsed_us) {
    /* [ESCR] Single Exit Principle: Initialize the return variable */
    bool b_is_success = true;
    uint8_t target_ps = s_apst_mgr.current_ps;

    if (s_apst_mgr.is_apst_enabled == true) {

        /* [ESCR] Saturation Arithmetic: Prevent wrap-around bugs during prolonged idle periods */
        if ((PM_IDLE_TIME_MAX_US - s_apst_mgr.idle_time_us) >= elapsed_us) {
            s_apst_mgr.idle_time_us += elapsed_us;
        } else {
            s_apst_mgr.idle_time_us = PM_IDLE_TIME_MAX_US;
        }

        /* 1. Find the deepest permissible power state */
        for (uint8_t ps = (NVME_MAX_POWER_STATES - 1U); ps > s_apst_mgr.current_ps; ps--) {
            uint32_t threshold = s_apst_mgr.idle_threshold_us[ps];

            /* Verify if the threshold is met AND the QoS wakeup latency is not violated */
            if ((threshold > 0U) && 
                (s_apst_mgr.idle_time_us >= threshold) &&
                (s_ps_specs[ps].exit_latency_us <= s_apst_mgr.max_allowed_latency_us)) {

                target_ps = ps;
                break; /* Target found; exit the loop */
            }
        }

        /* 2. Execute the transition if a deeper state is selected */
        if (target_ps > s_apst_mgr.current_ps) {

            /* [Fail-Safe] Ensure data integrity before cutting power */
            if (s_ps_specs[target_ps].is_non_operational == true) {
                if (Cache_FlushAllDirtyData() == false) {
                    /* Abort the sleep transition to prioritize data retention */
                    b_is_success = false;
                }
            }

            /* Proceed only if the flush was successful (or not required) */
            if (b_is_success == true) {
                /* Always arm the wakeup interrupt BEFORE going to sleep */
                HAL_EnableWakeupInterrupt();

                if (HAL_PmuSetPowerState(target_ps) == true) {
                    s_apst_mgr.current_ps = target_ps;
                } else {
                    b_is_success = false;
                }
            }
        }
    }

    return b_is_success;
}

/**
 * @brief Interrupt Service Routine (ISR) triggered by Host I/O (e.g., PCIe Wake).
 */
void PM_HandleHostWakeupInterrupt(void) {
    /* Instantly reset the idle timer */
    s_apst_mgr.idle_time_us = 0U;

    /* If asleep, rapidly transition back to the Active state (PS0) */
    if (s_apst_mgr.current_ps != NVME_POWER_STATE_PS0) {
        if (HAL_PmuSetPowerState(NVME_POWER_STATE_PS0) == true) {
            s_apst_mgr.current_ps = NVME_POWER_STATE_PS0;
        }
    }
}

💡 Core Design Insights for Embedded Engineers

1. QoS-Aware Sleep Arbitration

Look at the condition: s_ps_specs[ps].exit_latency_us <= s_apst_mgr.max_allowed_latency_us.
Deep sleep states like PS3 take significant time to wake up (e.g., 5ms). If the host requires a response within 1ms, dropping into PS3 will inevitably cause an I/O timeout. This single line of code acts as an intelligent arbitrator, guaranteeing that the SSD will never sleep deeper than it can afford to, strictly preserving the promised QoS regardless of how long the drive has been idle.

2. Fail-Safe Cache Flushing

Before entering a "Non-operational" state (where DRAM power is gated), the firmware must invoke Cache_FlushAllDirtyData(). If the flush fails due to transient NAND errors, the firmware prioritizes data integrity over power savings by deliberately aborting the sleep sequence (b_is_success = false;). This fail-soft design prevents irreversible data loss.

3. Saturation Arithmetic against Timer Overflow

A standard 32-bit counter in microseconds overflows after roughly 71 minutes. Without saturation arithmetic, a server left idle for a weekend would experience integer wrap-around, resetting the idle_time_us to 0 and causing the SSD to unpredictably wake up for no reason. The ESCR-compliant saturation logic effectively clips the timer at its maximum value, ensuring stable behavior over indefinite idle periods.

🛠️ Extreme Unit Testing with Unity (ESTR Compliant)

Testing APST involves proving the negative: "Ensure it doesn't sleep if QoS fails" or "Ensure it doesn't sleep if data can't be flushed." Using the Unity framework, we mock the hardware to inject extreme conditions and guarantee fail-safe behavior.

#include "unity.h"
#include <stdint.h>
#include <stdbool.h>

/* Include the source file for white-box testing */
#include "ftl_power_management.c"

/* --- Mock Variables & Call Counters --- */
static bool     g_mock_flush_success = true;
static uint32_t g_call_cache_flush = 0U;

static bool     g_mock_pmu_set_success = true;
static uint32_t g_call_pmu_set = 0U;

static uint32_t g_call_enable_wakeup = 0U;

/* --- External HAL/FW Function Mocks --- */
bool Cache_FlushAllDirtyData(void) {
    g_call_cache_flush++;
    return g_mock_flush_success;
}

bool HAL_PmuSetPowerState(uint8_t target_ps) {
    g_call_pmu_set++;
    return g_mock_pmu_set_success;
}

void HAL_EnableWakeupInterrupt(void) {
    g_call_enable_wakeup++;
}

/* --- Test Setup --- */
void setUp(void) {
    g_mock_flush_success = true;
    g_mock_pmu_set_success = true;
    g_call_cache_flush = 0U;
    g_call_pmu_set = 0U;
    g_call_enable_wakeup = 0U;

    /* Initialize APST Manager */
    s_apst_mgr.is_apst_enabled = true;
    s_apst_mgr.current_ps = NVME_POWER_STATE_PS0;
    s_apst_mgr.idle_time_us = 0U;
    s_apst_mgr.max_allowed_latency_us = 10000U; /* 10ms (Plenty of tolerance) */

    /* Set Thresholds */
    s_apst_mgr.idle_threshold_us[NVME_POWER_STATE_PS0] = 0U;      /* Base state */
    s_apst_mgr.idle_threshold_us[NVME_POWER_STATE_PS1] = 10000U;  /* 10ms to PS1 */
    s_apst_mgr.idle_threshold_us[2]                    = 0U;      /* PS2 unused */
    s_apst_mgr.idle_threshold_us[NVME_POWER_STATE_PS3] = 50000U;  /* 50ms to PS3 */
}
void tearDown(void) {}

/* =========================================================
 *  Test Cases for PM_UpdateIdleAndTransition (ESTR Compliant)
 * ========================================================= */

/* 1. Boundary Value Test: Timer Saturation (Prevent Wrap-around) */
void test_PM_UpdateIdle_Overflow_ShouldSaturateAtMax(void) {
    s_apst_mgr.idle_time_us = PM_IDLE_TIME_MAX_US - 100U; /* 100us before overflow */

    /* Add 150us (theoretically pushing it 50us past the limit) */
    PM_UpdateIdleAndTransition(150U);

    TEST_ASSERT_EQUAL_UINT32_MESSAGE(
        PM_IDLE_TIME_MAX_US, 
        s_apst_mgr.idle_time_us, 
        "[Boundary] The timer must saturate at the maximum value instead of wrapping around to 0."
    );
}

/* 2. Normal Path: Transition to PS3 with proper safety sequences */
void test_PM_Transition_ToPS3_ShouldFlushAndEnableWakeup(void) {
    /* Exceed the PS3 threshold (50ms) */
    bool result = PM_UpdateIdleAndTransition(60000U);

    TEST_ASSERT_TRUE_MESSAGE(result, "State transition should succeed.");
    TEST_ASSERT_EQUAL_UINT8_MESSAGE(NVME_POWER_STATE_PS3, s_apst_mgr.current_ps, "System should enter PS3.");

    /* Verify Transaction Order & Safety */
    TEST_ASSERT_EQUAL_UINT32_MESSAGE(1U, g_call_cache_flush, "[Fail-Safe] Cache MUST be flushed before entering Deep Sleep.");
    TEST_ASSERT_EQUAL_UINT32_MESSAGE(1U, g_call_enable_wakeup, "Wakeup interrupts MUST be armed before powering down.");
    TEST_ASSERT_EQUAL_UINT32_MESSAGE(1U, g_call_pmu_set, "Hardware power control command should be issued.");
}

/* 3. QoS Trade-off Arbitration: Idle time allows PS3, but QoS restricts to PS1 */
void test_PM_Transition_QosConstraint_ShouldLimitToPS1(void) {
    /* Host demands a maximum wakeup latency of 1,000us (1ms) */
    s_apst_mgr.max_allowed_latency_us = 1000U; 

    /* Exceed the PS3 threshold (50ms) */
    PM_UpdateIdleAndTransition(60000U);

    /* PS3 exit latency is 5ms, which violates the 1ms QoS limit. Therefore, it should stop at PS1. */
    TEST_ASSERT_EQUAL_UINT8_MESSAGE(NVME_POWER_STATE_PS1, s_apst_mgr.current_ps, "[QoS] Should cap the transition at PS1 to guarantee wakeup latency.");
    TEST_ASSERT_EQUAL_UINT32_MESSAGE(0U, g_call_cache_flush, "PS1 does not gate power, so unnecessary cache flushing should be skipped.");
}

/* 4. Fault Injection (Fail-Soft): Flush failure aborts the Deep Sleep transition */
void test_PM_Transition_FlushFails_ShouldAbortSafely(void) {
    /* [Fault Injection] Hardware fails to write cache to NAND */
    g_mock_flush_success = false;

    bool result = PM_UpdateIdleAndTransition(60000U); /* Attempt to enter PS3 */

    TEST_ASSERT_FALSE_MESSAGE(result, "Transition should be aborted (return false) upon flush failure.");

    /* [ESTR Fail-Soft Verification] */
    TEST_ASSERT_EQUAL_UINT8_MESSAGE(NVME_POWER_STATE_PS0, s_apst_mgr.current_ps, "[Data Protection] System MUST NOT power down if dirty data cannot be secured.");
    TEST_ASSERT_EQUAL_UINT32_MESSAGE(0U, g_call_pmu_set, "Hardware PMU should not be touched.");
}

/* 5. Asynchronous Event: Immediate wakeup and timer reset upon Host I/O */
void test_PM_HandleWakeup_ShouldResetTimerAndReturnToPS0(void) {
    /* Setup: Currently sleeping in PS1 */
    s_apst_mgr.current_ps = NVME_POWER_STATE_PS1;
    s_apst_mgr.idle_time_us = 15000U;

    /* Simulate Host PCIe Wakeup Interrupt */
    PM_HandleHostWakeupInterrupt();

    TEST_ASSERT_EQUAL_UINT32_MESSAGE(0U, s_apst_mgr.idle_time_us, "Idle timer must be instantly reset to 0.");
    TEST_ASSERT_EQUAL_UINT8_MESSAGE(NVME_POWER_STATE_PS0, s_apst_mgr.current_ps, "System must immediately return to Active state (PS0).");
    TEST_ASSERT_EQUAL_UINT32_MESSAGE(1U, g_call_pmu_set, "Hardware wakeup command must be issued.");
}

🎯 Key Test Design Principles

1. Proving State Preservation via Boundary Value Analysis

Test case 1 (Overflow_ShouldSaturateAtMax) highlights a classic embedded system bug: timer wrap-around. By feeding an elapsed time that intentionally breaks the 32-bit ceiling, we mathematically prove that the saturation logic holds the line. This guarantees long-term stability in highly available environments like enterprise data centers.

2. Validating Fail-Soft Data Protection

Test case 4 (FlushFails_ShouldAbortSafely) embodies the ESTR fail-soft philosophy. By simulating a NAND write error exactly at the moment the SSD tries to go to sleep, we assert that g_call_pmu_set remains 0U. This mathematically guarantees that the firmware will never prioritize power savings over the integrity of the user's data.

Implementing data transfer acceleration via "multi-channel interleaving" to unlock the maximum throughput of enterprise SSDs.

hk0816 — Sun, 01 Nov 2026 06:01:39 +0000

Accelerating SSD data transfer

Sample Code

#include <stdint.h>
#include <stdbool.h>
#include <stddef.h>

/* [ESCR] Eliminate magic numbers: Always append 'U' suffix */
#define FTL_NAND_CHANNELS           (8U)    /* Number of NAND channels on the controller */
#define FTL_MAX_DMA_DESCRIPTORS     (64U)   /* Max DMA descriptors issued per transaction */
#define FTL_SECTORS_PER_PAGE        (8U)    /* Logical sectors per physical page (4KB / 512B) */

/* Hardware DMA Request Structure */
typedef struct {
    uint32_t pba;           /* Physical Block Address */
    uint16_t sector_count;  /* Number of sectors to transfer */
    uint8_t  channel_id;    /* Target hardware channel (for parallel execution) */
    uint8_t  is_write;      /* Write(1) or Read(0) */
} HW_DmaRequest_t;

/* --- Mock declarations for external HAL/FTL functions --- */
/* Translates LBA to PBA and retrieves the physical channel ID attached to it */
extern uint32_t FTL_TranslateLbaToPbaAndChannel(uint64_t lba, uint8_t* p_out_channel);
/* Submits the built DMA descriptor to the hardware submission queue */
extern bool HAL_SubmitDmaRequest(const HW_DmaRequest_t* p_request);

/**
 * @brief Dispatches a host I/O request across multiple channels for parallel DMA transfer (Interleaving).
 * 
 * @param[in] start_lba      Starting Logical Block Address
 * @param[in] total_sectors  Total number of sectors to transfer
 * @param[in] is_write       True for Write, False for Read
 * @return true: All DMA queued successfully, false: Argument error or hardware queue full
 */
bool FTL_DispatchInterleavedTransfer(uint64_t start_lba, uint32_t total_sectors, bool is_write) {
    /* [ESCR] Single Exit Principle */
    bool b_is_success = false;
    bool b_has_error = false;

    HW_DmaRequest_t dma_req;
    uint32_t sectors_processed = 0U;
    uint32_t current_chunk;
    uint8_t  target_channel;
    uint32_t target_pba;
    uint32_t dma_count = 0U;

    /* [ESCR] Defensive Programming: Reject invalid size requests */
    if ((total_sectors > 0U) && (total_sectors <= (FTL_MAX_DMA_DESCRIPTORS * FTL_SECTORS_PER_PAGE))) {

        while ((sectors_processed < total_sectors) && (b_has_error == false)) {

            /* Calculate current chunk size without crossing page boundaries */
            current_chunk = FTL_SECTORS_PER_PAGE - ((start_lba + sectors_processed) % FTL_SECTORS_PER_PAGE);
            if (current_chunk > (total_sectors - sectors_processed)) {
                current_chunk = total_sectors - sectors_processed;
            }

            /* Address translation and channel assignment (Interleaving distribution happens here) */
            target_pba = FTL_TranslateLbaToPbaAndChannel(start_lba + sectors_processed, &target_channel);

            /* Build DMA descriptor */
            dma_req.pba          = target_pba;
            dma_req.sector_count = (uint16_t)current_chunk;
            dma_req.channel_id   = target_channel;
            dma_req.is_write     = is_write ? 1U : 0U;

            /* Asynchronously submit DMA request to hardware (parallel execution starts per channel) */
            if (HAL_SubmitDmaRequest(&dma_req) == true) {
                sectors_processed += current_chunk;
                dma_count++;
            } else {
                b_has_error = true; /* e.g., Hardware queue exhaustion */
            }

            /* Infinite loop prevention: DMA submission upper bound guard */
            if (dma_count >= FTL_MAX_DMA_DESCRIPTORS) {
                b_has_error = true;
            }
        }

        /* Success is only granted if all sectors were dispatched without error */
        if ((b_has_error == false) && (sectors_processed == total_sectors)) {
            b_is_success = true;
        }
    }

    return b_is_success;
}

Test Code

#include <stdint.h>
#include <stdbool.h>
#include <stddef.h>

/* [ESCR] Eliminate magic numbers: Always append 'U' suffix */
#define FTL_NAND_CHANNELS           (8U)    /* Number of NAND channels on the controller */
#define FTL_MAX_DMA_DESCRIPTORS     (64U)   /* Max DMA descriptors issued per transaction */
#define FTL_SECTORS_PER_PAGE        (8U)    /* Logical sectors per physical page (4KB / 512B) */

/* Hardware DMA Request Structure */
typedef struct {
    uint32_t pba;           /* Physical Block Address */
    uint16_t sector_count;  /* Number of sectors to transfer */
    uint8_t  channel_id;    /* Target hardware channel (for parallel execution) */
    uint8_t  is_write;      /* Write(1) or Read(0) */
} HW_DmaRequest_t;

/* --- Mock declarations for external HAL/FTL functions --- */
/* Translates LBA to PBA and retrieves the physical channel ID attached to it */
extern uint32_t FTL_TranslateLbaToPbaAndChannel(uint64_t lba, uint8_t* p_out_channel);
/* Submits the built DMA descriptor to the hardware submission queue */
extern bool HAL_SubmitDmaRequest(const HW_DmaRequest_t* p_request);

/**
 * @brief Dispatches a host I/O request across multiple channels for parallel DMA transfer (Interleaving).
 * 
 * @param[in] start_lba      Starting Logical Block Address
 * @param[in] total_sectors  Total number of sectors to transfer
 * @param[in] is_write       True for Write, False for Read
 * @return true: All DMA queued successfully, false: Argument error or hardware queue full
 */
bool FTL_DispatchInterleavedTransfer(uint64_t start_lba, uint32_t total_sectors, bool is_write) {
    /* [ESCR] Single Exit Principle */
    bool b_is_success = false;
    bool b_has_error = false;

    HW_DmaRequest_t dma_req;
    uint32_t sectors_processed = 0U;
    uint32_t current_chunk;
    uint8_t  target_channel;
    uint32_t target_pba;
    uint32_t dma_count = 0U;

    /* [ESCR] Defensive Programming: Reject invalid size requests */
    if ((total_sectors > 0U) && (total_sectors <= (FTL_MAX_DMA_DESCRIPTORS * FTL_SECTORS_PER_PAGE))) {

        while ((sectors_processed < total_sectors) && (b_has_error == false)) {

            /* Calculate current chunk size without crossing page boundaries */
            current_chunk = FTL_SECTORS_PER_PAGE - ((start_lba + sectors_processed) % FTL_SECTORS_PER_PAGE);
            if (current_chunk > (total_sectors - sectors_processed)) {
                current_chunk = total_sectors - sectors_processed;
            }

            /* Address translation and channel assignment (Interleaving distribution happens here) */
            target_pba = FTL_TranslateLbaToPbaAndChannel(start_lba + sectors_processed, &target_channel);

            /* Build DMA descriptor */
            dma_req.pba          = target_pba;
            dma_req.sector_count = (uint16_t)current_chunk;
            dma_req.channel_id   = target_channel;
            dma_req.is_write     = is_write ? 1U : 0U;

            /* Asynchronously submit DMA request to hardware (parallel execution starts per channel) */
            if (HAL_SubmitDmaRequest(&dma_req) == true) {
                sectors_processed += current_chunk;
                dma_count++;
            } else {
                b_has_error = true; /* e.g., Hardware queue exhaustion */
            }

            /* Infinite loop prevention: DMA submission upper bound guard */
            if (dma_count >= FTL_MAX_DMA_DESCRIPTORS) {
                b_has_error = true;
            }
        }

        /* Success is only granted if all sectors were dispatched without error */
        if ((b_has_error == false) && (sectors_processed == total_sectors)) {
            b_is_success = true;
        }
    }

    return b_is_success;
}

BiCS FLASH memory controller error correction and data reliability enhancement (ECC) function

hk0816 — Sun, 25 Oct 2026 03:50:32 +0000

High-capacity, high-density flash memory such as BiCS FLASH (3D NAND) is prone to bit inversion due to minute charge loss (retention degradation) and interference between adjacent cells (read disturb), making robust error correction (ECC: Error Correction Code) essential. While this is usually handled by hardware (LDPC or BCH engine), we have created sample code here that simulates a process where the device driver (software layer) controls and monitors the hardware ECC engine, and performs read retries (re-reading by adjusting the read voltage) as needed.

This code complies with the Ministry of Economy, Trade and Industry's IPA's "ESCR [C language version] Ver. 3.0," and thoroughly implements defensive programming, constant definition, and const qualifiers.

1. Sample Code

#include <stdint.h>
#include <stdbool.h>
#include <stddef.h>

/* Constants Definition (Elimination of Magic Numbers) */
#define BICS_PAGE_DATA_SIZE         (4096U) /* User data size (4KB) */
#define BICS_PAGE_PARITY_SIZE       (256U)  /* Parity data size */
#define BICS_MAX_CORRECTABLE_BITS   (120U)  /* Maximum correctable bits (Assuming LDPC) */
#define BICS_MAX_READ_RETRY_COUNT   (5U)    /* Maximum limit for read retry (voltage shift) */

/* ECC Operation Result Codes */
typedef enum {
    BICS_ECC_SUCCESS = 0,         /* No errors (or parity generation successful) */
    BICS_ECC_CORRECTED = 1,       /* Errors successfully corrected */
    BICS_ECC_UNCORRECTABLE = 2,   /* Uncorrectable errors (e.g., retry limit exceeded) */
    BICS_ECC_INVALID_PARAM = 3    /* Invalid parameters provided */
} bics_ecc_result_t;

/* Mock Interface for Hardware ECC Engine */
typedef struct {
    /* Reads data/parity and returns the number of error bits using Hard Decision */
    uint32_t (*hw_decode_hard)(const uint8_t* data, const uint8_t* parity);
    /* Shifts the read reference voltage (Vth) for Read Retry */
    bool (*hw_shift_read_voltage)(uint8_t retry_step);
    /* Reads the raw page data from NAND flash again */
    bool (*hw_read_page_raw)(uint32_t block, uint32_t page, uint8_t* data, uint8_t* parity);
} bics_ecc_hw_engine_t;

/* ECC Management Context */
typedef struct {
    bics_ecc_hw_engine_t hw_engine;
} bics_ecc_context_t;

/**
 * @brief  Generates parity data during a write operation (Encoding)
 * @note   ESCR Compliant: NULL pointer checks, const correctness applied
 */
bics_ecc_result_t bics_ecc_encode(
    const bics_ecc_context_t* const ctx,
    const uint8_t* const data,
    uint8_t* const parity_out) 
{
    if ((ctx == NULL) || (data == NULL) || (parity_out == NULL)) {
        return BICS_ECC_INVALID_PARAM;
    }

    /* In a real scenario, this transfers data to the hardware to generate parity. */
    /* For simulation purposes, we initialize the parity buffer to 0. */
    for (uint32_t i = 0U; i < BICS_PAGE_PARITY_SIZE; i++) {
        parity_out[i] = 0x00U;
    }

    return BICS_ECC_SUCCESS;
}

/**
 * @brief  Performs error correction (Decoding) and Read Retry on read operations
 * @note   ESCR Compliant: Comprehensive error handling, clear loop boundaries
 */
bics_ecc_result_t bics_ecc_decode_with_retry(
    const bics_ecc_context_t* const ctx,
    uint32_t block,
    uint32_t page,
    uint8_t* const data,
    uint8_t* const parity) 
{
    if ((ctx == NULL) || (data == NULL) || (parity == NULL)) {
        return BICS_ECC_INVALID_PARAM;
    }
    if ((ctx->hw_engine.hw_decode_hard == NULL) || 
        (ctx->hw_engine.hw_shift_read_voltage == NULL) || 
        (ctx->hw_engine.hw_read_page_raw == NULL)) {
        return BICS_ECC_INVALID_PARAM;
    }

    uint8_t retry_count = 0U;
    uint32_t error_bits = 0U;

    while (retry_count <= BICS_MAX_READ_RETRY_COUNT) {
        /* Execute error detection and correction via Hardware ECC Engine */
        error_bits = ctx->hw_engine.hw_decode_hard(data, parity);

        if (error_bits == 0U) {
            return BICS_ECC_SUCCESS; /* No errors found */
        }
        if (error_bits <= BICS_MAX_CORRECTABLE_BITS) {
            return BICS_ECC_CORRECTED; /* Errors were correctable */
        }

        /* If uncorrectable, perform a Read Retry by adjusting the read voltage */
        retry_count++;
        if (retry_count <= BICS_MAX_READ_RETRY_COUNT) {
            if (!ctx->hw_engine.hw_shift_read_voltage(retry_count)) {
                return BICS_ECC_UNCORRECTABLE; /* Voltage shift operation failed */
            }
            if (!ctx->hw_engine.hw_read_page_raw(block, page, data, parity)) {
                return BICS_ECC_UNCORRECTABLE; /* Raw read operation failed */
            }
        }
    }

    /* Uncorrectable ECC error (UECC) occurs if correction fails after maximum retries */
    return BICS_ECC_UNCORRECTABLE;
}

Key Points of ESCR Ver.3.0 Compliance

Ensuring NULL Safety (M101 / M102, etc.): Strict NULL checks for structure pointers and hardware operation function pointers are performed at the beginning of functions in bics_ecc_encode and bics_ecc_decode_with_retry.
Strict Const Modifier Use (M113): The const modifier is applied to argument pointers that cannot be changed (context, read-only data). This prevents unexpected data corruption (such as buffer overflows) at the compilation stage.
Elimination of Magic Numbers (M122): Page size, maximum number of retries, and allowable error bits are all defined using #define (or enum), and constants are given the U suffix to indicate they are unsigned.
Use of fixed-length integer types (M203): Instead of using environment-dependent types such as int, we have standardized to uint32_t and uint8_t from , eliminating embedded-specific data size issues.

This is automated test code using Unity (a unit testing framework) for a C language sample code demonstrating ECC processing (error correction and read retry).

To simulate hardware-dependent parts (ECC engine, voltage shift, reread), mock functions are implemented, and the hardware behavior is controlled for each test case during testing.

2. Test Code

#include "unity.h"
#include <stdint.h>
#include <stdbool.h>
#include <string.h>

/* --- Target Code Declarations (Usually included via header) --- */
/* (Assuming constants, structs, and function prototypes are declared here) */

/* --- Stub/Mock Control Variables for Testing --- */
static uint32_t mock_error_bits_sequence[10];
static uint8_t  mock_sequence_index;
static bool     mock_shift_voltage_result;
static bool     mock_read_page_result;
static uint8_t  mock_shift_call_count;

/* --- Mock Function Implementations --- */
static uint32_t mock_hw_decode_hard(const uint8_t* data, const uint8_t* parity) {
    uint32_t err = mock_error_bits_sequence[mock_sequence_index];
    if (mock_sequence_index < 9) mock_sequence_index++;
    return err;
}

static bool mock_hw_shift_read_voltage(uint8_t retry_step) {
    mock_shift_call_count++;
    return mock_shift_voltage_result;
}

static bool mock_hw_read_page_raw(uint32_t block, uint32_t page, uint8_t* data, uint8_t* parity) {
    return mock_read_page_result;
}

/* --- Test Context and Buffers --- */
static bics_ecc_context_t ctx;
static uint8_t test_data[BICS_PAGE_DATA_SIZE];
static uint8_t test_parity[BICS_PAGE_PARITY_SIZE];

/* --- Unity Setup and Teardown --- */
void setUp(void) {
    /* Initialize mock variables */
    memset(mock_error_bits_sequence, 0, sizeof(mock_error_bits_sequence));
    mock_sequence_index = 0U;
    mock_shift_voltage_result = true;
    mock_read_page_result = true;
    mock_shift_call_count = 0U;

    /* Initialize context (Register mock functions) */
    ctx.hw_engine.hw_decode_hard = mock_hw_decode_hard;
    ctx.hw_engine.hw_shift_read_voltage = mock_hw_shift_read_voltage;
    ctx.hw_engine.hw_read_page_raw = mock_hw_read_page_raw;

    memset(test_data, 0xFF, sizeof(test_data));
    memset(test_parity, 0xFF, sizeof(test_parity));
}

void tearDown(void) {}

/* --- Test Cases --- */

/* 1. Test defensive programming against invalid (NULL) parameters */
void test_bics_ecc_invalid_parameters(void) {
    TEST_ASSERT_EQUAL_INT(BICS_ECC_INVALID_PARAM, bics_ecc_encode(NULL, test_data, test_parity));
    TEST_ASSERT_EQUAL_INT(BICS_ECC_INVALID_PARAM, bics_ecc_decode_with_retry(NULL, 0, 0, test_data, test_parity));

    /* Test missing function pointers */
    bics_ecc_context_t bad_ctx = {0};
    TEST_ASSERT_EQUAL_INT(BICS_ECC_INVALID_PARAM, bics_ecc_decode_with_retry(&bad_ctx, 0, 0, test_data, test_parity));
}

/* 2. Test successful encode (parity generation) */
void test_bics_ecc_encode_success(void) {
    bics_ecc_result_t res = bics_ecc_encode(&ctx, test_data, test_parity);
    TEST_ASSERT_EQUAL_INT(BICS_ECC_SUCCESS, res);
    /* Verify mock simulation logic (cleared to 0x00) */
    TEST_ASSERT_EQUAL_UINT8(0x00, test_parity[0]);
}

/* 3. Test read decode with zero errors */
void test_bics_ecc_decode_no_error(void) {
    mock_error_bits_sequence[0] = 0U; /* 0 errors */

    bics_ecc_result_t res = bics_ecc_decode_with_retry(&ctx, 0, 0, test_data, test_parity);

    TEST_ASSERT_EQUAL_INT(BICS_ECC_SUCCESS, res);
    TEST_ASSERT_EQUAL_UINT8(0U, mock_shift_call_count); /* Ensure retry wasn't called */
}

/* 4. Test read decode with correctable errors */
void test_bics_ecc_decode_correctable_error(void) {
    mock_error_bits_sequence[0] = BICS_MAX_CORRECTABLE_BITS; /* Max tolerable limit */

    bics_ecc_result_t res = bics_ecc_decode_with_retry(&ctx, 0, 0, test_data, test_parity);

    TEST_ASSERT_EQUAL_INT(BICS_ECC_CORRECTED, res);
    TEST_ASSERT_EQUAL_UINT8(0U, mock_shift_call_count);
}

/* 5. Test successful read decode after 1 Read Retry */
void test_bics_ecc_decode_success_after_retry(void) {
    mock_error_bits_sequence[0] = BICS_MAX_CORRECTABLE_BITS + 10U; /* 1st attempt: Uncorrectable */
    mock_error_bits_sequence[1] = 50U;                             /* 2nd attempt: Correctable */

    bics_ecc_result_t res = bics_ecc_decode_with_retry(&ctx, 1, 0, test_data, test_parity);

    TEST_ASSERT_EQUAL_INT(BICS_ECC_CORRECTED, res);
    TEST_ASSERT_EQUAL_UINT8(1U, mock_shift_call_count); /* Verify voltage shifted once */
}

/* 6. Test uncorrectable errors even after reaching the max retry limit */
void test_bics_ecc_decode_uncorrectable_max_retry(void) {
    /* Setup mock to always return uncorrectable errors */
    for (int i = 0; i < 10; i++) {
        mock_error_bits_sequence[i] = BICS_MAX_CORRECTABLE_BITS + 10U;
    }

    bics_ecc_result_t res = bics_ecc_decode_with_retry(&ctx, 2, 0, test_data, test_parity);

    TEST_ASSERT_EQUAL_INT(BICS_ECC_UNCORRECTABLE, res);
    TEST_ASSERT_EQUAL_UINT8(BICS_MAX_READ_RETRY_COUNT, mock_shift_call_count); /* Verify max retries executed */
}

/* Test Runner */
int main(void) {
    UNITY_BEGIN();
    RUN_TEST(test_bics_ecc_invalid_parameters);
    RUN_TEST(test_bics_ecc_encode_success);
    RUN_TEST(test_bics_ecc_decode_no_error);
    RUN_TEST(test_bics_ecc_decode_correctable_error);
    RUN_TEST(test_bics_ecc_decode_success_after_retry);
    RUN_TEST(test_bics_ecc_decode_uncorrectable_max_retry);
    return UNITY_END();
}

Key Points of Test Code Design

Stateful Mock Implementation: The mock_error_bits_sequence array is used to return different error bit counts depending on the call count (mock_sequence_index). This perfectly simulates the dynamic hardware behavior of "error on the first attempt, but success on the second attempt after a retry."
Boundary Testing: The behavior when an error exactly at BICS_MAX_CORRECTABLE_BITS (maximum acceptable error limit) occurs, and the maximum retry limit (BICS_MAX_READ_RETRY_COUNT) is checked.
Achieving 100% C0 Coverage: The test case structure ensures that all branches are passed, including abnormal cases (NULL input), normal cases, corrective cases, and cases where the maximum retry limit is exceeded (UECC: Uncorrectable ECC Error).

BiCS FLASH memory controller wear leveling function

hk0816 — Sun, 25 Oct 2026 02:26:12 +0000

This is sample code for wear-leveling functionality for BiCS FLASH (3D NAND) controllers, along with automated test code using Unity. It complies with the Ministry of Economy, Trade and Industry's IPA's "ESCR [C language version] Ver. 3.0 (Code Practice Guide for Embedded Software)" and incorporates CERT C coding conventions and defensive programming (strict NULL checks, thorough use of const modifiers, elimination of magic numbers, and use of fixed-length integer types).

Here, we implement a dynamic wear leveling mechanism that selects the free block with the fewest erase cycles (P/E cycle count) (the least worn) to prevent uneven distribution during writing and erasing.

1. Sample code (implementation of BiCS wear leveling function)

#include <stdint.h>
#include <stdbool.h>
#include <stddef.h>

/* Constant definition (elimination of magic numbers) */
#define BICS_WL_TOTAL_BLOCKS       (8U)
#define BICS_WL_INVALID_BLOCK_ID   (0xFFFFFFFFU)

/* Block wear status metadata */
typedef struct {
    uint32_t erase_count; /* Erasure count (P/E cycle counter) */
    bool is_free;         /* free block flag */
} bics_block_wear_t;

/* Wear leveling management context */
typedef struct {
    bics_block_wear_t blocks[BICS_WL_TOTAL_BLOCKS];
} bics_wear_leveling_t;

/**
 * @brief  Initialization of the wear leveling management module
 * @note   ESCR compliant: NULL checking for pointer arguments, fixed-length integer types, and elimination of magic numbers.
 */
bool bics_wl_init(bics_wear_leveling_t* const wl) {
    if (wl == NULL) {
        return false;
    }

    for (uint32_t i = 0U; i < BICS_WL_TOTAL_BLOCKS; i++) {
        wl->blocks[i].erase_count = 10U; /* Initial number of erase cycles (example) */
        /* For example, let's use indices 6 and 7 as initial free blocks. */
        wl->blocks[i].is_free = (i >= 6U); 
    }
    return true;
}

/**
 * @brief  Select the empty block with the fewest erases (the least worn).
 *         (Core processing of dynamic wear leveling)
 * @note   ESCR compliant: Robust input validation and safe scanning.
 */
uint32_t bics_wl_select_free_block(const bics_wear_leveling_t* const wl) {
    if (wl == NULL) {
        return BICS_WL_INVALID_BLOCK_ID;
    }

    uint32_t selected_block = BICS_WL_INVALID_BLOCK_ID;
    uint32_t min_erase_count = 0xFFFFFFFFU;

    for (uint32_t i = 0U; i < BICS_WL_TOTAL_BLOCKS; i++) {
        if (wl->blocks[i].is_free) {
            if (wl->blocks[i].erase_count < min_erase_count) {
                min_erase_count = wl->blocks[i].erase_count;
                selected_block = i;
            }
        }
    }

    return selected_block;
}

/**
 * @brief  The erase count (P/E counter) is incremented when block erasure is complete.
 * @note   ESCR compliant: Boundary value checking and argument validation
 */
bool bics_wl_increment_erase_count(bics_wear_leveling_t* const wl, uint32_t block_id) {
    if (wl == NULL) {
        return false;
    }
    if (block_id >= BICS_WL_TOTAL_BLOCKS) {
        return false;
    }

    wl->blocks[block_id].erase_count++;
    return true;
}

/**
 * @brief  Change the block's empty state.
 */
bool bics_wl_set_block_free_status(bics_wear_leveling_t* const wl, uint32_t block_id, bool is_free) {
    if (wl == NULL) {
        return false;
    }
    if (block_id >= BICS_WL_TOTAL_BLOCKS) {
        return false;
    }

    wl->blocks[block_id].is_free = is_free;
    return true;
}

2. Automated test code using Unity

#include "unity.h"

static bics_wear_leveling_t wl_inst;

/* Unity standard setup */
void setUp(void) {
    bool init_res = bics_wl_init(&wl_inst);
    TEST_ASSERT_TRUE(init_res);
}

void tearDown(void) {
    /* Cleanup as needed */
}

/* Test Case 1: Verification that the empty block with the fewest erase counts is correctly selected (Dynamic Wear Leveling) */
void test_bics_wl_select_free_block_min_wear(void) {
    /* Leave blocks 6 and 7 empty to create a difference in the number of times they are cleared. */
    wl_inst.blocks[6].is_free = true;
    wl_inst.blocks[6].erase_count = 50U; /* A lot of wear */

    wl_inst.blocks[7].is_free = true;
    wl_inst.blocks[7].erase_count = 10U; /* Low wear (this is the one to choose) */

    uint32_t selected = bics_wl_select_free_block(&wl_inst);

    TEST_ASSERT_EQUAL_UINT32(7U, selected);
}

/* Test Case 2: Boundary Value Test in the Case Where No Empty Blocks Exist */
void test_bics_wl_select_free_block_no_free(void) {
    /* Make all blocks empty. */
    for (uint32_t i = 0U; i < BICS_WL_TOTAL_BLOCKS; i++) {
        wl_inst.blocks[i].is_free = false;
    }

    uint32_t selected = bics_wl_select_free_block(&wl_inst);

    TEST_ASSERT_EQUAL_UINT32(BICS_WL_INVALID_BLOCK_ID, selected);
}

/* Test Case 3: Verification of ESCR-compliant defensive programming (NULL safety and out-of-range indexes) and erasure counters. */
void test_bics_wl_safety_and_increment(void) {
    /* Checking the safety of NULL pointers */
    TEST_ASSERT_EQUAL_UINT32(BICS_WL_INVALID_BLOCK_ID, bics_wl_select_free_block(NULL));
    TEST_ASSERT_FALSE(bics_wl_increment_erase_count(NULL, 0U));
    TEST_ASSERT_FALSE(bics_wl_set_block_free_status(NULL, 0U, true));

    /* Checking for guards against out-of-range indexes */
    TEST_ASSERT_FALSE(bics_wl_increment_erase_count(&wl_inst, BICS_WL_TOTAL_BLOCKS));
    TEST_ASSERT_FALSE(bics_wl_set_block_free_status(&wl_inst, BICS_WL_TOTAL_BLOCKS, true));

    /* Verification of normal increment process */
    uint32_t initial_count = wl_inst.blocks[0].erase_count;
    bool inc_res = bics_wl_increment_erase_count(&wl_inst, 0U);

    TEST_ASSERT_TRUE(inc_res);
    TEST_ASSERT_EQUAL_UINT32(initial_count + 1U, wl_inst.blocks[0].erase_count);
}

/* test runner */
int main(void) {
    UNITY_BEGIN();

    RUN_TEST(test_bics_wl_select_free_block_min_wear);
    RUN_TEST(test_bics_wl_select_free_block_no_free);
    RUN_TEST(test_bics_wl_safety_and_increment);

    return UNITY_END();
}