5 UVM Patterns Every Verification Engineer Should Know

mritunjay bihari singh — Fri, 24 Jul 2026 06:55:46 +0000

Production-Tested Patterns That Scale from IP Blocks to SoCs
Introduction
Over the past 8 years verifying everything from cache coherency controllers to high-speed interconnects, I've noticed that most verification headaches come from not knowing these five UVM patterns. They're not flashy. They won't make your testbench run faster. But they'll make the difference between a clean coverage closure in 6 weeks versus a nightmare that drags 16 weeks past tape-out.

This isn't a tutorial. This assumes you know UVM basics. This is about how professionals actually structure testbenches when the stakes are real.

Pattern 1: The Layered Agent Architecture
(Why Your Monitor Shouldn't Drive, and Your Driver Shouldn't Monitor)
The Problem
Ninety-nine percent of first-time UVM code I review has this sin:

// ❌ WRONG: Driver trying to do everything
class axi_driver extends uvm_driver #(axi_transaction);
virtual axi_if vif;

task run_phase(uvm_phase phase);
    forever begin
        seq_item_port.get_next_item(item);

        // Driving
        vif.awaddr <= item.addr;
        vif.awlen <= item.len;

        // ⚠️ Also monitoring back???
        // Checking slave response
        if (vif.bvalid) begin
            // This is a MONITOR's job, not driver's!
            `uvm_info("DRV", $sformatf("Write complete: %0h", item.addr), UVM_MEDIUM)
        end

        seq_item_port.item_done(item);
    end
endtask

endclass
Why this is toxic:

Tight coupling – Driver can't be tested independently from monitor
Race conditions – Driver writes data, then immediately monitors its own write (timing issues)
Scoreboard confusion – Monitor is supposed to collect gold truth; now it's mixed with driver implementation
Reusability nightmare – Can't plug this driver into different testbenches
The Pattern: Layered, Separate Concerns
// ✅ CORRECT: Driver only drives
class axi_driver extends uvm_driver #(axi_transaction);
virtual axi_if vif;

task run_phase(uvm_phase phase);
    forever begin
        seq_item_port.get_next_item(item);
        drive_write_transaction(item);
        seq_item_port.item_done(item);
    end
endtask

// ONLY driving logic here
task drive_write_transaction(axi_transaction item);
    @(posedge vif.clk);
    vif.awvalid <= 1'b1;
    vif.awaddr  <= item.addr;
    vif.awlen   <= item.len;
    vif.awsize  <= item.size;

    // Wait for slave to accept
    wait(vif.awready);
    @(posedge vif.clk);
    vif.awvalid <= 1'b0;
endtask

endclass

// ✅ CORRECT: Monitor only monitors (passive)
class axi_monitor extends uvm_monitor;
virtual axi_if vif;
uvm_analysis_port #(axi_transaction) ap;

task run_phase(uvm_phase phase);
    forever begin
        @(posedge vif.awvalid && posedge vif.awready);

        // Purely passive observation
        axi_transaction item = axi_transaction::type_id::create("item");
        item.addr = vif.awaddr;
        item.len  = vif.awlen;
        item.size = vif.awsize;

        // Send to analysis port (for scoreboard)
        ap.write(item);
    end
endtask

endclass
Why This Works at Scale
When I was verifying the interconnect on a 32-core SoC:

Isolation meant I could test the driver with a simple slave (5 hours to debug driver issues)
Reuse meant I used the same driver on 4 different interconnect variants
Scoreboard clarity – I knew EXACTLY which transactions came from the monitor (observation) vs. the driver (stimulus)
Real win: Found a subtle slave-to-driver handshake bug only because the monitor was purely passive. If they were tangled, I'd never have caught it.

DEV Community: mritunjay bihari singh

5 UVM Patterns Every Verification Engineer Should Know