DEV Community: Sanakousar

LPC 2148 ARM CPU PART-2

Sanakousar — Thu, 15 Feb 2024 12:36:42 +0000

Hello Readers,
My name is Sana, and I’m working at Luxoft India as a Junior Software Developer. Luxoft has given me several opportunities to work on numerous projects, which has stimulated me to discuss the crucial strategies concerned in ARM Embedded system. Here we will speak about the in-detail LPC 2148 ARM CPU.

Introduction
The LPC2148 family of microcontrollers, developed by NXP Semiconductors, are 32-bit devices based on the ARM7TDMI-S core. They offer a compelling combination of processing power, memory capacity, and peripheral features, making them well-suited for a wide range of embedded applications. For censorious code size applications, alternative 16-bit Thumb mode decrease code by more than 30 % with minimal performance penalty. Due to the small size and low power consumption, LPC2148 is perfect for applications where miniaturization is an essential requirement, like that access control and point-of-sale. Serial communications interfaces made these devices very good suitable fit for communication gateway and protocol transfers, soft modems, voice recognition and low end imaging, providing both high buffer size and big processing power. several 32-bit timers, level sensitive to external interrupt pins build these microcontrollers particularly fitted for industrial control and medical systems.

Features of LPC2148 Microcontroller

16/32-bit ARM7TDMI-S microcontroller in a small QFP64 package.
8 to 40 KB of on-chip static RAM and 32 to 512 KB on-chip flash program memory.128 bit broad interface/accelerator enables high speed 60 MHz operation.
In-System or In-Application Programming (ISP/IAP) through on-chip boot-loader software. One flash sector or full chip erase 400 ms and programming of 256 bytes in 1 ms.
USB 2.0 Full Speed controllable1 Device Controller with 2 KB of endpoint RAM. LPC2148 provides 8 KB of on-chip RAM available to USB by DMA.
Two 10-bit A/D converters provide a complete of 6/14 analog inputs, with exchange times as low as 2.44 micros per channel.
Single 10-bit D/A converter allocate variable analog output.
Two 32-bit timers/external event counters (with 4 captures and 4 compare channels each), PWM unit (six outputs) watchdog.
Low power real-time clock with independent power and allocated 32 kHz clock input.
Multiple serial interfaces which includes two UARTs (16C550), two Fast I2C-buses (400 Kbit/s),
SPI and SSP with buffering variables data length capabilities.
Vectored interrupt controller (VIC) with configurable priorities along with vector addresses.
Processor wake-up from power-down mode through external interrupt or BOD.
Single power supply chip by POR and BOD circuits

Pin Description of 2148 CPU
The Pin diagram of a LPC 2148 is as shown in the figure. It is having 16 pins at each side and total of 64 pins. Most of the pins are multiplexed to do the multi functioning operation.

Operation of LPC 2148 Microcontroller

The ARM7 Local Bus connected to on-chip memory controllers.

The AMBA Advanced High-performance Bus (AHB) for connected to the interrupt controller, and

The ARM Peripheral Bus (APB, a compatible superset of ARM's AMBA Advanced Peripheral Bus) purposed for connection to on-chip peripheral task.

The LPC2148 configure the ARM7TDMI-S processor in little-endian byte order. AHB peripherals assign 2-megabyte range of addresses at extremely top of the 4 gigabyte ARM memory space. Every AHB peripheral is assign a 16 KB address space inside the AHB address space. LPC2148 peripherals function (other than the interrupt controller) is connected to the APB bus. The AHB to APB bridge connected the APB bus to the AHB bus. APB peripherals are also all assign a 2 megabyte range of addresses, start at the 3.5 gigabyte address point. Each one APB peripheral is assign a 16 kB address space inside the APB address space.

The connection of on-chip peripheral to device pins is controlled by a pin connect block. This should be configured on software to fit particular application requirements for the use of peripheral function and pins.

The ARM7TDMI-S is a general purpose 32-bit microprocessor, which provide high level performance and very low power utilization. The ARM architecture is based on Reduced Instruction Set Computer (RISC) principles, and instruction set and associated decode mechanism are more simpler than those of micro programmed Complex Instruction Set Computers. This simple results in a high instruction throughput and expert real-time interrupt feedback from a small and cost-effective processor core.

Pipeline techniques are in work so that all parts of the processing and memory systems can work continuously. Typically, while instruction is being executed, its successor being decoded, and a third instruction is being get from memory.

The ARM7TDMI-S processor also employs a most special architectural strategy called a THUMB, which makes it similarly suitable to large-volume applications with its memory limitation or applications where code density is a problem.

The character behind THUMB is that of a reduced instruction set. Basically, the ARM7TDMI-S processor has two type of instruction sets:
• The standard 32-bit ARM instruction set.
• A 16-bit THUMB instruction set.

The THUMB set’s 16-bit a instruction length permit it arrived at twice the density of standard ARM code while retaining all of to the ARM’s performance advantages over a traditional 16-bit processor using 16-bit registers. This is achievable because THUMB code operates on same 32-bit register set as ARM code.

ARM EMBEDDED SYSTEM AND ARM PROCESSOR FUNDAMENTALS - PART 3

Sanakousar — Thu, 15 Feb 2024 10:39:39 +0000

Introduction
The ARM processor core is a key component of most successful 32-bit embedded systems. ARM cores are used in mobile phones, organizers, and a multitude of everyday portable consumer devices.
The first ARM1 prototype was designed in 1985. Over 1 billion ARM processors had been delivered worldwide by the end of 2001. The ARM Company bases their success on a simple and powerful original design, which continues to improve today through the constant technical innovation. In fact, the ARM core is not a single core, but a whole family of designs sharing similar design principle and a common instruction set.
In this Article we discuss initially an overview of ARM design philosophy, an example of embedded device and its typical hardware and software technologies that surrounded an ARM processor. Then we discuss a brief description of ARM core model with its registers, mode and pipeline.

ARM Design Philosophy

There are many special features that have driven the ARM Processor design.
They are as follow:

Power consumption
Code density
Price
Size
Debug technology
Core processor

The above listed parameters for the ARM designs philosophy is clearly illustrated below.

Portable embedded systems require battery power. The ARM processor has been designed to reduce power consumption. It is important for applications such as mobile phones and personal digital assistants.

Embedded systems are price sensitive
And use slow and low-cost memory devices. For high volume Application to get substantial savings essential for high-volume applications like digital cameras, every cent has to be accounted for in the design.

And, reduce the area of embedded processor; smaller the area used by the embedded processor, reduced cost of the design and manufacturing for the entire product.

ARM has equipped its processors with hardware-level debugging mechanisms to provide software engineers with a clear view of code execution, streamlining problem identification and resolution.

The integrated debugging tools within ARM processors empower software engineers to delve deeper into code behavior during execution, fostering a more efficient and streamlined debugging workflow.

The ARM core is not a pure RISC architecture because of the ARM core adopts the RISC philosophy. This flexibility arguably forms its core strength, allowing it to excel in real-world applications

Operation:

Data items are set in the register file called as storage bank made up of 32-bit registers. Since the ARM core is a 32-bit processor, most of the instruction treat the register as holding signed or unsigned 32- bit values. The sign extends hardware transform signed 8-bit or 16-bit numbers to 32-bit values as they are read from memory and arranged in register.
ARM instruction typically have two source register i.e., Rn and Rm, and Single result or destination register Rd. Source operands are read from register file using internal buses A and B respectively. The ALU (arithmetic logic unit) or MAC (multiply-accumulate unit) takes the register values Rn and Rm from the A and B buses and evaluates a result.
Data processing instruction write the result to Rd directly to the register file. Load and Store instructions use ALU to generate an address to be hold in the address register and broadcast on the address bus.
One important feature of the ARM is that register Rm alternately can be preprocessed in barrel shifter before it enters the ALU. Together barrel shifter and ALU is used to calculate a wide range of expression and addresses.
After passing through the functional elements, the result in the Rd is written back to register file using the result bus.
For Load and Store instruction the incrementer updates the address register before the core reads or writes next register value from or to next sequential memory location. The processor continues executing instruction until an exception or interrupt changes normal execution flow.

Embedded System Software

To derive an embedded system the software is needed. Figure shows the block diagram of typical software components required to control an embedded device. It mainly consists of four typical software components. Each software component in the stack uses a high level of abstraction to individual the code from the hardware device.
The first code To ensure a smooth transition to the operating system, the board first executes target-specific initialization code, which establishes a baseline hardware configuration.
An infrastructure to control application is being provided by the operating system. The operating system also handle hardware system resources. Many embedded system do not have a full operating system but a simple task scheduler that is either event or poll driven.
Device drivers act as a bridge, offering a unified software interface for interacting with the various peripherals attached to the hardware. Applications, such as a diary app on a mobile phone, carry out specific tasks that fulfill the device's intended purpose. The operating system acts as a coordinating the execution of multiple applications that may be running concurrently on a single device. Software components can reside in either ROM (firmware) for permanent storage, like the initialization code, or RAM for temporary execution.

Conclusion

LPC 2148 ARM CPU

Sanakousar — Sat, 27 Jan 2024 15:49:41 +0000

Introduction
The LPC2148 microcontrollers are based on a 32-bit ARM7TDMI-S CPU with real-time emulation and embedded trace support, that combines the microcontroller with embedded high speed flash memory ranging from 32 kB to 512 kB. A 128-bit memory interface and special accelerator architecture enable 32-bit code execution on maximum clock rate. For censorious code size applications, alternative 16-bit Thumb mode decrease code by more than 30 % with minimal performance penalty. Due to the small size and low power consumption, LPC2148 is perfect for applications where miniaturization is an essential requirement, like that access control and point-of-sale. A blend of serial communications interfaces ranging from a USB 2.0 Full Speed device, multiple UARTs, SPI, SSP to I2Cs, on-chip SRAM of 8 kB up to 40 kB, make these devices very good suitable fit for communication gateways and protocol converters, soft modems, voice recognition and low end imaging, providing both large buffer size and big processing power. several 32-bit timers, single / dual 10-bit ADC(s) and DAC, PWM channels and 45 fast GPIO lines with up to 9 edge or level sensitive external interrupt pins build these microcontrollers particularly fitted for industrial control and medical systems.

Features of LPC2148 Microcontroller

16/32-bit ARM7TDMI-S microcontroller in a small QFP64 package.
8 to 40 KB of on-chip static RAM and 32 to 512 KB on-chip flash program memory.128 bit broad interface/accelerator enables high speed 60 MHz operation.
In-System or In-Application Programming (ISP/IAP) through on-chip boot-loader software. One flash sector or full chip erase 400 ms and programming of 256 bytes in 1 ms.
USB 2.0 Full Speed controllable1 Device Controller with 2 KB of endpoint RAM. LPC2148 provides 8 KB of on-chip RAM available to USB by DMA.
Two 10-bit A/D converters provide a complete of 6/14 analog inputs, with exchange times as low as 2.44 micros per channel.
Single 10-bit D/A converter allocate variable analog output.
Two 32-bit timers/external event counters (with 4 captures and 4 compare channels each), PWM unit (six outputs) watchdog.
Low power real-time clock with independent power and allocated 32 kHz clock input.
Multiple serial interfaces which includes two UARTs (16C550), two Fast I2C-buses (400 Kbit/s),
SPI and SSP with buffering variables data length capabilities.
Vectored interrupt controller (VIC) with configurable priorities along with vector addresses.
Up to 45 of 5 V tolerant fast general purpose I/O pins in a small LQFP64 package.
Processor wake-up from power-down mode through external interrupt or BOD.
Single power supply chip by POR and BOD circuits
60 MHz maximum CPU clock accessible from programmable on-chip PLL with settling time of 100us.

Block Diagram of LPC 2148 Microcontroller
As shown in the below figure the LPC2148 consist of an ARM7TDMIS CPU with emulation support,

The ARM7 Local Bus connected to on-chip memory controllers.
The AMBA Advanced High-performance Bus (AHB) for connected to the interrupt controller, and
The ARM Peripheral Bus (APB, a compatible superset of ARM's AMBA Advanced Peripheral Bus) purposed for connection to on-chip peripheral task.

The LPC2148 configure the ARM7TDMI-S processor in little-endian byte order. AHB peripherals assign a 2-megabyte range of addresses at the extremely top of the 4 gigabyte ARM memory space. Every AHB peripheral is assign a 16 KB address space inside the AHB address space. LPC2148 peripheral functions (other than the interrupt controller) are connected to APB bus. The AHB to APB bridge connected the APB bus to the AHB bus. APB peripherals are also all assign a 2 megabyte range of addresses, start at the 3.5 gigabyte address point. Each one APB peripheral is assign a 16 kB address space inside the APB address space.

The ARM7TDMI-S is a general purpose 32-bit microprocessor, which provide high level performance and very low power utilization. The ARM architecture is build on Reduced Instruction Set Computer (RISC) principles, and the instruction set and associated decode mechanism are much simpler than those of micro programmed Complex Instruction Set Computers. This simple results in a high instruction throughput and expert real-time interrupt feedback from a small and cost-effective processor core.

The ARM7TDMI-S processor also employs a special architectural strategy called as THUMB, which makes it ideally suitable to high-volume applications with memory limitation or applications where code density is a problem.

The crucial character behind THUMB is that of a super-reduced instruction set. Basically, the ARM7TDMI-S processor has two type of instruction sets:
• The standard 32-bit ARM instruction set.
• A 16-bit THUMB instruction set.

The THUMB set’s 16-bit instruction length permit it to arrive at twice the density of standard ARM code while retaining almost all of the ARM’s performance benefit over a traditional 16-bit processor using 16-bit registers. This is achievable because THUMB code operates on same 32-bit register set as ARM code.

ARM EMBEDDED SYSTEM AND ARM PROCESSOR FUNDAMENTALS - PART 2

Sanakousar — Wed, 24 Jan 2024 18:36:24 +0000

Introduction
The ARM processor core is a key component of most successful 32-bit embedded systems. ARM cores are widely used in mobile phones, organizers, and a multitude of other everyday portable consumer devices.
The first ARM1 prototype was designed in 1985. Over 1 billion ARM processors had been delivered worldwide by the end of 2001. The ARM Company bases their success on a simple and powerful original design, which continues to improve today through the constant technical innovation. In fact, the ARM core is not a single core, but a whole family of designs sharing similar design principle and a common instruction set.
In this Article we discuss initially an overview of ARM design philosophy, an example of embedded device and its typical hardware and software technologies that surrounded an ARM processor. Then we discuss a brief description of ARM core model with its registers, mode and pipeline.

ARM Core Data Flow Model
The block diagram of an ARM core has functional units such as ALU, Address registers, Register file, Barrel shifter, MAC and Instruction decoder. All these functional blocks are connected by data buses, as shown in Figure, where the arrows represent the flow of data, the lines represent the buses, and the blocks represent either an function unit or a storage area. The figure shows not only the flow of data but also the abstract component that makes up an ARM core.
Data enter the processor core through the Data bus. The data may be instruction to be executed or a data element. Figure shows a Von Neumann implementation of the ARM in which the data item and instruction share the same bus. In contrast, Harvard implementation of the ARM use two separate buses, one for the data items and other for the instructions.
The instruction decoder translates the instructions into the binary form (execute form) before they are executed. One and all instruction executed be connected to a particular instruction set.
The ARM processor uses Load-Store architecture. This means it hold two instruction types for transferring data in and out of the processor. They are

Load
Store

The load-store architecture is used on the ARM processor. Load instructions copy data from memory to register in the core, and conversely the store instruction copy data from register to memory. There are no data processing instructions that directly operate data in memory. Thus, data processing is carried out merely in registers.

Operation:

Data items are set in the register file called as storage bank made up of 32-bit registers. Since the ARM core is a 32-bit processor, most of the instruction treat the register as holding signed or unsigned 32- bit values. The sign extends hardware transform signed 8-bit or 16-bit numbers to 32-bit values as they are read from memory and arranged in register.
ARM instruction typically have two source register i.e., Rn and Rm, and Single result or destination register Rd. Source operands are read from register file using internal buses A and B respectively. The ALU (arithmetic logic unit) or MAC (multiply-accumulate unit) takes the register values Rn and Rm from the A and B buses and evaluates a result.
Data processing instruction write the result to Rd directly to the register file. Load and Store instructions use ALU to generate an address to be hold in the address register and broadcast on the address bus.
One important feature of the ARM is that register Rm alternately can be preprocessed in barrel shifter before it enters the ALU. Together barrel shifter and ALU is used to calculate a wide range of expression and addresses.
After passing through the functional elements, the result in the Rd is written back to register file using the result bus.
For Load and Store instruction the incrementer updates the address register before the core reads or writes next register value from or to next sequential memory location. The processor continues executing instruction until an exception or interrupt changes normal execution flow.

ARM Registers
General purpose registers carry either data or an address.
They are identified with the letter ‘r’ prefixed to register number. For example, register 4 is represent as r4. The processor can work in seven different modes. The below figure shows the active registers obtain in the user mode.

All registers are shown are 32 bit in size.

● There are totally 18 active registers
● 16 data registers – r0 to r15
● 2 process status registers
● r13, r14, r15 have special functions

● r13 – stack pointer (sp) used as the stack pointer and stores the top of the stack in the current processor mode
● r14 – link register (lr) where the core holds the return address whenever it calls a subroutine.
● r15 – program counter (pc) and contains the address of the next instruction to be that needs to be executed.
● r13 and r14 can also be used as general purpose register which can be particularly useful since these registers are banked during processor mode change.
● the registers r0 to r13 are orthogonal. Any instruction that you can apply to r0, you can equally apply other registers.
●there are instructions that treat as r14 and r15 in a special way.

In addition to 16 data registers, there are two type of program status registers. They are;

CPSR (current program status register)
SPSR (saved program status register) The register file contains all the register available to a programmer. Which registers are visible to the programmer relate to the current mode of the processor.

ARM EMBEDDED SYSTEM AND ARM PROCESSOR FUNDAMENTALS

Sanakousar — Mon, 08 Jan 2024 08:05:09 +0000

ARM Design Philosophy
There are many special features that have driven the ARM Processor design.
They are as follow:

Power consumption
Code density
Price
Size
Debug technology
Core processor

The above listed parameters for the ARM designs philosophy is clearly illustrated below.

Portable embedded systems require battery power. The ARM processor has been specially designed to reduce power consumption. It is important for applications such as mobile phones and personal digital assistants.

High code density is another crucial feature, since embedded systems have limited memory due to cost and physical size restrictions. It is necessary for applications such as mobile phones and mass storage devices.

And, reduce the area of embedded processor; smaller the area used by the embedded processor, reduced cost of the design and manufacturing for the entire product.

ARM has equipped its processors with hardware-level debugging mechanisms to provide software engineers with a clear view of code execution, streamlining problem identification and resolution.

The integrated debugging tools within ARM processors empower software engineers to delve deeper into code behavior during execution, fostering a more efficient and streamlined debugging workflow.

The ARM core is not a pure RISC architecture because of the ARM core adopts the RISC philosophy. This flexibility arguably forms its core strength, allowing it to excel in real-world applications.

Embedded System Hardware

From small sensors found on a production line, to the real-time control systems used on a NASA space probe are controlled by the Embedded systems. All devices use a combination of software and hardware components.

The above Figure shows a typical embedded device based on an ARM core. Each block does specific function. The lines connecting the blocks are the buses carrying data. The embedded System hardware is divided into four main hardware components. They are;

ARM processor
Controllers
Peripheral and
Bus
The embedded device is mainly controlled by the ARM processor. Different version of ARM processor are available to suit the desire operating characteristics. An ARM Processor comprises a core and Peripheral. The core is an execution engine that processes instruction and manipulates data. The peripheral are the surrounding components that interface it with a bus, such as memory management and caches.
Controller are mainly used to coordinate important functional blocks of the System. Interrupt and memory controllers are the two commonly used controller.
The peripheral provide all the input-output capability external to the chip and are responsible for the uniqueness of the embedded device.
A bus is used to communicate between different parts of the device i.e., to exchange the data between the device.

Embedded System Software

Conclusion
The embedded device is mainly controlled by the ARM processor. Different version of ARM processor are available to suit the desire operating characteristics. An ARM Processor comprises a core and Peripheral. The core is an execution engine that processes instruction and manipulates data. The peripheral are the surrounding components that interface it with a bus, such as memory management and caches.

This is part 1 of the ARM Embedded System

This will be continued in the next article, including examples. Please let me know if you have any queries.
Thanks for reading.

AUTOSAR MCAL PARTT-2

Sanakousar — Fri, 29 Dec 2023 05:58:05 +0000

Hello Readers,
My name is Sana, and I’m working at Luxoft India as a Junior Software Developer. Luxoft has given me several opportunities to work on numerous projects, which has stimulated me to discuss the crucial strategies concerned in AUTOSAR MCAL. Here we will speak about the in-detail AUTOSAR MCAL Part2.

Introduction
MCAL stand for Microcontroller Abstraction Layer. The MCAL layer is one of the four layers of the AUTOSAR architecture, the other three are Application Layer, the RTE Layer, and the ECU Abstraction Layer. MCAL is the lowest layer of BSW(Basic Software). It contains driver with direct access to microcontroller , internal peripheral and memory mapped microcontroller external device. Its act as bridge between Application software and hardware. MCAL is hardware specific layer that ensures a standard interface to the basic software. Its makes higher software layer independent of microcontroller.

The Microcontroller Abstraction Layer sub divided into four parts:

Controller Driver
Memory Driver
Com Driver
I/O Driver

Microcontroller Driver
A microcontroller driver is a software module that provides an interface to the hardware peripherals of a microcontroller. It allows the upper software layers to access the peripherals without having to know the specific details of the hardware.

GPT Driver:
GPT (General Purpose Timer) device driver uses on-chip microcontroller timer. Initializes GPT and performs timer count. The GPT driver is an essential part of any embedded system that can accurately measure time and generate interrupts at precise intervals.
WDG Driver:
WDG (Watchdog) Driver, The primary purpose of a watchdog timer is to detect and recover from software or system failures, such as code execution errors, infinite loops, or other unexpected behavior.it is a hardware peripheral that is used to prevent software errors from causing the system to become unresponsive.
• The watchdog driver is responsible for initializing, configuring, and triggering watchdog timer.
• The watchdog driver produce an API that can be used by the upper software layers to interface with the watchdog timer.
MCU (Micro Controller Unit):
MCU (Micro Controller Unit) Driver module provides interface for accessing the microcontroller, including its core functions and its integrated peripherals (e.g., ADC, PWM, CAN, SPI, and FLS).Its designed to perform specific operation in an embedded system.
Memory Driver
Memory Drivers provides standardized interface for get back the memory of the ECU, which includes RAM, ROM, and flash memory.

The memory driver provides the following services:

Initialization of the memory devices
Reading and writing to memory
Erasing memory
Managing memory protection
Testing the memory devices

Flash Driver: Flash drivers are an essential part of any system that uses flash memory. This will help to make and act like that our software is portable, reliable, and productive. Its initialize Flash and reads/writes to Flash memory.

Communication Drivers
The communication driver in MCAL modules that handle communication protocols and provide interfaces between different Electronic Control Units (ECUs) within the vehicle or with external devices.
This module Provides a standardized interface for retrieve the communication interfaces used in the ECU, such as CAN, LIN, and FlexRay.

CAN (Controller Area Network):
A widely used communication protocol in automotive applications for inter-ECU communication. It allows multiple ECUs to communicate with each other over a shared bus. Driver that initializes and performs CAN input/output. CAN is multi master anyone can send the data. Its carries 8 bytes for traditional CAN.
LIN (Local Interconnect Network):
A simple and cost-effective communication protocol commonly used for communication with less critical ECUs in the vehicle. Its cost effective and low-end multiplexed communication in automotive networks. It use the serial universal asynchronous receiver/transmitter (UART) embedded into most modern low-cost 8-bit microcontrollers.
FlexRay:
A high-speed communication protocol used in advanced driver assistance systems (ADAS) and other safety-critical applications. Its single network cable run that connects multiple ECUs together.
Its initializes FlexRay and performs FlexRay input/output.
Ethernet:
Ethernet is becoming more popular for in-vehicle communication due to its higher data rates and ability to handle multiple protocols simultaneously. Its used for sending data along with cables is faster, more reliable, and more secure than sending it as radio waves, as Wi-Fi does. With the increasing complication of automotive systems.

I/O Driver:
An I/O driver in MCAL is a software module that provides access to the microcontroller's (MCU) I/O ports. It abstracts physical layer of I/O port, making it simple for the upper software layer to interconnect with them.

ICU(Input Capture Unit):
The ICU is software module in MCAL layer that handles the capture of input signals, usually related time measurements, on a microcontroller. The primary purpose of the ICU is to exactly capture the time of particular events or pulses that occur on external pins or signals connected to microcontroller.
PWM (Pulse Width Modulation):
PWM driver is software module responsible for generating and controlling PWM signals on a microcontroller. The objective of deriving PWM (Pulse Width Modulation) using timers and interrupts is to achieve exact control of the output pulse width and frequency. PWM is a commonly used technique in embedded systems and electronic devices to control the speed of motors, brightness of LEDs, Heating and cooling control, and various other applications where precise control of the output signal is required.
ADC Driver:

ADC allows the microcontroller to convert analog signals (voltage) to digital signals from sensors, transducers, and other analog devices into digital values that can be processed and make use of the digital circuitry of the microcontroller.
The ADC driver is being an essential part of an automotive applications, where it is used to read analog signals from various sensors, such as temperature sensors, pressure sensors, position sensors, and other transducers.

Conclusion
In this Article I have Tried to explain about Autosar MCAL. Please let me know if you have any queries.

Thanks for reading.

ARM EMBEDDED SYSTEM

Sanakousar — Tue, 26 Dec 2023 19:16:33 +0000

ARM Design Philosophy
There are many special features that have driven the ARM Processor design.
They are as follow:

Power consumption
Code density
Price
Size
Debug technology
Core processor

The above listed parameters for the ARM designs philosophy is clearly illustrated below.

Portable embedded systems require battery power. The ARM processor has been specially designed to reduce power consumption. It is essential for applications such as mobile phones and personal digital assistants (PDAs).
High code density is another major feature, since embedded systems have limited memory due to cost and/or physical size restrictions. It is essential for applications such as mobile phones and mass storage devices.
Embedded systems are price sensitive
And use slow and low-cost memory devices. For high volume Application to get substantial savings essential for high-volume applications like digital cameras, every cent has to be accounted for in the design.

And, reduce the area of embedded processor; smaller the area used by the embedded processor, reduced cost of the design and manufacturing for the entire product.

ARM has equipped its processors with hardware-level debugging mechanisms to provide software engineers with a clear view of code execution, streamlining problem identification and resolution.
The integrated debugging tools within ARM processors empower software engineers to delve deeper into code behavior during execution, fostering a more efficient and streamlined debugging workflow.
The ARM core is not a pure RISC architecture because of the ARM core adopts a pragmatic approach to the RISC philosophy. While not strictly adhering to a purist ideal, this flexibility arguably forms its core strength, allowing it to excel in real-world applications.

Instruction Set for Embedded Systems
The features of ARM instruction set which makes the ARM suitable for embedded system are as follows:

Variable cycle execution for certain instructions
Enhance instructions
Thumb 16-bit instruction set
Conditional execution
Inline barrel shifter leading more complex instructions.
Some of the ARM instructions execute in a single cycle but few instructions take more than one cycle.
ARM instructions are designed for flexibility in execution time, with some completing in a single cycle while others take longer, depending on the complexity of the task. For example, load-store-multiple instructions, which transfer multiple registers, can adjust their execution time based on the number of registers involved. This adaptability enhances both performance and code density, especially when dealing with sequential memory addresses.
ARM processors incorporate an inline barrel shifter, a hardware component can manipulate data within registers before it's used by an instruction. This preprocessing capability increase the power of many instructions, leading to improved core performance and more compact code.
The combination of these features has solidified ARM processors as one of the most widely adopted 32-bit embedded processor cores. Their adaptable execution, compact code options, efficient data handling, streamlined execution, and enhanced processing capabilities make them a preferred choice for a diverse range of embedded applications.

These additional features have made the ARM processor one of the most large commonly used 32-bit embedded processor cores.

Embedded System Hardware

ARM processor
Controllers
Peripheral and
Bus

The embedded device is mainly controlled by the ARM processor. Different version of ARM processor are available to suit the desire operating characteristics. An ARM Processor comprises a core and Peripheral. The core is an execution engine that processes instruction and manipulates data. The peripheral are the surrounding components that interface it with a bus, such as memory management and caches.
Controller are mainly used to coordinate important functional blocks of the System. Interrupt and memory controllers are the two commonly used controller.
The peripheral provide all the input-output capability external to the chip and are responsible for the uniqueness of the embedded device.
A bus is used to communicate between different parts of the device i.e., to exchange the data between the device.

This is part 1 of the ARM Embedded System

This will be continued in the next article, including examples. Please let me know if you have any queries.
Thanks for reading.

BASICS OF AUTOSAR MCAL

Sanakousar — Thu, 07 Dec 2023 07:25:33 +0000

Hello Readers,

My name is Sana, and I work at Luxoft India as a Junior Software Developer. Luxoft has given me several opportunities to work on various projects, which has inspired me to learn the essential processes involved in developing AUTOSAR Modulеs and Add-Ons in AUTOSAR MCAL.

The Microcontroller Abstraction Layer sub divided into four parts:

Controller Driver
Memory Driver
Com Driver
I/O Driver

How does MCAL Work
MCAL layer is the set of software modules that provide a standardized interface for accessing the microcontroller and other hardware components of the ECU. MCAL contains drivers for the microcontroller, communication interfaces, timers, and other peripherals.
MCAL layer provides set of services that can be accessed by the application software by the AUTOSAR interface. These services consist of functions for initializing the hardware, configuring the hardware, and controlling the hardware. it can be used to customize the behavior of the software modules.

How MCAL layer play important role in AUTOSAR
The MCAL layer act as important role in automotive software development. By providing a standardized interface for accessing the hardware, it allows the application software to be independent of the specific microcontroller and hardware components used in the ECU. This layer makes it easy to develop, test, and maintain the software. Hardware upgrades can be implemented without the need to modify the application software.

Software Architecture of MCAL

MCAL provides a collection of specialized software components, each tailored to a specific hardware function. These components, known as drivers, interact directly with the corresponding on-chip peripheral hardware. For example, CAN Driver will ensure that CAN messages can be received and transmitted by the MCU.

Modules in MCAL
MCAL each module is responsible for abstracting different hardware components of the ECU.

Microcontroller Driver

MCU Driver : MCU (Micro Controller Unit) Driver module provides a standardized interface for accessing the microcontroller, including its core functions and its integrated peripherals (e.g., ADC, PWM, CAN, SPI, and FLS).MCU (Micro Controller Unit) Driver, this device driver helps configure MCU settings, initializes clock and helps configure power mode settings.
GPT Driver: GPT (General Purpose Timer) driver allows you to configure and use the General Purpose Timer available in the microcontroller for various timing and measurement tasks, such as generating delays, managing input captures, or creating periodic events. device driver uses on-chip MCU timer. Initializes GPT and performs timer count.
WDG Driver: WDG (Watchdog) Driver, The primary purpose of a watchdog timer is to detect and recover from software or system failures, such as code execution errors, infinite loops, or other unexpected behavior.it is a hardware peripheral that is used to prevent software errors from causing the system to become unresponsive. This on-chip device driver Initializes and performs WDG mode settings.

Memory Driver

Memory Drivers provides a standardized interface for retrieve the memory of the ECU, which includes RAM, ROM, and flash memory.
The memory driver typically provides the following services:

Initialization of the memory devices
Reading and writing to memory
Erasing memory
Managing memory protection
Testing the memory devices

Flash driver: Flash drivers are an essential part of any system that uses flash memory. This will help to ensure that our software is portable, reliable, and efficient. Its initialize Flash and reads/writes to Flash memory.

Communication Drivers

This module Provides a standardized interface for retrieve the communication interfaces used in the ECU, such as CAN, LIN, and FlexRay.

FlexRay: A high-speed communication protocol used in advanced driver assistance systems (ADAS) and other safety-critical applications. Its initializes FlexRay and performs FlexRay input/output.
CAN (Controller Area Network): A widely used communication protocol in automotive applications for inter-ECU communication. It allows multiple ECUs to communicate with each other over a shared bus. Driver that initializes and performs CAN input/output.

I/O Driver

An I/O driver in MCAL is a software module that provides access to the microcontroller's (MCU) I/O ports. It abstracts the physical layer of I/O port, making it easier for the upper software layer to interact with them.

Conclusion
The MCAL layer play a vital role in AUTOSAR software architecture, its allows easy development for automotive Software. making it easy to integrate different software components.

I have written some of the basics of AUTOSAR MCAL and I will continue this topic in my upcoming Articles Thank you..

Design Seats Comfort System using Renesas Controller

Sanakousar — Wed, 22 Nov 2023 05:46:07 +0000

Hello Readers,
I'm Sana, and I'm a Junior Software Developer with Luxoft India. I'm happy to share this post, in which I relate my previous experience with Design Seats Comfort system using Renesas Controller.

Introduction
Here in this Article, we have designed the Seats comfort system in which seat comfort systems can adjust to the driver and passengers individual preferences. They can also adapt to different seasons.
Seats Comfort System heating and cooling solution is a complete system that provides a comfortable and personalized driving experience. This specification covers the functional requirements for the HR/PU single seat heater/ventilation ECU. Additionally, it will capture all the assumptions that are made to allow the project to proceed in a timely manner.

Project Hardware Setup and Overview

Micro Controller :
Renesas MCU : RL78 / F12 series - R5F109GCC
Equipment Being Used in Project:

The ECU will be connected to the following:

1 - Power Supply 
2 - Harness
3 - Heater Mat PADs (Cush and Back)
4 - Blower
5 - Switch assemblies with led indicator
6 - CRO

Hardware Details

Functional Block Diagram

Device Driver(DD) Modules being used in this Project:

Scheduler: In this project, we have designed the scheduler to run at 10ms rate based on project requirement. Which allow the application to be process the data at each 10ms rate and provide designed output. In order to achieve this goal, we have used Timer Channel-3 & Interrupt Channel-3 for design the scheduler.
Timer: In this project, We have used Total 8 channel, 16bits Timer to achieve different different functionality as below :

Ch0 - Master of Heater @5Hz
Ch1- Heater Back - Slave
Ch2 - Heater Cushion - Slave
Ch3 - Scheduler
Ch4 - Master of Blower @20Khz
Ch5 - Blower Cushion - Slave
Ch6 - blower back - Slave
Ch7 - LIN

Interrupts : Each Timers (T0 to T7) are generating interrupt (ISR0 to ISR7) respectively and used as per point no.3
PWM : In this Project, We have designed PWM with Multi PWM (Pulse Width Modulation) Functionality to achieve Heater and Blower (Ventilation) Functionality per point no.3
Watchdog : We have designed watchdog functionality to be serve at 3V per project requirement.
ADC : In this Project, We have used 8 ADC Channel as below :

ANI7 NTC_CUSH_A2D NTC_Cush_A2D
ANI6 uIGN1 IGN1 feedback
ANI5 uHEAT_LS_FB Heat mode Low side current feedback
ANI4 VSP_BACK_A2D Back Fan Speed Voltage Monitor
ANI3 VM_CURRENT_A2D VM Current Monitor
ANI2 uIGN2 IGN2 feedback
ANI1 VSP_CUSH_A2D Cushion Fan Speed Voltage Monitor
ANI0 uHEAT_CURRENT_A2D Cush/Back Heat Mode Current Monitor

LIN : LIN is nothing but Local Interconnect Network used for Communication between Master and Slave. We have designed very basic functionality of communication between Master and Slave.

Operational Modes :

OFF Mode:
In OFF State the ECU will transition from the ON Mode to the OFF Mode
when IGN_VOLTAGE < 5-VDC
ON Mode:
In ON State the ECU from the OFF Mode to the ON Mode
when IGN_VOLTAGE > 5-VDC
Normal Operation Mode :
It transits from IDLE to Normal Mode when 10-VDC IGN_VOLTAGE 15-VDC
Heat Mode:
The ECU will transition from the IDLE Mode to HEAT Mode when Heat Mode Switch is pressed while ECU in Normal Operation Mode.
The ECU will transition from the VENT Mode to HEAT Mode when Heat Mode Switch is pressed while ECU in Normal Operation Mode.
Vent (Blower) Mode:
The ECU will transition from the IDLE Mode to Vent Mode when Vent Mode Switch is pressed while ECU in Normal Operation Mode.
The ECU will transition from the HEAT Mode to VENT Mode when VENT Mode Switch is pressed while ECU in Normal Operation Mode.
Degraded Mode :
It transits from NORMAL HEAT or VENT Mode state to the DEGRADED HEAT state when IGN_VOLTAGE < 8.5-VDC.
It transits from the NORMAL HEAT or VENT Mode state to the DEGRADED HEAT state when IGN_VOLTAGE > 16.5-VDC.
Fault State:
The ECU shall disable HEATER or BLOWER Functionality within 10-msec transitioning to the FAULT state from Normal operation mode.
The ECU shall set HEAT_IND or VENT_IND to INACTIVE within 16-sec of transitioning to the FAULT state.

- CS+ IDE Setup

CS + IDE : First Impression of CS + IDE - Its all about HOW CS+ IDE look like

Clock setting : Select the High-Speed Main Mode - 2.7 (V) < VDC < 5.5 (V) Volts, Threshold Voltage to 0.2 VDD and Set High-Speed Oscillator Clock to 32 MHz based on Project requirement.

Note:
Selection of High-Speed Main Mode Voltage and High-Speed Oscillator Clock setting depend on ECU Specification and watchdog requirement.
For more information, please read Renesas controller datasheet.

Select Internal Low Speed Oscillator Clock to 15Khz and CPU and Peripheral Clock to 32Mhz on based on Project requirement.

Device setting should be done as mentioned below:

Note:
Selection of Link option and Device Setting depend on project requirement.
For more information, please read Renesas controller datasheet.

On chip debug mode should be enabled as below:

Selection of debugger depend on which debugger you have connected with Hardware. i.e. : E1 debugger , E2 or E2 Lite debugger

Reset resource should be enabled:

Note:
Selection of Reset resource depend on project requirement. (i.e., software reset , hard Reset, watchdog reset), We have enabled in this project as we are using watchdog.
For more information, please read Renesas controller datasheet

Voltage needs to be set to 5 Volts to enable the flashing through debugger

Selection of Debugger Tool: Option to select debugger connected with Hardware

Selection of .abs File for Debugging : For Renesas Controller, .abs file is debugger file to do debugging with existing code / build. Engineer used this file to keep the breakpoint and evaluate the result in watch window.

Selection of .hex file for debugger : For Renesas Controller, .hex file is executable file for Testing Purpose. Engineer used this file for Testing

Create Project:
Once you open the CS+ IDE, You can see first impression of IDE as below, later select Project option and Create New Project

Conclusion
The Design Seats Comfort System using Renesas Controller project was a successful endeavor that resulted in a high-performance, cost-effective, and reliable seating system for automotive applications. The project team successfully integrated enabling advanced features such as personalized comfort settings, climate control, and massage functions. The system was designed to meet the stringent requirements of the automotive industry, including durability, safety, and electromagnetic compatibility (EMC).

Derive PWM using Timer/ Interrupts

Sanakousar — Fri, 17 Nov 2023 10:41:49 +0000

Hello Readers,
I'm Sana, and I'm a Junior Software Developer with Luxoft India. I'm happy to share this post, in which I relate my previous experience with Derive the PWM using timer/interrupt.

Introduction
PWM stands for Pulse Width Modulation. It's a technique that controls analog devices with a digital output.
PWM is used to generate analog signals from digital devices like microcontrollers. The signal produced is a train of square wave pulses. The wave is either high or low at any given time
The objective of deriving PWM (Pulse Width Modulation) using timers and interrupts is to achieve precise control of the output pulse width and frequency. PWM is a commonly used technique in embedded systems and electronic devices to control the speed of motors, brightness of LEDs, Heating and cooling control, and various other applications where precise control of the output signal is required.

Hardware and Software setup

Micro Controller:
Renesas MCU : RL78 / F12 series - R5F109GC- 48PINS
Equipment being used:

Renesas E2 Lite Debugger
CRO
Power Supply
USB Cable
CRO Probes

Hardware Details

Operational Modes:

OFF Mode:
In OFF State the ECU will transition from the ON Mode to the OFF Mode
when IGN_VOLTAGE < 5-VDC
ON Mode:
In ON State the ECU will transition from the OFF Mode to the ON Mode
when IGN_VOLTAGE > 5-VDC.
IDLE Mode:
When Ignition Voltage is 5-VDC > IGN_VOLTAGE < 10-VDC and user is not switching (not pressing any switch) Heater or Ventilation mode can be consider as IDLE Mode.
It will default to the IDLE sub- mode when in the OPERATIONAL Mode.
In Idle Mode, ECU is in RUN condition , However all the outputs are disable.
Normal Operation Mode :
It transits from IDLE Mode to Normal Mode when 10-VDC > IGN_VOLTAGE < 15-VDC
Heat Mode:
The ECU will transition from the IDLE Mode to HEAT Mode when Heat Mode Switch is pressed while ECU in Normal Operation Mode.
The ECU will transition from the VENT Mode to HEAT Mode when Heat Mode Switch is pressed while ECU in Normal Operation Mode.
Vent (Blower) Mode:
The ECU will transition from the IDLE Mode to Vent Mode when Vent Mode Switch is pressed while ECU in Normal Operation Mode.
The ECU will transition from the HEAT Mode to VENT Mode when VENT Mode Switch is pressed while ECU in Normal Operation Mode
Degraded Mode :
It transits from NORMAL HEAT or VENT Mode state to the DEGRADED HEAT state when IGN_VOLTAGE < 8.5-VDC.
It transits from the NORMAL HEAT or VENT Mode state to the DEGRADED HEAT state when IGN_VOLTAGE > 16.5-VDC.

Fault State:
When user disconnect the Seat Cushion HMAT / Seat Back HMAT or BLOWER, then within 10-msec of Normal operation mode will transitioning to the FAULT state.
The ECU shall disable HEATER or BLOWER Functionality within 10-msec transitioning to the FAULT state from Normal operation mode.
The ECU shall set HEAT_IND or VENT_IND to INACTIVE within 16-sec of transitioning to the FAULT state.
Fault Protection:
The ECU shall be capable of operating after a fault is removed without incurring any physical damage or functional degradation.

I/O Port configuration:
The I/O Port Configuration is essential for establishing proper communication, facilitating PWM generation, interfacing with peripherals, and ensuring system compatibility in the project. It allows for precise control and validation of signals, enabling successful implementation of PWM using timers and interrupts.
In our Project as per the requirement we made I/o Configuration for all the Ports, based on the input received from the in the form of excel(I/O pin mapping).

Timer Configuration
Timer configuration is essential for precise timing, PWM generation, support for multiple channels, interrupt generation, efficient resource utilization, dynamic adjustments, compatibility with hardware, and system optimization. It enables the project to achieve accurate and controlled PWM signals, enhancing the functionality and performance of the overall system.
In our project we considered Renesas RL78 Microcontroller, which consists of eight 16 bit-timer, Considered channel 0 to channel7.

I/O Port Validation

Validated the I/O Port using LED, by considering Port (P73) as output.
While we RUN the software, LED will be ready to glow.

PWM Validation

PWM Implementation on Renesas Controller:

Used Timer channels from channel0 to channel7

Channel Usage

0 -- Master of Ch1

1 -- Slave of Ch1 (generates output TO01)

2 -- Slave of Ch2 (generates output TO02)

3 -- Interval timer Ch3

4 -- _ Master of Ch2 _

5 -- Slave of Ch5 (generates output TO05)

6 -- Slave of Ch6 (generates output TO06)

7 -- Interval timer Ch7embed

PWM Feasibility on Evaluation Board:
Renesas evaluation boards have built-in hardware support for PWM generation.
The evaluation board usually includes timer modules, such as the TAU (Timer Array Unit), that can be utilized for generating PWM signals.

PWM Validation:

TimerChannel1 as Slave and P16 as output, Pin in target board: channel1(CN1) 16pin, with duty cycle 50%

Conclusion
Pulse-width modulation (PWM) is a powerful technique for controlling the power delivered to a load. By varying the duty cycle of a PWM signal, the average power delivered to the load can be controlled. This technique is widely used in a variety of applications, including motor control, LED lighting, and power supplies. Renesas microcontrollers (MCUs) offer a variety of hardware and software features that can be used to generate PWM signals. The Timer/Interrupt units (TIUs) on Renesas MCUs are particularly well-suited for PWM generation, as they offer a high degree of flexibility and control.

Design the Scheduler using Timer Array Unit and Interrupt

Sanakousar — Wed, 15 Nov 2023 10:02:26 +0000

Hello Readers,
I'm Sana, and I'm a Junior Software Engineer with Luxoft India. I'm happy to share this post, in which I relate my previous experience with Design the scheduler using timer array unit and interrupt.

Introduction
Here in this Article, we have designed the scheduler to run at a 5ms, 10ms, 100ms rate based on project requirements. Which is provide sync and process the data application and MCAL to provide designed output.
Scheduler use to do scheduling the tasks. Here we are using Non Pre-emptive O.S means task execute based on FIFO (First In First Out), so which task is queue it will start and complete it job later next time will execute.
It is responsible for ensuring that all tasks are executed in a timely manner. If the scheduler is not implemented correctly, it can lead to system instability or even failure. CPU Scheduling is a process that allows one process to use the CPU while another process is delayed due to unavailability of any resources such as I/O etc, thus making full use of the CPU. The purpose of CPU Scheduling is to make the system more efficient, faster, and fairer. The scheduler will always choose the task with the highest priority that is ready to run.

Hardware and Software setup

Micro Controller :
Renesas MCU : RL78 / F12 series - R5F109GC- 48PINS
Equipment being used:
1. Renesas Evolution Board
2. E2 Lite Debugger
3. Cable
4. CRO

Operational Modes:

OFF Mode:
In OFF State the ECU will transition from the ON Mode to the OFF Mode
when IGN_VOLTAGE < 5-VDC
ON Mode:
In ON State the ECU will transition from the OFF Mode to the ON Mode
when IGN_VOLTAGE > 5-VDC.
IDLE Mode:
When Ignition Voltage is 5-VDC > IGN_VOLTAGE < 10-VDC and user is not switching (not pressing any switch) Heater or Ventilation mode can be consider as IDLE Mode.
It will default to the IDLE sub- mode when in the OPERATIONAL Mode.
In Idle Mode, ECU is in RUN condition , However all the outputs are disable.
Normal Operation Mode :
It transits from IDLE Mode to Normal Mode when 10-VDC > IGN_VOLTAGE < 15-VDC
Heat Mode:
The ECU will transition from the IDLE Mode to HEAT Mode when Heat Mode Switch is pressed while ECU in Normal Operation Mode.
The ECU will transition from the VENT Mode to HEAT Mode when Heat Mode Switch is pressed while ECU in Normal Operation Mode.
Vent (Blower) Mode:
The ECU will transition from the IDLE Mode to Vent Mode when Vent Mode Switch is pressed while ECU in Normal Operation Mode.
The ECU will transition from the HEAT Mode to VENT Mode when VENT Mode Switch is pressed while ECU in Normal Operation Mode
Degraded Mode :
It transits from NORMAL HEAT or VENT Mode state to the DEGRADED HEAT state when IGN_VOLTAGE < 8.5-VDC.
It transits from the NORMAL HEAT or VENT Mode state to the DEGRADED HEAT state when IGN_VOLTAGE > 16.5-VDC.

Fault State:
When user disconnect the Seat Cushion HMAT / Seat Back HMAT or BLOWER, then within 10-msec of Normal operation mode will transitioning to the FAULT state.
The ECU shall disable HEATER or BLOWER Functionality within 10-msec transitioning to the FAULT state from Normal operation mode.
The ECU shall set HEAT_IND or VENT_IND to INACTIVE within 16-sec of transitioning to the FAULT state.
Fault Protection:
The ECU shall be capable of operating after a fault is removed without incurring any physical damage or functional degradation.

I/O Port configuration

In this project we are using RL78/F12 microcontrollers are provided with digital I/O ports, which enable variety of control operations. These ports have several alternate functions
I/O port configuration is the process of setting up the I/O ports on a microcontroller to control external devices. This can be done in software.
In our Project as per the requirement we made I/O Configuration for all the Ports, based on the input received from the customer in the form of excel(I/O Mapping)

Timer configuration
In this project, We have used Total 8 channel, 16bits Timer to achieve different functionality such as schedulers.
Timers are a common peripheral in microcontrollers. They can be used for a variety of purposes, such as generating interrupts, controlling peripherals, and implementing timekeeping.
Renesas controllers, timers are configured using a set of registers. These registers control the timer's mode, period, and compare value.

Interrupt Configuration
Interrupt configuration is essential for the Renesas scheduler. The scheduler is responsible for managing the execution of tasks in a multi-tasking system.
When an interrupt occurs, the scheduler will automatically call the registered interrupt handler. The interrupt handler can then perform any necessary processing and then return control to the scheduler.

Validation of Scheduler
In this picture we can see if we Apply the break point to each ISR. If the breakpoint is hit, it will stop the program execution and allow to step through the code in the ISR.

Conclusion
This essay has presented a design for a scheduler using the timers array unit and interrupts at rate 5ms, 10ms, 100ms in Renesas control. The design has been validated using both the CS+ IDE and CRO, demonstrating its correctness and reliability. The scheduler offers several potential benefits, such as improved performance and reliability. Future work could focus on developing a more general-purpose scheduler that can be used on a wider range of Renesas microcontrollers.