DEV Community: A Serputov

AWS Simple Email Service + Serverless Vercel + Node.js Deploy&Receive Emails For Free

A Serputov — Sun, 12 Jun 2022 18:27:33 +0000

This is a quick guide: On How To Deploy(Create) Node.js Server With AWS SES on Vercel(Heroku, Netlify, e.t.c)

Our Code will Send A Confirmation Email On Form Submission.

Create A Server

const express = require("express");
const path = require("path");
const bodyParser = require("body-parser");
const app = express();
const port = process.env.PORT || 8080;

app.get("/home", function (req, res) {
  res.sendFile(path.join(__dirname, "/index.html"));
});

app.listen(port);

console.log("Server started at http://localhost:" + port);

We don't need Post Routes anymore.

HTML>

<!DOCTYPE html>
<html lang="en">
<head>
</head>
<body>
<div>Works!</div>
</body>
</html>

Setup AWS Simple Email Notification Service. https://us-east-1.console.aws.amazon.com/ses/home?region=us-east-1#/homepage

You will need to confirm your email.

Done.

In HTML we need to add <form action="/api/hello" method="POST" style=" padding: 1%;margin-left:25%;width: 50%;">

/api/hello is the endpoint for Serverless in Vercel.

Create Your Logic Inside hello.js file in api folder.

var aws = require("aws-sdk");

export default function hello(req, res) {
  const formData = req.body;
  console.log(req.body.name);

  aws.config.update({
    credentials: {
      accessKeyId: process.env.AWS_ACCESS_KEY_ID_MYAPP,
      secretAccessKey: process.env.AWS_SECRET_ACCESS_KEY_MYAPP,
    },
    region: process.env.AWS_REGION_MYAPP,
  });

  // AWS.config.update({region: });

  var params = {
    Destination: {
      /* required */
      CcAddresses: [
        "ser****@gmail.com",
        /* more items */
      ],
      ToAddresses: [
        "serp****@gmail.com",
        "additionalemail@gmail.com",
        /* more items */
      ],
    },
    Message: {
      /* required */
      Body: {
        /* required */
        Text: {
          Charset: "UTF-8",
          Data: `${JSON.stringify(formData)}`,
        },
      },
      Subject: {
        Charset: "UTF-8",
        Data: "Test email",
      },
    },
    Source: "serp****@gmail.com" /* required */,
    ReplyToAddresses: [
      "serpu****@gmail.com",
      /* more items */
    ],
  };

  // Create the promise and SES service object
  var sendPromise = new aws.SES({ apiVersion: "2010-12-01" })
    .sendEmail(params)
    .promise();

  // Handle promise's fulfilled/rejected states
  sendPromise
    .then(function (data) {
      console.log(data.MessageId);
      res.status(200).send(`Hello Thank you!!`);
    })
    .catch(function (err) {
      console.error(err, err.stack);
    });
  //   res.redirect("/home");
  //
}

Don't FORGET to add env variables inside your Vercel Website.

Conclusion

Thanks For Reading.

Links

🖇 Follow me on GitHub

🖇 Follow me on Twitter

_p.s This post was made out of my curiosity.

Auto-Commiter. Controls your commits and GitHub.

A Serputov — Sat, 23 Apr 2022 15:03:45 +0000

Auto-committer.

https://github.com/aserputov/auto

This is simple, but I think exciting project idea to make auto commits into your GitHub.

How does it work?

Small story.

I use git a lot, it helps me manage projects, and I know that making small but meaningful commits is essential to you in future or for your team members.

But, it's tough to do that every small block of code changes.

There are many things you can do with Git and even more with API.

I decided to create something that would commit for me.

My problems:

How to commit only the correct code that can be built.

We need to check the code before committing.

Can we add a feature to check if we already have a repo there we want to commit, or should we create a new repo with the same name as a folder?

Yes, we can, but there will be problems with it because Github Api asks for a token to authenticate.

Currently, I'm working with Node.js and kind of made a prototype. npm commit

I will add more in progress.

Conclusion

⚠️ Computer Architecture Blog Post: Link

Links

🖇 Follow me on GitHub

🖇 Follow me on Twitter

_p.s This post was made for Telescope.

Memory Systems

A Serputov — Fri, 22 Apr 2022 21:10:04 +0000

Memory Systems.

After searching online about hot field - memory systems, I found this great paper.

The memory system is the storage of information (data) in a computer system. The processor (also called the central processing unit, or CPU) accesses (reads or loads) data from the memory system, performs computations on them, and stores (writes) them back to memory. The memory system is a collection of storage locations. Each storage location, or memory word, has a numerical address. A collection of storage locations from an address space. Figure 1 shows the essentials of how a processor is connected to a memory system via address, data, and control lines.

This is work in progress.

Resources:

https://www.studytonight.com/computer-architecture/memory-organization

https://citeseerx.ist.psu.edu/viewdoc/download?doi=10.1.1.103.9197&rep=rep1&type=pdf

Conclusion

It was a Great project to work on and a great course to learn about different ways to optimize code.

Thank you, professor and readers!

⚠️ Computer Architecture Blog Post: Link

Links

🖇 Follow me on GitHub

🖇 Follow me on Twitter

_p.s This post was made for Telescope.

SPO 600 project part 3 - Analysis

A Serputov — Fri, 22 Apr 2022 05:10:36 +0000

Introduction

This is the final part of our project to implement SVE2 instructions into an open-source project. Thank you for reading.

If you didn't yet read the second, please see this link.

Also, you can see the link to the repo here.

https://github.com/aserputov/std-simd

Pull Request: https://github.com/VcDevel/std-simd/pull/35

For this project, I did two different ways to work with SVE2.

Autovectorization
Intrinsics

Also, I have two different types of machines that help me test the library.

We can't apply our instructions to all the files, but at least I tried something.

We don't have hardware for ARM9 yet, so we won't see many differences.

Added different variables to the project for SVE2.

Update: after receiving feedback on project part 2.

My initial idea was to work with autovectorization.

As I see now there is no way to add autovectorization to my header library.

That's why in the second part of my project, I decided to use intrinsics with SVE2.

You can track my progress here:
https://github.com/VcDevel/std-simd/pull/35

But now more on what was my idea with intrinsics:(Of course I found that it was super hard to do and I still in progress, but I think I did a small progress)

First step in my analysis: https://developer.arm.com/documentation/100748/0616/SVE-Coding-Considerations-with-Arm-Compiler/Using-SVE-and-SVE2-intrinsics-directly-in-your-C-code

Intrinsics are C or C++ pseudo-function calls that the compiler replaces with the appropriate SIMD instructions. These intrinsics let you use the data types and operations available in the SIMD implementation, while allowing the compiler to handle instruction scheduling and register allocation.

My code steps:

Header file inclusion

#ifdef __ARM_FEATURE_SVE
#include <arm_sve.h>
#endif /* __ARM_FEATURE_SVE */ 

// All functions and types that are defined in the header file have the prefix sv, to reduce the chance of collisions with other extensions.

In my code it's on line 51 https://github.com/VcDevel/std-simd/blob/5a1ef0e3c5ccc36fbc4af8fb1ad8c89e6e6d0dd4/experimental/bits/simd.h#L51

SVE vector types.
arm_sve.h defines the following C types to represent values in SVE vector registers. Each type describes the type of the elements within the vector:

I updated a few variables types for now with Sve2 types.
I'm still in progress, because it seems work is too big.
(Note: I would like to mention that I created constexpr for Sve2 to maybe future logic in std-simd library. I thought and still think it will help not a lot but at some points for SVE2.)

!Docs
Common situations where SVE types might be used include:

As the type of an object with automatic storage duration.
As a function parameter or return type.
As the type in a (type) {value} compound literal.
As the target of a pointer or reference type.
As a template type argument.

The
SVE2 intrinsics

!Docs reference
To enable only the base SVE2 instructions, use the +sve2 option with the armclang -march or -mcpu options. To enable additional optional SVE2 instructions, use the following armclang options:

+sve2-aes to enable scalable vector forms of AESD, AESE, AESIMC, AESMC, PMULLB, and PMULLT instructions.
+sve2-bitperm to enable the BDEP, BEXT, and BGRP instructions.
+sve2-sha3 to enable scalable vector forms of the RAX1 instruction.
+sve2-sm4 to enable scalable vector forms of SM4E and SM4EKEY instructions.
You can use one or more of these options. Each option also implies +sve2. For example, +sve2-aes+sve2-bitperm+sve2-sha3+sve2-sm4 enables all base and optional instructions. For clarity, you can include +sve2 if necessary.

I got some kind of the point on how to the intrinsics, but I'm still looking there I can add them in this header library:
Ex.(I use)

void daxpy_1_1(int64_t n, double da, double *dx, double *dy)
{
    for (int64_t i = 0; i < n; ++i) {
        dy[i] = dx[i] * da + dy[i];
    }
}

void daxpy_1_1(int64_t n, double da, double *dx, double *dy)
{
    int64_t i = 0;
    svbool_t pg = svwhilelt_b64(i, n);                                       // [1]
    do {
        svfloat64_t dx_vec = svld1(pg, &dx[i]);                     // [2]
        svfloat64_t dy_vec = svld1(pg, &dy[i]);                     // [2]
        svst1(pg, &dy[i], svmla_x(pg, dy_vec, dx_vec, da));         // [3]
        i += svcntd();                                              // [4]
        pg = svwhilelt_b64(i, n);                                   // [1]
    }
    while (svptest_any(svptrue_b64(), pg));                                   // [5]
}

https://developer.arm.com/documentation/100987/0000/
I will progress with this work and update post.

Also, because I didn't show auto-vectorization on practice in std-simd library and not actually build it, I decided to show that I have knowledges on how it works, and used one extra library, to apply them():

My choice fall on this project:
https://github.com/cisco/openh264

It was easy to build and test on different machines, because except Israel and Portugal servers I also had my own arm64 and x86 local machines.

Here : make OS=ios ARCH=**ARCH**

!DOCS

Valid values for **ARCH** are the normal iOS architecture names such as armv7, armv7s, arm64, and i386 and x86_64 for the simulator. Another settable iOS specific parameter is SDK_MIN, specifying the minimum deployment target for the built library. For other details on building using make on the command line, see 'For All Platforms' below.

After with find command we found this executable files:


-rw-r--r--   1 anatoliyserputov  staff   443656 libcommon.a
-rw-r--r--   1 anatoliyserputov  staff     8160 libconsole_common.a
-rw-r--r--   1 anatoliyserputov  staff  1604152 libdecoder.a
-rw-r--r--   1 anatoliyserputov  staff  2019888 libencoder.a
-rw-r--r--   1 anatoliyserputov  staff  4444584 libopenh264.a
-rw-r--r--   1 anatoliyserputov  staff   377176 libprocessing.a

Also, I built it using make ARCH=arm64

And, on Israel

Now, it's time to test.

testbin/CmdLineExample.sh

https://github.com/cisco/openh264

Now, we only need to run it with qemu-aarch64

Conclusion

It was a Great project to work on and a great course to learn about different ways to optimize code.

Thank you, professor and readers!

⚠️ Computer Architecture Blog Post: Link

Links

🖇 Follow me on GitHub

🖇 Follow me on Twitter

_p.s This post was made for SPO600 class.

Telescope final release 3.0

A Serputov — Tue, 19 Apr 2022 20:11:40 +0000

Release 3.0

We will push our final release in a few days, and I would like to talk about it.

First of all, it was a great semester, and I worked with many different technologies included in Telescope architecture.

Meeting and being Sheriff was my most loved part because it helped me improve my skills.

Currently, I have one issue left regarding Nginx. I hope to finish by the end of the semester.

I hope that we will successfully launch our 3.0 release and slowly move to the following heights.

Lastly, Thank you to every team member and professor I worked with on OSD and Telescope.

Conclusion

⚠️ Computer Architecture Blog Post: Link

Links

🖇 Follow me on GitHub

🖇 Follow me on Twitter

_p.s This post was made for Telescope.

SPO600 project part 2

A Serputov — Wed, 13 Apr 2022 20:45:27 +0000

For those who don't remember, I'm currently working on a project to implement SVE2 instructions into an open-source project.

In the last part, I was looking for an excellent candidate to which we could add SVE2 instruction.

This part will look into the open-source directory and see how we can implement scalable vector extensions.

First of all, I previously decided to work with the VC library on our project.https://github.com/VcDevel/Vc

After searching around, I found that this repository has a better project than SSE and Neon.

STD-SIMD is almost the same project I was working on but a bit more advanced: https://github.com/VcDevel/std-simd.

Here, you can see my progress: with the maintainer team and the progress I'm making:

Issue-1:https://github.com/VcDevel/Vc/issues/320

Issue-2:https://github.com/VcDevel/std-simd/issues/34

Pull-Request: https://github.com/VcDevel/std-simd/pull/35

I started by cloning the repo and searching through the code:

Are there SIMD instructions? Yes.

Is there SVE? No.

But there is SSE. Yes.

There is also AVX.

Also, let's check for architecture.
X86. Yes.

ARM/ARM64. No

After I checked all the files, I decided to start implementing the code:
There were no .s .S files which made it a bit scary, but I have a plan.
It will be some If&def that will switch between existing x86 functions to arm/arm64. I'm going to try to implement SVE2 with arm/64.

What options do I have:

auto-vectorization
intrinsics
inline-assembly

Let's see what we can do:

For auto-vectorization, it's needed to change the build instructions, but it won't be specific and as our professor said C compiler can't always know what to do.
Intrinsics and Inline-assembly are complicated to include because it's not only a build instruction but a change in a source code. As I looked a bit through the code, it has intrinsic inside it, defined as macros.

Also, I found our If statement for different instructions:

simd.c 
#if _GLIBCXX_SIMD_X86INTRIN
#include "bits/simd_x86.h"
#elif _GLIBCXX_SIMD_HAVE_NEON
#include "bits/simd_neon.h"
#elif __ALTIVEC__
#include "bits/simd_ppc.h"
#endif
#include "bits/simd_math.h"

I've decided to start with auto-vectorization and work a bit with arm/arm64 inline assembly or intrinsics if I have time.

I want to note that we won't have a chance to see an increase in time because we don't have the hardware yet, but lets at least prepare our code and build it successfully.

I just read through the library instructions for auto-vectorization and tried to build on different machines, simply adding the flags to my build.

gcc -O3 -march=armv8-a+sve2 ... // 03 flag to enable auto-vectorization

gcc -O2 -march=armv8-a+sve2 -ftree-vectorize ... // or -ftre...

I have an arm64 and x86 local computer, so I checked on both machines, and everything was built. But as mentioned above, we can't see the difference because of hardware, but at least we know it will work in the future new architecture.

In addition to this, I decided to dive deeper into the code and maybe at least try adding intrinsics for sve2.

Here, you can see all the progress. I have already changed a few files. Include header:

#include <arm_sve.h>

And wrote an ifdef statement to switch between different architecture and instructions.

I will progress on this more until part three and after, so maybe the maintainer could accept my changes into their code.

Pull-Request: https://github.com/VcDevel/std-simd/pull/35

Conclusion

References:

https://developer.arm.com/documentation/100987/0000/

https://developer.arm.com/architectures/instruction-sets/intrinsics/#f:@navigationhierarchiessimdisa=[sve2]

⚠️ Pull-Request: https://github.com/VcDevel/std-simd/pull/35

Links

🖇 Follow me on GitHub

🖇 Follow me on Twitter

_p.s This post was made for my Software Portability and Optimization class. project part2

How React-Native Cross-Platform Works?

A Serputov — Tue, 29 Mar 2022 04:09:37 +0000

React-Native. https://github.com/facebook/react-native

This Blog Post started as a curiosity on how cross-platforming features work in React Native, but while researching, I discovered that this blog post should be a work in progress about something more.

About https://webkit.org WebKit engine.
About hidden JavaScriptCore framework. https://www.cyberark.com/resources/threat-research-blog/the-mysterious-realm-of-javascriptcore
https://github.com/WebKit/webkit/tree/main/Source/JavaScriptCore
About Why every browser switching to Blink could be bad news for the web https://medium.com/@stouff.nicolas/why-every-browser-switching-to-blink-could-be-bad-news-for-the-web-aea773059e84
About Gecko.https://developer.mozilla.org/en-US/docs/Glossary/Gecko
About Chrominum&V8&Blink. https://www.chromium.org/chromium-projects/
https://v8.dev
How I decided to switch for only Chrominium based architecture browsers.
I will call this blog post a work in progress.
There are a lot of things to research.
If you're curious how cross-platform systems work, across Linux,osx, windows, ios, android or different processors, leave a comment or ideas. Thanks.
p.s I knew JavaScript was weird, but why so why sooooo odd.

https://www.cyberark.com/wp-content/uploads/2021/03/Figure1.png

Conclusion

TL;DR

⚠️ Next Blog Post.

Links

🖇 Follow me on GitHub

🖇 Follow me on Twitter

_p.s This post was made out of my curiosity

Telescope. 3.0-alpha

A Serputov — Tue, 29 Mar 2022 02:23:01 +0000

We successfully landed the 2.9 release, and now we focus on the alpha-3.0 release. I am glad to share that our small team fixed all the bugs for Eslint and created additional enhancements for eslint inside our monorepo tools.

For this week, I will focus on the Docker file best practices issue to finish my part in the web repo.

It's almost the end of the school year, and we are all focused on peacefully landing our Telescope 3.0 release.

Conclusion

⚠️ Computer Architecture Blog Post: Link

Links

🖇 Follow me on GitHub

🖇 Follow me on Twitter

_p.s This post was made for Telescope.

SVE2. ARM9.

A Serputov — Thu, 24 Mar 2022 02:10:59 +0000

Explore the New Armv9 Decade.

The most significant new feature with new Armv9 compatible CPUs that will be directly observable to developers and users is the baselining of SVE2 as a successor to NEON.

The Armv9 Scalable Vector Extensions version 2 (SVE2) provides variable-width SIMD credentials for AArch64 systems.

In its first implementation, Scalable Vector Extensions, or SVE, was announced back in 2016 and implemented for the first time in Fujitsu's A64FX CPU cores, now powering the world's #1 supercomputer Fukagu in Japan. The problem with SVE was that this first iteration of the new variable vector length SIMD instruction set was somewhat limited in scope and aimed more at HPC workloads, missing many of the more versatile instructions covered by NEON.

SVE2 was announced in April 2019 and looked to solve this issue by complementing the new scalable SIMD instruction set with the needed instructions to serve more varied DSP-like workloads that currently use NEON.

The benefit of SVE and SVE2 beyond the addition of various modern SIMD capabilities is their variable vector size, ranging from 128b to 2048b, allowing variable 128b granularity of vectors, irrespective of the actual actuality hardware is running on. Purely from a view of vector processing and programming, a software developer would only ever have to compile his code once. If in the future a CPU would come out with, say, native 512b SIMD execution pipelines, the code would be able already to take advantage of the entire width of the units. Similarly, the same principle would be able to run on more conservative designs with a lower hardware execution width capability, which is essential to Arm as they design CPUs from IoT to mobile to datacentres. It also does this all while remaining within the 32b encoding space of the Arm architecture. In contrast, alternative implementations such as x86 have to add new extensions and instructions depending on vector size.

Building SVE2 Code

To build code that includes SVE2 instructions, you will need to instruct the compiler or assembler to emit code for an Armv8a processor that also understands the SVE2 instructions; this is performed using the -march= option (which is read as "machine architecture"). The architecture specification for this target is currently "armv8-a+sve2":

gcc -march=armv8-a+sve2 ...

Remember that to invoke the auto vectorizer in GCC version 11. It would help if you used -O3:

gcc -O3 -march=armv8-a+sve2 ...

Using SVE2 Intrinsics Header Files

To use SVE2 intrinsics in a C program, include the header file arm_sve.h:

#include <arm_sve2.h>

Running SVE2 Code

To run SVE2 code on an Armv8 system, you can use the QEMU user-mode system. This will trap SVE2 instructions and emulate them in software while executing Armv8a instructions directly on the hardware:

qemu-aarch64 ./binary

This blog post is work in progress;

Resources

https://www.arm.com/campaigns/arm-vision

https://www.anandtech.com/show/16584/arm-announces-armv9-architecture
https://developer.arm.com/documentation/ddi0602/2021-12/

Conclusion

⚠️ Computer Architecture Blog Post: Link

Links

🖇 Follow me on GitHub

🖇 Follow me on Twitter

_p.s This post was made for my Software Portability and Optimization class.

Inline Assembly Language. What is that?

A Serputov — Wed, 23 Mar 2022 18:29:42 +0000

An inline assembler is a part of some compilers that permits low-level code written in assembly language to be embedded within a program, among code that otherwise has compiled from a higher-level language such as C.

The embedding of assembly language code is usually done for one of these reasons:

Optimization.
Pass to processor-specific instructions.
Pass to certain calling conventions not yet supported by the compiler.
System calls and interrupts: High-level languages rarely have a direct facility to make arbitrary system calls, so assembly code is used.
To emit special directives for the linker or assembler, such as changing sectioning, macros, or making symbol aliases.

Examples:

Demonstrates two kinds of inline assembly syntax offered by the GCC compiler. This program will only work correctly on the x86-64 platform under Linux.

#include <stdio.h>

extern int func(void);
// the definition of func is written in assembly language
__asm__(".globl func\n\t"
        ".type func, @function\n\t"
        "func:\n\t"
        ".cfi_startproc\n\t"
        "movl $7, %eax\n\t"
        "ret\n\t"
        ".cfi_endproc");

int main(void)
{
    int n = func();
    // gcc's extended inline assembly
    __asm__ ("leal (%0,%0,4),%0"
           : "=r" (n)
           : "0" (n));
    printf("7*5 = %d\n", n);
    fflush(stdout); // flush is intentional

    // standard inline assembly in C++
    __asm__ ("movq $60, %rax\n\t" // the exit syscall number on Linux
             "movq $2,  %rdi\n\t" // this program returns 2
             "syscall");
}

Output

7*5 = 35

_Inline assembler poses a direct concern for the compiler as it confuses the breakdown of what is done to individually variable, a crucial piece of register allocation. It represents the performance might fall. The inline assembler also complicates future porting and maintenance of a program.

Alternative structures are often provided to simplify the job for both the compiler and the programmer. Most compilers offer intrinsic functions for special instructions, and C-function wrappers for arbitrary system calls are available on every Unix platform._

Usually, "intrinsics" guides to built-in functions -- i.e. most common library functions that the compiler can/will cause inline rather than calling a fundamental function in the library. For instance, a call like memset(array1, 10, 0) could compile for an x86 as something like:

mov ecx, 10
 xor eax, eax
 mov edi, offset FLAT:array1
 rep stosb

Intrinsics like this are purely an optimization. "Needing" intrinsics would most likely be when the compiler helps intrinsics that allow you to develop code that the compiler can't (or usually won't) generate directly. For an obvious example, quite a few compilers for x86 have "MMX Intrinsics" that let you use "functions" that are just direct representations of MMX instructions.

Are there Intrinsics or inline assembly with JavaScript.

Honestly, I searched a lot about this question and found only this information. I will leave this blog post as a work in progress for now. If you have comments, please share them. Thank you, I appreciate any help with this research.

https://github.com/WebAssembly/design/issues/1206
https://webassembly.org
https://stackoverflow.com/questions/12168575/executing-generated-assembler-inline

Resources

https://wiki.cdot.senecacollege.ca/wiki/Inline_Assembly_Language
https://en.cppreference.com/w/c/language/asm
https://en.wikipedia.org/wiki/Inline_assembler
https://stackoverflow.com/questions/2268562/what-are-intrinsics
https://www.codeproject.com/Articles/15971/Using-Inline-Assembly-in-C-C
https://stackoverflow.com/questions/48518225/what-are-intrinsic-types-in-javascript
https://stackoverflow.com/questions/12168575/executing-generated-assembler-inline
https://github.com/v8/v8/blob/master/src/objects/dictionary.h

Conclusion

⚠️ Computer Architecture Blog Post: Link

Links

🖇 Follow me on GitHub

🖇 Follow me on Twitter

_p.s This post was made for my Software Portability and Optimization class.

SPO600 project part 1

A Serputov — Tue, 22 Mar 2022 19:58:16 +0000

First of all, let's talk about the project and what we should do for the first stage.

This semester, the project involves adding SVE2 optimizations to an open-source software package.

For the first part, we will go through these parts:
(I decide not to rewrite the same documentation, you can read more about the rules of each part here.)

Identify some candidate open-source packages for optimization.

Find the SIMD implementations in these packages.

Select the package you want to work with.

Create a strategy for your changes.

Note how the community accepts contributions and engages with the community to discuss your proposed work.

Let's find some open-source candidates:

I'm substantial open-source fun for almost two years now, and out of my curiosity, I decided first to check the libraries and software that I previously wanted to contribute.

The most recent idea was to look through Curl and a few python libraries. Also, I decided to see the javascript web socket library. Still, after reading more tips on the lab, I thought it's much better to look through library-level packages only and better with c/c++ because it's easier to add assembly in one of these ways:

auto-vectorization
inline assembler
intrinsicts.

Examples:
https://github.com/pandas-dev/pandas
https://github.com/booknlp/booknlp/find/main
https://github.com/optuna/optuna

I've decided to switch to something better, and after a few hours of searching, I found this repository:
NSIMD https://github.com/agenium-scale/nsimd
FastDifferentialCoding https://github.com/lemire/FastDifferentialCoding
VS https://github.com/VcDevel/Vc
XSIMD https://github.com/xtensor-stack/xsimd

I was shocked to find this project from google repo:
https://github.com/google/highway and I even wrote an email to the owner repo to see what progress they did and everything about SIMD/SVE instructions inside the repo:

I received a feedback:

but unfortunately while receiving this email, I also saw that they already have SVE2 instructions:

It's great to have some experience and implement the todos, but that's in a different blogPost.

I decided to move on and came across these repositories:
XSIMD https://github.com/xtensor-stack/xsimd
VS https://github.com/VcDevel/Vc
Why?

Is there SIMD implementations in these packages?

Yes, both of these repositories have SIMD instructions, but one of them only has arm instructions.

Select the package you want to work with.

About the package.
Vc is portable, zero-overhead C++ types for explicitly data-parallel programming.

I will work mainly with VC to implement the SVE2 instructions and work with XSIMD.

Create a strategy for your changes.

For now, I have already forked their repo on GitHub and cloned it to my local VSCode. Now I will browse through the code to see what I can update, how their build process works, how the library works overall, and how to implement all the features for SVE2 instructions, like .h(header file) + script for build and so on.

Note how the community accepts contributions and engages with the community to discuss your proposed work.

I will need to write the message on slack or an email to check if I can add SVE2 instructions to their repo. But as it's a GitHub repo, I hope they will check my updates simply with a new Pull Request.

I created an Issue. Let's see how it will go:

https://github.com/VcDevel/Vc/issues/320

Also I will definitely spend time on google/highway. Please wait for my new blog about it as soon as possible.

Conclusion

⚠️ Computer Architecture Blog Post: Link

Links

🖇 Follow me on GitHub

🖇 Follow me on Twitter

_p.s This post was made for my Software Portability and Optimization class. Lab 6.

Algorithm Selection with Inline Assembly(part2)

A Serputov — Mon, 21 Mar 2022 21:28:41 +0000

This is the second part of Algorithm Selection with Inline Assembly. We are going to change our code to use SVE2 instructions.

Quick Note: The Armv9 Scalable Vector Extensions version 2 (SVE2) provide a variable-width SIMD capability for AArch64 systems.

We will work with the AArch64(Israel server) machine for those who don't remember.

The purpose of this lab is to:

Create a new version of the volume scaling code from the Algorithm Selection Lab, which uses SVE2 instructions.
Next, we will prove that the code is using SVE2 instructions by analyzing the disassembly of the relevant portion of the binary.

Let's start:

I started by changing the Makefile to compile our files with different commands to use :

gcc -march=armv8-a+sve2 ...

Remember that in order to invoke the autovectorizer in GCC version 11, you must use -O3:

gcc -O3 -march=armv8-a+sve2 ...

The next step is to add SVE instructions into our C code and check how long it will take to execute with new features.

Here is our current code for Vol4:

#include <stdlib.h>
#include <stdio.h>
#include <stdint.h>
#include "vol.h"
#include <arm_sve.h>

int main() {

#ifndef __aarch64__
    printf("Wrong architecture - written for aarch64 only.\n");
#else


    // these variables will also be accessed by our assembler code
    int16_t*    in_cursor;       // input cursor
    int16_t*    out_cursor;       // output cursor
    int16_t     vol_int;        // volume as int16_t

    int16_t*    limit;         // end of input array

    int       x;           // array interator
    int       ttl=0 ;         // array total

// ---- Create in[] and out[] arrays
    int16_t*    in;
    int16_t*    out;
    in=(int16_t*) calloc(SAMPLES, sizeof(int16_t));
    out=(int16_t*) calloc(SAMPLES, sizeof(int16_t));

// ---- Create dummy samples in in[]
    vol_createsample(in, SAMPLES);

// ---- This is the part we're interested in!
// ---- Scale the samples from in[], placing results in out[]


    // set vol_int to fixed-point representation of the volume factor
    // Q: should we use 32767 or 32768 in next line? why?
    vol_int = (int16_t)(VOLUME/100.0 * 32767.0);

    // Q: what is the purpose of these next two lines?
    in_cursor = in;
    out_cursor = out;
    limit = in + SAMPLES;

    // Q: what does it mean to "duplicate" values in the next line?
    __asm__ ("dup w1.8h,%w0"::"r"(vol_int)); // duplicate vol_int into v1.8h

    while ( in_cursor < limit ) {
        __asm__ (
            "ldr q0, [%[in_cursor]], #16  \n\t"
            // load eight samples into q0 (same as v0.8h)
            // from [in_cursor]
            // post-increment in_cursor by 16 bytes
            // ans store back into the pointer register

            "sqrdmulh v0.8h, v0.8h, v1.8h  \n\t"
            // with 32 signed integer output,
            // multiply each lane in v0 * v1 * 2
            // saturate results
            // store upper 16 bits of results into
            // the corresponding lane in v0

            "str q0, [%[out_cursor]],#16      \n\t"
            // store eight samples to [out_cursor]
            // post-increment out_cursor by 16 bytes
            // and store back into the pointer register

            // Q: What do these next three lines do?
            : [in_cursor]"+r"(in_cursor), [out_cursor]"+r"(out_cursor)
            : "r"(in_cursor),"r"(out_cursor)
            : "memory"
            );
    }

// --------------------------------------------------------------------

    for (x = 0; x < SAMPLES; x++) {
        ttl=(ttl+out[x])%1000;
    }

    // Q: are the results usable? are they correct?
    printf("Result: %d\n", ttl);

    return 0;

#endif
}

Note: We are checking our code on 5M Samples.

How to add SVE2 instructions?

We need to know more about SVE2. From the lab instructions, we have these links to ARM developers docs:
Arm Armv9-A A64 Instruction Set Architecture - https://developer.arm.com/documentation/ddi0602/2021-12/
Introduction to SVE2 - https://developer.arm.com/documentation/102340/0001/?lang=en
Intrinsics - Arm C Language Extensions for SVE (ACLE) - https://developer.arm.com/documentation/100987/latest
SVE Coding Considerations with Arm Compiler - Note that this documentation is specific to Arm's compiler, but most of it will apply to other compilers, including gcc - https://developer.arm.com/documentation/100748/0616/SVE-Coding-Considerations-with-Arm-Compiler

After reading, I started implementing the instructions for SVE2.
I decide to work with vol4.

Let's include header #include <arm_sve.h>
Our Makefile has already new instructions, for vol4
I have

 gcc -O3 -march=armv8-a+sve2 ${CCOPTS} vol4.c vol_createsample.o -o vol4
And for all other I decided to experiment:
gcc ${CCOPTS} vol1/2/3/5.c -march=armv8-a+sve2 vol_createsample.o -Ofast -o vol1/2/3/5

Also, I've decided to change the number of samples.

To run all the vol with SVE2 instruction, we need to run it with this command qemu-aarch64 .

Also, I updated the register as said in SVE instructions.

I had one error while working on this lab, but I found out it was because of number of samples.

Conclusion

⚠️ Computer Architecture Blog Post: Link

Links

🖇 Follow me on GitHub

🖇 Follow me on Twitter

_p.s This post was made for my Software Portability and Optimization class. Lab 6.