<?xml version="1.0" encoding="UTF-8"?>
<rss version="2.0" xmlns:atom="http://www.w3.org/2005/Atom" xmlns:dc="http://purl.org/dc/elements/1.1/">
  <channel>
    <title>DEV Community: Silverwarriorin</title>
    <description>The latest articles on DEV Community by Silverwarriorin (@silverwarriorin).</description>
    <link>https://dev.to/silverwarriorin</link>
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      <title>DEV Community: Silverwarriorin</title>
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    <item>
      <title>Designing some memory for the Z80 supercomputer</title>
      <dc:creator>Silverwarriorin</dc:creator>
      <pubDate>Wed, 18 May 2022 13:25:18 +0000</pubDate>
      <link>https://dev.to/silverwarriorin/designing-some-memory-for-the-z80-supercomputer-5a0f</link>
      <guid>https://dev.to/silverwarriorin/designing-some-memory-for-the-z80-supercomputer-5a0f</guid>
      <description>&lt;p&gt;I have heard the comparison of CPUs to brains, and while this is good for teaching the basics of computer operation, I tend to disagree with this analogy as you dive deeper into the computer hardware world. I disagree with this because a brain is made up of many parts, one of which is memory, which is a fundamental part of the operation of computer systems and biological organisms alike. That said today I am going to design a memory module for the Z80 supercomputer.&lt;/p&gt;

&lt;h2&gt;
  
  
  What is memory?
&lt;/h2&gt;

&lt;p&gt;Understanding exactly &lt;em&gt;what&lt;/em&gt; memory is and how it works is a fundamental part of designing computer systems. Think of memory in this case as the computers working memory, as well as its short term memory. We will use it to store variables, programs, results from computations as well any other storage that does not need to be stored after power down. &lt;/p&gt;

&lt;h2&gt;
  
  
  How much memory is enough?
&lt;/h2&gt;

&lt;p&gt;There is no definitive answer to this question, an iPhone with 1Mb of memory would not be very useful, but a Z80 with the same would be extremely overkill. In this case, due to the memory requirements of 1024 bit numbers, which take up a whole whopping 128 bytes of memory, or .128Kb I will have around 512Kb of working memory. Due note that only one 1024 bit number wouldn't be very useful, so in order to have 256 of them we would need 32Kb of RAM, still not 512Kb but that gives me a good amount of memory for future features.&lt;/p&gt;

&lt;h2&gt;
  
  
  What kind of memory?
&lt;/h2&gt;

&lt;p&gt;There are many kinds of memory, from the magnetic core memory used in the Apollo Guidance computer, to the NOR and NAND flash memory in the USB stick. However when talking about volatile memory, the kind used in RAM sticks and modules, SRAM and DRAM rule supreme. DRAM is expensive and generally higher capacity, however SRAM is abundant, uses less circuitry and is less expensive in smaller chip capacities. Finding memory chips with a capacity of 512Kb is not difficult, but first we need to convert to Kbits in order to make our search easier, this is a fairly easy tasks by just multiplying Kbytes by 8 to get Kbits, 512 * 8 = 4096 or 4Mbits. Another important characteristic of memory is the organization, memory comes in many different forms in order to be compatible with many different processors, in this case we need a 512x8 chip, meaning it has 512 banks of 8 bit values. The IS61C5128AL-10TLI by ISSI fits these requirements perfectly.&lt;/p&gt;

&lt;h2&gt;
  
  
  Wiring the chip to a Z80
&lt;/h2&gt;

&lt;h3&gt;
  
  
  Data lines
&lt;/h3&gt;

&lt;p&gt;Wiring the data lines for this chip is fairly straight forward and we can follow the same general steps as the processor&lt;br&gt;
&lt;a href="https://res.cloudinary.com/practicaldev/image/fetch/s--WtJCSmKF--/c_limit%2Cf_auto%2Cfl_progressive%2Cq_auto%2Cw_880/https://dev-to-uploads.s3.amazonaws.com/uploads/articles/565wjs3u3siqii2lscqz.png" class="article-body-image-wrapper"&gt;&lt;img src="https://res.cloudinary.com/practicaldev/image/fetch/s--WtJCSmKF--/c_limit%2Cf_auto%2Cfl_progressive%2Cq_auto%2Cw_880/https://dev-to-uploads.s3.amazonaws.com/uploads/articles/565wjs3u3siqii2lscqz.png" alt="Data Lines" width="880" height="690"&gt;&lt;/a&gt;&lt;/p&gt;

&lt;h3&gt;
  
  
  Control Lines
&lt;/h3&gt;

&lt;p&gt;Next up are the control lines for the memory chip, in order to address the chip properly we need to use some logic to ensure the chip is only read from during a memory read, and not an IO read, same goes for writing to the chip. This can be accomplished with a simple OR gate, since the RD/WR lines as well as the MEMRQ lines are active low, as well as the RD/WR lines on the SRAM chip.&lt;/p&gt;

&lt;p&gt;&lt;a href="https://res.cloudinary.com/practicaldev/image/fetch/s--OEJ-Hmqm--/c_limit%2Cf_auto%2Cfl_progressive%2Cq_auto%2Cw_880/https://dev-to-uploads.s3.amazonaws.com/uploads/articles/wsyozfua0qivgy85xi50.png" class="article-body-image-wrapper"&gt;&lt;img src="https://res.cloudinary.com/practicaldev/image/fetch/s--OEJ-Hmqm--/c_limit%2Cf_auto%2Cfl_progressive%2Cq_auto%2Cw_880/https://dev-to-uploads.s3.amazonaws.com/uploads/articles/wsyozfua0qivgy85xi50.png" alt="Control Lines" width="880" height="886"&gt;&lt;/a&gt;&lt;/p&gt;

&lt;h3&gt;
  
  
  Address Lines 0-15
&lt;/h3&gt;

&lt;p&gt;Connecting these is also straightforward, its only lines 16-18 that are a tad complicated&lt;/p&gt;

&lt;p&gt;&lt;a href="https://res.cloudinary.com/practicaldev/image/fetch/s--N7DQujHz--/c_limit%2Cf_auto%2Cfl_progressive%2Cq_auto%2Cw_880/https://dev-to-uploads.s3.amazonaws.com/uploads/articles/thmqv7rp6ruslt9murc4.png" class="article-body-image-wrapper"&gt;&lt;img src="https://res.cloudinary.com/practicaldev/image/fetch/s--N7DQujHz--/c_limit%2Cf_auto%2Cfl_progressive%2Cq_auto%2Cw_880/https://dev-to-uploads.s3.amazonaws.com/uploads/articles/thmqv7rp6ruslt9murc4.png" alt="First Address Lines" width="880" height="685"&gt;&lt;/a&gt;&lt;/p&gt;

&lt;h3&gt;
  
  
  Address Lines 16-18
&lt;/h3&gt;

&lt;p&gt;Now these lines are a bit more complicated because the Z80 only has 16 bits for address space, so we need to employ some tricks to expand this address space using a technique called bank switching. In order to do this we are going to use something called a D Latch in combination with some IO logic using something called a multiplexer. However that will be built in a separate module, however for now we can add the latches using a 74hc573&lt;/p&gt;

&lt;p&gt;&lt;a href="https://res.cloudinary.com/practicaldev/image/fetch/s--F-zvuvO3--/c_limit%2Cf_auto%2Cfl_progressive%2Cq_auto%2Cw_880/https://dev-to-uploads.s3.amazonaws.com/uploads/articles/85wfpee0si72ubat45c0.png" class="article-body-image-wrapper"&gt;&lt;img src="https://res.cloudinary.com/practicaldev/image/fetch/s--F-zvuvO3--/c_limit%2Cf_auto%2Cfl_progressive%2Cq_auto%2Cw_880/https://dev-to-uploads.s3.amazonaws.com/uploads/articles/85wfpee0si72ubat45c0.png" alt="Latches" width="880" height="705"&gt;&lt;/a&gt;&lt;/p&gt;

&lt;h3&gt;
  
  
  The ROM
&lt;/h3&gt;

&lt;p&gt;All computers need some sort of read only memory that executes immediately at startup, in this case I am going to use a 64Kbit or 8Kb, which may seem small but this can't be written to so it won't be used as RAM, for this I am going to use the at28hc64bf, This can be wired in the same way.&lt;/p&gt;

&lt;p&gt;&lt;a href="https://res.cloudinary.com/practicaldev/image/fetch/s--mAEHGdKK--/c_limit%2Cf_auto%2Cfl_progressive%2Cq_auto%2Cw_880/https://dev-to-uploads.s3.amazonaws.com/uploads/articles/csq9ca8vx5n7fpqnlhfc.png" class="article-body-image-wrapper"&gt;&lt;img src="https://res.cloudinary.com/practicaldev/image/fetch/s--mAEHGdKK--/c_limit%2Cf_auto%2Cfl_progressive%2Cq_auto%2Cw_880/https://dev-to-uploads.s3.amazonaws.com/uploads/articles/csq9ca8vx5n7fpqnlhfc.png" alt="Image description" width="880" height="847"&gt;&lt;/a&gt;&lt;/p&gt;

&lt;h3&gt;
  
  
  The #CS pin
&lt;/h3&gt;

&lt;p&gt;This pin is used in order to select the memory chips we are accessing, because this chip shares memory space with the ram chip, we effectively need to disable the RAM chip when in the ROMS address space, which can be done with a ton of OR gates. And an inverter.&lt;br&gt;
&lt;a href="https://res.cloudinary.com/practicaldev/image/fetch/s--cVms0Fcw--/c_limit%2Cf_auto%2Cfl_progressive%2Cq_auto%2Cw_880/https://dev-to-uploads.s3.amazonaws.com/uploads/articles/epygx9iq0y49ij1393dh.png" class="article-body-image-wrapper"&gt;&lt;img src="https://res.cloudinary.com/practicaldev/image/fetch/s--cVms0Fcw--/c_limit%2Cf_auto%2Cfl_progressive%2Cq_auto%2Cw_880/https://dev-to-uploads.s3.amazonaws.com/uploads/articles/epygx9iq0y49ij1393dh.png" alt="Image description" width="880" height="408"&gt;&lt;/a&gt;&lt;/p&gt;

&lt;h3&gt;
  
  
  Placing and routing
&lt;/h3&gt;

&lt;p&gt;This is the same process as last time, here is the result after using an autorouter.&lt;/p&gt;

&lt;p&gt;&lt;a href="https://res.cloudinary.com/practicaldev/image/fetch/s--bjqLhP8P--/c_limit%2Cf_auto%2Cfl_progressive%2Cq_auto%2Cw_880/https://dev-to-uploads.s3.amazonaws.com/uploads/articles/f3op6gegv22y91ltnmkh.png" class="article-body-image-wrapper"&gt;&lt;img src="https://res.cloudinary.com/practicaldev/image/fetch/s--bjqLhP8P--/c_limit%2Cf_auto%2Cfl_progressive%2Cq_auto%2Cw_880/https://dev-to-uploads.s3.amazonaws.com/uploads/articles/f3op6gegv22y91ltnmkh.png" alt="Image description" width="880" height="1241"&gt;&lt;/a&gt;&lt;/p&gt;

&lt;h3&gt;
  
  
  What's next
&lt;/h3&gt;

&lt;p&gt;There are many more boards to design, including control boards, expansion modules such as an enhanced ALU, output boards and all sorts of other boards, but I think next I will design the output board, since many of the expansion boards need to be designed before the control boards.&lt;/p&gt;

</description>
      <category>supercomputing</category>
      <category>programming</category>
      <category>hardware</category>
      <category>retro</category>
    </item>
    <item>
      <title>Designing an 8-bit supercomputer</title>
      <dc:creator>Silverwarriorin</dc:creator>
      <pubDate>Fri, 13 May 2022 19:16:12 +0000</pubDate>
      <link>https://dev.to/silverwarriorin/designing-an-8-bit-supercomputer-5hbm</link>
      <guid>https://dev.to/silverwarriorin/designing-an-8-bit-supercomputer-5hbm</guid>
      <description>&lt;p&gt;In this short series I will be designing one of the first Z80 based supercomputers, in order to accomplish this we need to make useful modules for the multiple Z80 processors to use, this will include external APUs that can handle the large floating point numbers that the machine will be able to compute.&lt;/p&gt;

&lt;h2&gt;
  
  
  Z80 Compute Modules
&lt;/h2&gt;

&lt;p&gt;In order for this machine to have any usable modules first we need to build some Z80 processor cards, this can easily be accomplished with a few small boards.&lt;/p&gt;

&lt;h3&gt;
  
  
  The Z80
&lt;/h3&gt;

&lt;p&gt;The Z80 is an 8-bit processor with 16 bits of address space, there are a multitude of control and status lines as well that need to be controlled in order for the processor to run properly, first of which are the power (+5V) and ground (GND) connections, which supply power to the Z80, the +5V line should also have a decoupling capacitor to ground with a 100nF value.&lt;/p&gt;

&lt;p&gt;&lt;a href="https://res.cloudinary.com/practicaldev/image/fetch/s--tQ4oz7qJ--/c_limit%2Cf_auto%2Cfl_progressive%2Cq_auto%2Cw_880/https://dev-to-uploads.s3.amazonaws.com/uploads/articles/rbll1u05n3ix70gm88hh.png" class="article-body-image-wrapper"&gt;&lt;img src="https://res.cloudinary.com/practicaldev/image/fetch/s--tQ4oz7qJ--/c_limit%2Cf_auto%2Cfl_progressive%2Cq_auto%2Cw_880/https://dev-to-uploads.s3.amazonaws.com/uploads/articles/rbll1u05n3ix70gm88hh.png" alt="Z80 with the power connected" width="880" height="583"&gt;&lt;/a&gt;&lt;/p&gt;

&lt;p&gt;Next are the control signals, ordinarily you would tie the majority of these to ground with a resistor, however in this case they will be needed later down the design process in order to control and monitor certain aspects of the running system, as such we will tie them to ground with an external input for control using a D Type latch. &lt;/p&gt;

&lt;p&gt;&lt;a href="https://res.cloudinary.com/practicaldev/image/fetch/s--sKJgsfva--/c_limit%2Cf_auto%2Cfl_progressive%2Cq_auto%2Cw_880/https://dev-to-uploads.s3.amazonaws.com/uploads/articles/incxm9t952u8dk8tghur.png" class="article-body-image-wrapper"&gt;&lt;img src="https://res.cloudinary.com/practicaldev/image/fetch/s--sKJgsfva--/c_limit%2Cf_auto%2Cfl_progressive%2Cq_auto%2Cw_880/https://dev-to-uploads.s3.amazonaws.com/uploads/articles/incxm9t952u8dk8tghur.png" alt="Z80 with IO sorted" width="880" height="911"&gt;&lt;/a&gt;&lt;/p&gt;

&lt;p&gt;There is a lot going on here, but basically I am attaching these pins to a latch so external circuitry can control them.&lt;/p&gt;

&lt;p&gt;The final pieces of the puzzle for now are the data lines and address lines as well as a few other outputs and inputs, these will be used in tandem with the BUSREQ control line in order for the processors to access the memory and peripherals.&lt;/p&gt;

&lt;p&gt;&lt;a href="https://res.cloudinary.com/practicaldev/image/fetch/s--Z1_1uboT--/c_limit%2Cf_auto%2Cfl_progressive%2Cq_auto%2Cw_880/https://dev-to-uploads.s3.amazonaws.com/uploads/articles/vllqplcxpland1t08fe7.png" class="article-body-image-wrapper"&gt;&lt;img src="https://res.cloudinary.com/practicaldev/image/fetch/s--Z1_1uboT--/c_limit%2Cf_auto%2Cfl_progressive%2Cq_auto%2Cw_880/https://dev-to-uploads.s3.amazonaws.com/uploads/articles/vllqplcxpland1t08fe7.png" alt="All hooked up" width="880" height="866"&gt;&lt;/a&gt;&lt;/p&gt;

&lt;p&gt;With this being the final schematic.&lt;/p&gt;

&lt;h3&gt;
  
  
  Routing the traces
&lt;/h3&gt;

&lt;p&gt;Routing PCB traces is a massive pain, so I am going to use an autorouter to do the job for me, more specifically a tool called FreeRouting&lt;/p&gt;
&lt;div class="ltag-github-readme-tag"&gt;
  &lt;div class="readme-overview"&gt;
    &lt;h2&gt;
      &lt;img src="https://res.cloudinary.com/practicaldev/image/fetch/s--566lAguM--/c_limit%2Cf_auto%2Cfl_progressive%2Cq_auto%2Cw_880/https://dev.to/assets/github-logo-5a155e1f9a670af7944dd5e12375bc76ed542ea80224905ecaf878b9157cdefc.svg" alt="GitHub logo"&gt;
      &lt;a href="https://github.com/freerouting"&gt;
        freerouting
      &lt;/a&gt; / &lt;a href="https://github.com/freerouting/freerouting"&gt;
        freerouting
      &lt;/a&gt;
    &lt;/h2&gt;
    &lt;h3&gt;
      Advanced PCB auto-router
    &lt;/h3&gt;
  &lt;/div&gt;
  &lt;div class="ltag-github-body"&gt;
    
&lt;div id="readme" class="md"&gt;
&lt;p&gt;
&lt;a rel="noopener noreferrer" href="https://raw.githubusercontent.com/freerouting/freerouting/master/design/social_preview/freerouting_social_preview_1280x960_v2.png"&gt;&lt;img src="https://res.cloudinary.com/practicaldev/image/fetch/s--bMd-UNOa--/c_limit%2Cf_auto%2Cfl_progressive%2Cq_auto%2Cw_880/https://raw.githubusercontent.com/freerouting/freerouting/master/design/social_preview/freerouting_social_preview_1280x960_v2.png" alt="Freerouting" title="Freerouting"&gt;&lt;/a&gt;
&lt;/p&gt;

&lt;h1&gt;
Freerouting&lt;/h1&gt;

&lt;h5&gt;
Freerouting is an advanced autorouter for all PCB programs that support the standard Specctra or Electra DSN interface.&lt;/h5&gt;

&lt;p&gt;
    &lt;a href="https://github.com/freerouting/freerouting/releases"&gt;&lt;img src="https://camo.githubusercontent.com/40a22b1300be9f8ab0a05c0ca29ced4275d1e7e7cd092cc167062e51c735113f/68747470733a2f2f696d672e736869656c64732e696f2f6769746875622f762f72656c656173652f66726565726f7574696e672f66726565726f7574696e67" alt="Release version"&gt;&lt;/a&gt;
    &lt;a href="https://github.com/freerouting/freeroutingLICENSE"&gt;&lt;img src="https://camo.githubusercontent.com/70bb9725a94638d71dc776002d29bc1089e27f85709948ad9e7fb2f0cd379a68/68747470733a2f2f696d672e736869656c64732e696f2f6769746875622f6c6963656e73652f66726565726f7574696e672f66726565726f7574696e67" alt="License"&gt;&lt;/a&gt;
&lt;/p&gt;

&lt;h3&gt;
👉 This project needs JAVA and UI/UX volunteers! Contact @andrasfuchs for details! 👈
&lt;/h3&gt;



&lt;p&gt;&lt;a href="https://github.com/freerouting/freerouting/releases"&gt;Installers for Windows and Linux can be downloaded here.&lt;/a&gt;&lt;/p&gt;

&lt;h2&gt;
Introduction&lt;/h2&gt;

&lt;p&gt;This software can be used together with all host PCB design software systems containing a standard Specctra or Electra DSN interface. It imports .DSN files generated by the Specctra interface of the host system and exports .SES Specctra session files.&lt;/p&gt;

&lt;p&gt;Altough the software can be used for manual routing in 90 degree, 45 degree and free angle modes, it's main focus is on autorouting.&lt;/p&gt;

&lt;h3&gt;
Getting started&lt;/h3&gt;


&lt;ol&gt;
&lt;li&gt;

&lt;p&gt;After launching freerouting, a window appears promting you to select your exported .DSN design file
&lt;a rel="noopener noreferrer" href="https://user-images.githubusercontent.com/910321/167868226-f046da72-357d-44f6-ba0d-ee27d34725c1.png"&gt;&lt;img src="https://res.cloudinary.com/practicaldev/image/fetch/s--QPQPwUO6--/c_limit%2Cf_auto%2Cfl_progressive%2Cq_auto%2Cw_880/https://user-images.githubusercontent.com/910321/167868226-f046da72-357d-44f6-ba0d-ee27d34725c1.png" alt="image"&gt;&lt;/a&gt;&lt;/p&gt;
&lt;/li&gt;
&lt;li&gt;
&lt;p&gt;After opening a design you can start the autorouter with the button in the toolbar on top of the board window
&lt;a rel="noopener noreferrer" href="https://user-images.githubusercontent.com/910321/167868601-1510f75d-73a2-4321-ac03-2dd4a91732eb.png"&gt;&lt;img src="https://res.cloudinary.com/practicaldev/image/fetch/s--KI9-g4GJ--/c_limit%2Cf_auto%2Cfl_progressive%2Cq_auto%2Cw_880/https://user-images.githubusercontent.com/910321/167868601-1510f75d-73a2-4321-ac03-2dd4a91732eb.png" alt="image"&gt;&lt;/a&gt;&lt;/p&gt;
&lt;/li&gt;
&lt;li&gt;
&lt;p&gt;While autorouter is running you can…&lt;/p&gt;
&lt;/li&gt;
&lt;/ol&gt;
&lt;/div&gt;
  &lt;/div&gt;
  &lt;div class="gh-btn-container"&gt;&lt;a class="gh-btn" href="https://github.com/freerouting/freerouting"&gt;View on GitHub&lt;/a&gt;&lt;/div&gt;
&lt;/div&gt;


&lt;p&gt;Prior to routing:&lt;br&gt;
&lt;a href="https://res.cloudinary.com/practicaldev/image/fetch/s--W5-g90lR--/c_limit%2Cf_auto%2Cfl_progressive%2Cq_auto%2Cw_880/https://dev-to-uploads.s3.amazonaws.com/uploads/articles/b5lkp8k7p1d52ett6zfg.png" class="article-body-image-wrapper"&gt;&lt;img src="https://res.cloudinary.com/practicaldev/image/fetch/s--W5-g90lR--/c_limit%2Cf_auto%2Cfl_progressive%2Cq_auto%2Cw_880/https://dev-to-uploads.s3.amazonaws.com/uploads/articles/b5lkp8k7p1d52ett6zfg.png" alt="Prior to routing" width="880" height="853"&gt;&lt;/a&gt;&lt;/p&gt;

&lt;p&gt;After reorganizing:&lt;br&gt;
&lt;a href="https://res.cloudinary.com/practicaldev/image/fetch/s--wFuYpOsh--/c_limit%2Cf_auto%2Cfl_progressive%2Cq_auto%2Cw_880/https://dev-to-uploads.s3.amazonaws.com/uploads/articles/qz5fakwfxexx4plucu1d.png" class="article-body-image-wrapper"&gt;&lt;img src="https://res.cloudinary.com/practicaldev/image/fetch/s--wFuYpOsh--/c_limit%2Cf_auto%2Cfl_progressive%2Cq_auto%2Cw_880/https://dev-to-uploads.s3.amazonaws.com/uploads/articles/qz5fakwfxexx4plucu1d.png" alt="Image description" width="880" height="853"&gt;&lt;/a&gt;&lt;/p&gt;

&lt;p&gt;After routing:&lt;br&gt;
&lt;a href="https://res.cloudinary.com/practicaldev/image/fetch/s--yO_WbGCl--/c_limit%2Cf_auto%2Cfl_progressive%2Cq_auto%2Cw_880/https://dev-to-uploads.s3.amazonaws.com/uploads/articles/9kr2m3cbtepmm5wxq3e3.png" class="article-body-image-wrapper"&gt;&lt;img src="https://res.cloudinary.com/practicaldev/image/fetch/s--yO_WbGCl--/c_limit%2Cf_auto%2Cfl_progressive%2Cq_auto%2Cw_880/https://dev-to-uploads.s3.amazonaws.com/uploads/articles/9kr2m3cbtepmm5wxq3e3.png" alt="Image description" width="880" height="852"&gt;&lt;/a&gt;&lt;/p&gt;

&lt;p&gt;3D Render:&lt;br&gt;
&lt;a href="https://res.cloudinary.com/practicaldev/image/fetch/s--0I6BdNXY--/c_limit%2Cf_auto%2Cfl_progressive%2Cq_auto%2Cw_880/https://dev-to-uploads.s3.amazonaws.com/uploads/articles/v83zbpbesgv7rik1a854.png" class="article-body-image-wrapper"&gt;&lt;img src="https://res.cloudinary.com/practicaldev/image/fetch/s--0I6BdNXY--/c_limit%2Cf_auto%2Cfl_progressive%2Cq_auto%2Cw_880/https://dev-to-uploads.s3.amazonaws.com/uploads/articles/v83zbpbesgv7rik1a854.png" alt="Image description" width="880" height="655"&gt;&lt;/a&gt;&lt;/p&gt;

&lt;p&gt;Next Up: Memory Modules&lt;/p&gt;

</description>
      <category>retro</category>
      <category>z80</category>
      <category>hardware</category>
      <category>programming</category>
    </item>
  </channel>
</rss>
