DEV Community: 千田　智也

From 1,464 Unrouted Nets to Zero — But I'm Still Not Calling This Board Manufacturable

千田　智也 — Sun, 25 Oct 2026 04:14:44 +0000

TL;DR

Part 2 of letting an AI agent (Codex, driving KiCad through its CLI) design my Raspberry Pi CM4 Mini-ITX IO board. The board is now fully routed and adopted as the official design: ERC 0, DRC 0, unrouted nets 0, schematic↔PCB mismatches 0. Vendor-model power simulations that timed out last time now complete all 12 cases. And yet the strict all-checks pass flag is still false, and I am not releasing Gerbers — because a fault simulation leaves about −1.35 V on a power controller pin, and nobody has explained it away yet.

This is a series: Part 1 — 486 checks and the first scoreboard.

The scoreboard: Part 1 → Part 2

Check	Part 1 (Oct 24)	Part 2 (Oct 25)
ERC errors	0	0
DRC errors	244	0
Unrouted nets	1,464	0
Schematic↔PCB mismatches	0	0
Warnings	188	124 (94 copper slivers, 21 vias, 9 track ends)
Board	placement stage, 0 tracks	170×170 mm, 8 layers, 963 footprints, 18,500 tracks + vias
Vendor-model startup sims	timed out twice, undetermined	12/12 cases completed to 300 ms
Strict all-checks pass	false	still false (warnings + one unresolved fault case)

The formal re-verification ran on 2026-10-25 at 11:42 JST and also confirmed that none of the 52 input files changed while the checks were running — the loop checks its own homework, including whether the homework moved.

Top side. The silkscreen still says "ROUTED ENGINEERING PROTOTYPE / DO NOT FABRICATE" — that text has earned its place.

Bottom side, with the power stages and the back of the ATX connector.

What it took to finish routing

High-speed differential sections were reworked segment by segment: length-error cancellation across the AC-coupling capacitors, layer usage, and via depth differences were corrected. On D5, both capacitors moved to the B side and the clock termination was repositioned. The loop also verified that no existing signal's reference GND plane gained new splits.
Power monitor window adjusted: R119 went 150 Ω → 200 Ω and R272 9.31 kΩ → 9.42 kΩ, synced across schematic, PCB, BOM and part data. A pin type on U300.A8 was corrected to match the actual output.
The verification scripts themselves got fixed: a stale dependency on old power summaries and an absolute/relative path mismatch in file collation. The checker now verifies that the board, the part data and the stored analysis results actually agree with each other.

Simulations: the static picture holds, the dynamic picture advanced

Re-run on the adopted board:

384 passive SPICE conditions across the 6 base power rails
Voltage drop including 357 shared-GND points
68 control/sense paths, 16 power sections, 48 capacitor paths
32,768 PG/UV analysis conditions — the tightest power-good re-engagement margin across the 4 branches is about 5.345 mV

All of that holds within the declared static conditions. And the part that was stuck last time moved: with the original ADI/Nexperia vendor models, 4 power branches × (startup, output short circuit, normal input loss) = 12 cases, all numerically completed to 300 ms, passing limited terminal-voltage and MOSFET-voltage checks against the saved waveforms.

The catch: −1.35 V that nobody has explained away

A separate internal-fault diagnosis puts a 1 mΩ short on the upstream BUCK side. On the latest board, the saved waveforms still show:

LTC4229 pin	Minimum in saved waveform
IN	≈ −1.338 V
DSRC	≈ −1.353 V

The check floor is −0.3 V. Added-capacitor and snubber proposals did not fix it, so they were not adopted into the board. Two honest caveats cut in opposite directions: this is a partial model with assumed parasitics and supply response, so it does not prove the real board would be damaged — but "the model might be wrong" is not a passing grade either. Until this is resolved, the design does not get called complete, problem-free, or manufacturable, and the Gerber/drill/assembly outputs stay unreleased.

Still open after that: fault tolerance, the full power control loop, high-speed SI, thermal/EMI, simultaneous real-world I/O, and case/assembly/manufacturing checks.

Questions for you

When a partial SPICE model shows a below-absolute-maximum pin voltage that layout tweaks won't move, where do you look first — the model's assumed parasitics, or the circuit?
Would you fabricate a board whose own verification suite refuses to say "pass"?

Series: Part 1 covered the spec (DisplayPort + HDMI, 2× USB-A, 2× USB-C, a PCIe switch feeding 2 slots + 2 M.2, ATX 24-pin power) and the first 486 power-analysis conditions. The Japanese edition of Part 1 is on Qiita. Part 2 in Japanese is on Qiita too.

I Let an AI Agent Design My Raspberry Pi CM4 Board — 486 Checks Later, Here's the Scoreboard

千田　智也 — Sat, 24 Oct 2026 16:07:46 +0000

TL;DR: For two days, an AI coding agent (Codex) has been designing a Mini-ITX I/O board for the Raspberry Pi CM4 by driving KiCad from the command line in an inspect → fix loop. ERC is clean, the 5V rail passed 486 analysis conditions, routing has started — and the power design is fighting back. This is build log #1.

I'm building a carrier board for the Raspberry Pi Compute Module 4. Or, more accurately: I'm watching one get built.

The designer is an AI agent working through kicad-cli and scripted checks — running ERC/DRC, comparing schematic and PCB nets, doing DC analysis on the power rails, fixing what the checks flag, and re-running. My job is reading its inspection reports and looking at renders. It feels less like prompting a chatbot and more like supervising a very fast, very literal junior engineer who never sleeps and documents everything.

The spec is a bit unhinged

Mini-ITX form factor, ATX 24-pin power
DisplayPort ×1, HDMI ×1
USB-A ×2, USB-C ×2
A PCIe switch feeding PCIe slots ×2 + M.2 ×2

If you know the CM4, you see the problem immediately: the module exposes one PCIe Gen2 x1 lane, and DisplayPort isn't native to it. Cramming this into Mini-ITX, with ATX soft-power handling on top, is exactly the kind of dense, constraint-heavy problem I wanted to throw at the loop.

The loop's toolbox

Everything goes through the CLI and scripts, roughly like this:

kicad-cli sch erc board.kicad_sch            # electrical rule check
kicad-cli pcb drc board.kicad_pcb            # design rule check
# + custom scripts: net consistency, power DC analysis across tolerances

No GUI, no mouse. Just checks, fixes, and re-checks — hundreds of iterations.

The scoreboard after 2 days

Schematic ERC: 0 errors, 3 warnings
Schematic ↔ PCB net mismatches: 0
CM4 5V rail DC analysis: 486 conditions (reference/resistor tolerance, temperature coefficient, input bias) → output range 4.909–5.092 V. Inside the CM4's 5V ±5% requirement, with ~0.16 V of margin on the low side
Startup analysis with the manufacturer's power model: timed out twice. Still undetermined, and the loop says so plainly. I trust a tool more when it admits what it hasn't proven
At placement stage: 1,464 unrouted segments, 244 DRC errors. Routing has now started, so those numbers are finally moving

An 8mm × 10mm drama

The moment that made me start this log is a clearance check in the power section. On the front copper, a signal trace (D4 TX N) has to pass the projection of the back-side MOSFET's drain pad — Q901, sitting next to the R900 current shunt. The drain is a high-current power net, so the loop projects the back-side pad onto the front view and routes the signal around it, checking clearance point by point.

Unglamorous, invisible work. Also the work that decides whether a board works at all.

Where it's losing (for now)

IR drop. Under load, the power rails sag more than they should. The loop has started flagging it on its own
The 1.1 V rail still drops too much
Power sequencing for the expansion cards is unfinished — a board that boots the CM4 but browns out a PCIe card is a paperweight
MOSFET selection for the power stage is still open. Those FETs set the Rds(on) losses, so the choice feeds straight back into the IR-drop problem. The loop is researching candidates right now

The silkscreen on the current layout literally reads "UNROUTED ENGINEERING DRAFT / DO NOT FABRICATE". Accurate.

Questions for people who've done this

If you've designed CM4 carrier boards:

How did you handle power sequencing for downstream PCIe devices?
What MOSFETs did you land on for the input power stage?

Genuinely collecting answers — the loop and I are still deciding, and I'd rather learn from your scars than earn my own.

Part 2 when routing finishes (or when the startup analysis finally completes instead of timing out — whichever comes first).

DEV Community: 千田 智也