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    <title>DEV Community: Yetkin Akyuz</title>
    <description>The latest articles on DEV Community by Yetkin Akyuz (@user-name).</description>
    <link>https://dev.to/user-name</link>
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      <title>DEV Community: Yetkin Akyuz</title>
      <link>https://dev.to/user-name</link>
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    <item>
      <title>Von Neumann &amp; Harvard Architectures</title>
      <dc:creator>Yetkin Akyuz</dc:creator>
      <pubDate>Mon, 12 Apr 2021 08:10:25 +0000</pubDate>
      <link>https://dev.to/user-name/von-neumann-harvard-architectures-30f5</link>
      <guid>https://dev.to/user-name/von-neumann-harvard-architectures-30f5</guid>
      <description>&lt;p&gt;Considering the problem of how to access memory in CPU level, There are two popular designs: Von Neumann and Harvard architectures.&lt;/p&gt;


&lt;center&gt;
&lt;img src="https://media2.dev.to/dynamic/image/width=800%2Cheight=%2Cfit=scale-down%2Cgravity=auto%2Cformat=auto/https%3A%2F%2Fyetkinakyuz.com%2Fwp-content%2Fuploads%2F2021%2F03%2FVon-Neumann.png" alt="Von Neumann Architecture" width="800" height="400"&gt;&lt;p&gt;Figure 1: Von Neumann Architecture [2]&lt;/p&gt;


&lt;/center&gt;

&lt;p&gt;The Von Neumann architecture, created by John Von Neumann in 1945, is a computer architecture in which data and instruction memories share a single storage unit. There is only one bus each for memory addresses and data transmission.&lt;/p&gt;

&lt;p&gt;&lt;a href="https://media2.dev.to/dynamic/image/width=800%2Cheight=%2Cfit=scale-down%2Cgravity=auto%2Cformat=auto/https%3A%2F%2Fdev-to-uploads.s3.amazonaws.com%2Fuploads%2Farticles%2Fs4nx302hg3lj5xyyd51a.png" class="article-body-image-wrapper"&gt;&lt;img src="https://media2.dev.to/dynamic/image/width=800%2Cheight=%2Cfit=scale-down%2Cgravity=auto%2Cformat=auto/https%3A%2F%2Fdev-to-uploads.s3.amazonaws.com%2Fuploads%2Farticles%2Fs4nx302hg3lj5xyyd51a.png" alt="Harvard Architecture" width="720" height="404"&gt;&lt;/a&gt;&lt;/p&gt;
&lt;center&gt;&lt;p&gt;Figure 2: Harvard Architecture [3]&lt;/p&gt;&lt;/center&gt;

&lt;p&gt;In the Harvard architecture, which takes its name from Harvard Mark I, the computer for which it is used for the first time, data and instruction memories are physically separated from each other. Both have separate memory address bus and data bus. When a program runs, instruction flow and data flow take place over separate sets of buses.&lt;/p&gt;

&lt;h3&gt;
  
  
  The Von Neumann Bottleneck
&lt;/h3&gt;

&lt;p&gt;The fact that a single bus transmits both instructions and data leads to a problem called The Von Neumann Bottleneck. Because a single bus can only access one class of memory at a time, the throughput is lower than the speed at which the CPU can run. Therefore, the CPU has to constantly wait for the required data to be transported, resulting in a drastic drop in processing speed.&lt;/p&gt;

&lt;p&gt;&lt;a href="https://media2.dev.to/dynamic/image/width=800%2Cheight=%2Cfit=scale-down%2Cgravity=auto%2Cformat=auto/https%3A%2F%2Fdev-to-uploads.s3.amazonaws.com%2Fuploads%2Farticles%2Fib7fcvio7owdoxm9kgui.png" class="article-body-image-wrapper"&gt;&lt;img src="https://media2.dev.to/dynamic/image/width=800%2Cheight=%2Cfit=scale-down%2Cgravity=auto%2Cformat=auto/https%3A%2F%2Fdev-to-uploads.s3.amazonaws.com%2Fuploads%2Farticles%2Fib7fcvio7owdoxm9kgui.png" alt="Performance of processor and memory" width="800" height="444"&gt;&lt;/a&gt;&lt;/p&gt;
&lt;center&gt;&lt;p&gt;Figure 3: Performance of processor and memory [4]&lt;/p&gt;&lt;/center&gt;

&lt;p&gt;The most logical solution is to use a cache, which holds the last data used by the processor. In this way, the processor does not need to access memory and the expected time is compensated.&lt;/p&gt;

&lt;p&gt;The problem is experienced in general today, rather than only in Von Neumann architecture. Memory technology, which cannot keep up with the development of processor technology, greatly increases this problem.&lt;/p&gt;

&lt;h3&gt;
  
  
  The Modified Harvard Architecture
&lt;/h3&gt;

&lt;p&gt;&lt;a href="https://media2.dev.to/dynamic/image/width=800%2Cheight=%2Cfit=scale-down%2Cgravity=auto%2Cformat=auto/https%3A%2F%2Fdev-to-uploads.s3.amazonaws.com%2Fuploads%2Farticles%2Fj5dtkthxovlk9802talo.jpg" class="article-body-image-wrapper"&gt;&lt;img src="https://media2.dev.to/dynamic/image/width=800%2Cheight=%2Cfit=scale-down%2Cgravity=auto%2Cformat=auto/https%3A%2F%2Fdev-to-uploads.s3.amazonaws.com%2Fuploads%2Farticles%2Fj5dtkthxovlk9802talo.jpg" alt="Modified Harvard Architecture" width="529" height="596"&gt;&lt;/a&gt;&lt;/p&gt;
&lt;center&gt;&lt;p&gt;Figure 4: Modified Harvard Architecture [6]&lt;/p&gt;&lt;/center&gt;

&lt;p&gt;The Modified Harvard architecture is a variation of the Harvard computer architecture that allows the contents of the instruction memory to be accessed as data, unlike the pure Harvard architecture. It supports higher performance concurrent data and instruction access of Harvard architecture. It also loosens the distinction between commands and data. Two separate caches are used, supported by the same memory address, one for commands and the other for data. In short, while Harvard architecture is used on the cache side, Von Neumann architecture is used on the main memory side.&lt;/p&gt;

&lt;p&gt;Most of the modern computers described as Harvard architecture are actually modified Harvard architecture.&lt;/p&gt;

&lt;h3&gt;
  
  
  References
&lt;/h3&gt;

&lt;ol&gt;
&lt;li&gt;Zhu, Y. (Jun 2018). Embedded Systems with ARM Cortex-M Microcontrollers in Assembly Language and C&lt;/li&gt;
&lt;li&gt;&lt;a href="https://en.wikipedia.org/wiki/Von_Neumann_architecture" rel="noopener noreferrer"&gt;Wikipedia. Von Neumann Architecture&lt;/a&gt;&lt;/li&gt;
&lt;li&gt;&lt;a href="https://en.wikipedia.org/wiki/Harvard_architecture" rel="noopener noreferrer"&gt;Wikipedia. Harvard Architecture&lt;/a&gt;&lt;/li&gt;
&lt;li&gt;&lt;a href="https://iopscience.iop.org/article/10.1088/1742-6596/523/1/012002/pdf" rel="noopener noreferrer"&gt;Nowak, A. (2014). Opportunities and choice in a new vector era&lt;/a&gt;&lt;/li&gt;
&lt;li&gt;&lt;a href="https://en.wikipedia.org/wiki/Modified_Harvard_architecture" rel="noopener noreferrer"&gt;Wikipedia. Modified Harvard Architecture&lt;/a&gt;&lt;/li&gt;
&lt;li&gt;&lt;a href="https://blocksandfiles.com/2019/08/20/back-to-the-future-with-persistent-memory/" rel="noopener noreferrer"&gt;Blocksandfiles. (2019). Back to the future with persistent memory&lt;/a&gt;&lt;/li&gt;
&lt;/ol&gt;

</description>
      <category>computerscience</category>
      <category>todayilearned</category>
    </item>
    <item>
      <title>My First Project: Design and Fabrication of a Cost-Effective Spin Coater</title>
      <dc:creator>Yetkin Akyuz</dc:creator>
      <pubDate>Fri, 08 Jan 2021 06:54:24 +0000</pubDate>
      <link>https://dev.to/user-name/my-first-project-2pg0</link>
      <guid>https://dev.to/user-name/my-first-project-2pg0</guid>
      <description>&lt;p&gt;Hi there!&lt;/p&gt;

&lt;p&gt;I would like to share with you my first project "Low Cost Spin Coater Device" that I made for the Engineering Design class I took in my undergraduate education in Electrical &amp;amp; Electronics Engineering.&lt;/p&gt;

&lt;p&gt;With this project, I aimed to support the free software philosophy through to the project's completely free and open source design, which has MIT License, and to make the product accessible to a wider audience than the ones sold in the market with low cost.&lt;/p&gt;

&lt;p&gt;The spin coating method is a commonly used coating method to obtain uniform thin material films, usually polymers, on the surface of a substrate using the concept of centrifugal force. This method, which is easy to use, safe and inexpensive, is highly preferred for many applications where high quality layers are required such as microcircuit manufacturing, compact discs, magnetic disk coatings, polymer electronic devices.&lt;/p&gt;

&lt;p&gt;The device allows the user to define up to 10 different stages in 500-7200 RPM and 5-3600 seconds intervals, except for 5 different quick programs in its memory.&lt;/p&gt;

&lt;p&gt;The device, which I completed with a cost of less than 70$, can reach the desired speeds within an average of 5 seconds and keep it constant with an average of 6% error. This error can decrease to 2% at high speeds.&lt;/p&gt;

&lt;p&gt;You can access all parts of the project on GitHub and use it as you wish.&lt;/p&gt;

&lt;p&gt;GitHub Link: &lt;a href="https://github.com/yetkinakyuz/SpinCoater" rel="noopener noreferrer"&gt;https://github.com/yetkinakyuz/SpinCoater&lt;/a&gt;&lt;/p&gt;

&lt;p&gt;&lt;a href="https://media2.dev.to/dynamic/image/width=800%2Cheight=%2Cfit=scale-down%2Cgravity=auto%2Cformat=auto/https%3A%2F%2Fdev-to-uploads.s3.amazonaws.com%2Fi%2Fgvg31qjschkoh7h6nxtj.jpeg" class="article-body-image-wrapper"&gt;&lt;img src="https://media2.dev.to/dynamic/image/width=800%2Cheight=%2Cfit=scale-down%2Cgravity=auto%2Cformat=auto/https%3A%2F%2Fdev-to-uploads.s3.amazonaws.com%2Fi%2Fgvg31qjschkoh7h6nxtj.jpeg" alt="SpinCoater Project Result" width="800" height="800"&gt;&lt;/a&gt;&lt;/p&gt;

</description>
      <category>beginners</category>
      <category>python</category>
      <category>programming</category>
      <category>showdev</category>
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