What is the internal clock in STM32 timer?

In STM32 timer terminology, the “internal clock” usually means the timer is clocked by CK_INT — a clock that comes from inside the MCU’s clock tree (RCC), not from an external pin.

What CK_INT actually is

For most STM32 families, a timer’s internal clock source is the timer kernel clock derived from the APB bus clock:

• Timers on APB1 use PCLK1 → TIMxCLK
• Timers on APB2 use PCLK2 → TIMxCLK

And there’s a very important rule on many STM32 lines:

Timer clock “x2” rule (common on many STM32)

If the APB prescaler is 1:

• TIMxCLK = PCLKx

If the APB prescaler is > 1:

• TIMxCLK = 2 × PCLKx

So if you slow down APB with a prescaler, the timer often still gets a doubled clock so timer performance doesn’t drop as much.

Note: The exact “x2” behavior can vary by STM32 family/sub-line, but the above is the classic rule for many STM32 (e.g., lots of STM32F1/F4-class behavior).

How it drives the timer counter

The timer doesn’t count at TIMxCLK directly. It goes through the prescaler:

• Counter clock (CK_CNT) = TIMxCLK / (PSC + 1)

Then counting mode matters:

• Upcounting: update event happens every (ARR + 1) counter ticks
• So update frequency is roughly: f_update = CK_CNT / (ARR + 1)

“Internal clock” vs other timer clock sources

When you configure a timer, the counter clock can come from:

• Internal clock (CK_INT) (most common)
• External clock from a pin (ETR or TIx)
• Internal trigger (ITR) from another timer (timer-to-timer sync)
• Encoder mode, etc.

So “internal clock” specifically means: the timer is running from the MCU clock tree, not an external signal.

Quick example

Say:

• PCLK1 = 50 MHz
• APB1 prescaler = 2 (so prescaler > 1 → timer clock doubles)
• Then TIMxCLK = 2 × 50 MHz = 100 MHz
• If PSC = 99 → CK_CNT = 100 MHz / (99+1) = 1 MHz
• If ARR = 999 → update event = 1 MHz / (999+1) = 1 kHz