The principle, configuration, and simulation of XADC IP in Xilinx FPGA

Below is a practical, engineering-style view of XADC (Xilinx/AMD 7-series on-chip ADC) + XADC Wizard IP: principle, Vivado configuration, and simulation.

1) Principle: what the XADC block actually is
Hardware inside the FPGA

On 7-series devices, XADC is a hard macro that includes:

• Dual 12-bit ADCs (up to 1 MSPS) plus on-chip sensors (die temperature, VCCINT/VCCAUX/VCCBRAM, etc.).
• Access to up to 17 external analog channels (1 dedicated VP/VN differential pair + up to 16 VAUX differential pairs, depending on package/device).
• A register interface where conversion results land in status registers, and configuration lives in control registers accessible through the DRP (Dynamic Reconfiguration Port) or JTAG.

Why “differential” matters in FPGA environments

The ADC uses a differential sampling scheme specifically to reject common-mode noise from digital switching (ground bounce, shared impedance noise, etc.).

That’s why you’ll see recommendations like “route as tightly coupled differential pairs” for the analog inputs.

Timing model in one paragraph

A full conversion is driven by ADCCLK; a “classic” headline number from UG480 is:

1 MSPS max, and 26 ADCCLK cycles are required per acquisition+conversion in continuous sampling, implying ~26 MHz max ADCCLK for that top rate.

If your source impedance/filter needs more settling, you either slow ADCCLK or extend acquisition time (ACQ bits).

Output data format (common gotcha)

Conversion results are stored in 16-bit status registers, but the 12-bit sample is MSB-justified (the 12 MSBs are the meaningful ADC value).

2) Configuring XADC IP in Vivado (XADC Wizard)
Step A — Add the IP and choose an interface

In Vivado IP Catalog, add XADC Wizard. The wizard generates an HDL wrapper that configures:

• external channels
• internal sensor channels
• operating mode
• alarms

It supports these common integration styles:

• DRP (simple HDL control, no AXI interconnect needed)
• AXI4-Lite (CPU-friendly register access)
• AXI4-Stream (streaming samples into FIFOs/DMA/DSP logic)

Step B — Pick operating mode + channels

Typical choices:

• Single-channel mode: simplest control loop (poll one channel)
• Channel sequencer: scan a list of channels (e.g., Temp + VCCINT + VAUX0/1/2)
• Event-driven sampling (CONVST/CONVSTCLK timing control) when you want sampling aligned to a system event (PWM edge, etc.)

Step C — Handle external analog inputs correctly (hardware-facing settings)

Key UG480 points that influence real designs:

• External range is effectively 1 V full-scale; if your real-world signal is higher (2.5 V, 5 V, 12 V…), you must attenuate (resistor divider) so the XADC input sees ~0–1 V. UG480 even illustrates monitoring higher rails via divider/conditioning.
• Inputs are high-impedance differential and should be routed like analog (tight pair, short, clean return).
• Use an anti-alias / RC filter close to the pins; the settling time depends on your divider/filter/source impedance.

Step D — VAUX pins are “special” I/O pins

VAUX analog inputs are shared with normal digital IO balls. In Vivado:

• Just connecting VAUX ports at top-level enables them as analog (no pin LOC constraints needed for the analog function itself), but the bank still needs a compatible IOSTANDARD selected.
• Once used as analog, those pins are not available as normal digital IO.

Step E — Alarms & averaging (the “don’t make it noisy” settings)

For supply/temperature monitoring, enabling averaging reduces noise sensitivity and makes alarm thresholds less twitchy (UG480’s example notes averaging’s importance for typical monitoring/alarm use).

Step F — “INIT_40 … INIT_5F” (what the wizard is really doing)

Under the hood, the wizard sets XADC control registers by emitting INIT_xx attributes (e.g., INIT_40/41/42 for configuration, INIT_48–4F for sequencer, INIT_50–5F for alarm thresholds).

You can also write these registers later over DRP after configuration, but the wizard’s “init” approach is the fastest bring-up path.

3) Simulation of XADC (important reality check)
The core idea

Digital simulators can’t “simulate analog pins” directly. For XADC, the UNISIM/SIMPRIM model reads analog values from a text file, and that file is the only way to inject analog stimulus into the sim:

You point the primitive at the file using SIM_MONITOR_FILE.

The Analog Stimulus file format (UG480)

UG480 explains the stimulus file is:

• space/tab delimited
• timestamp in the first column
• subsequent columns are analog values for sensors and/or external channels
• column order doesn’t matter as long as timestamp is first

How Vivado/XADC Wizard helps generate stimulus (PG091)

XADC Wizard provides simulation options including:

• default stimulus file design.txt
• specifying relative/absolute path
• generating waveforms (CONSTANT/SINE/TRIANGLE/SQUARE), setting frequency and number of waves

It also supports CSV→TXT conversion via an auto-generated Tcl script (_csv_to_txt.tcl) if you want to bring in data from a spreadsheet/instrument export.

Practical sim checklist

1. Generate IP output products / example design.
2. Confirm SIM_MONITOR_FILE points to the correct design.txt (or your custom file).
3. Run behavioral simulation and observe:

• EOC/EOS (end-of-conversion / end-of-sequence)
• DRP handshake (DEN/DWE/DRDY) if using DRP reads

1. Decode sample values using “12 MSBs are the ADC code” rule.

4) Example real application: rail monitoring + external sensor on an Artix-7 board
Goal

You want an FPGA to:

• continuously monitor die temperature + VCCINT
• measure an external 12 V supply rail
• trip a fault output if voltage/temperature exceed limits

Hardware

1. Build a resistor divider + RC filter so 12 V → 0–1 V at VAUX (classic XADC approach).
2. Route VAUXP/VAUXN as a tight differential pair; place the filter close to the FPGA pins.

Vivado XADC Wizard config (typical)

• Interface: DRP (pure HDL), or AXI4-Lite if you have MicroBlaze
• Mode: channel sequencer
• Enabled channels: Temp, VCCINT, VAUX0
• Averaging: enabled for more stable alarm behavior
• Alarms: configure voltage/temp thresholds (wizard sets INIT_50–5F)

Firmware/logic behavior

• Each EOS, read the relevant status registers (remember: 12 MSBs hold the sample).
• If alarm output asserts, latch a FAULT flag and optionally shut down a DC-DC enable.

Simulation

• Generate a design.txt that ramps the VAUX channel and steps temperature; point SIM_MONITOR_FILE to it.
• Or let the wizard generate a sine/triangle stimulus for VAUX to validate your readout chain.