XADC (eXtensible Analog-to-Digital Converter) is an on-chip analog mixed-signal (AMS) block inside many AMD/Xilinx 7-series FPGAs (Artix-7/Kintex-7/Virtex-7) and Zynq-7000. It’s basically a built-in dual 12-bit ADC (up to ~1 MSPS) plus on-chip sensors (die temperature + internal supply monitoring) that you can read/control from your FPGA design.
What XADC is used for
1) System monitoring (“health sensors” for the FPGA)
- Measure FPGA die temperature
- Monitor internal power rails (useful for power integrity, thermal throttling, brownout detection, logging)
2) Reading external analog signals (real ADC channels)
- You can bring analog voltages into dedicated VAUXP/VAUXN auxiliary analog inputs (pins that can be used for analog in certain modes).
- Typical input ranges are limited (often around 0–1 V depending on mode), so you usually add external scaling/conditioning (divider, op-amp, filter) for sensors that output 3.3 V/5 V.
3) Safety & control features
- Built-in sequencer (scan multiple channels)
- Alarms/thresholds (e.g., over-temperature, under/over-voltage) for protective actions
How you access XADC data in an FPGA design
You read/configure XADC through the DRP (Dynamic Reconfiguration Port)—a register interface that can be driven by FPGA logic (or accessed via JTAG).
Converted measurements land in data/status registers you can poll or capture on events like end-of-conversion/sequence.
Practical examples
- Thermal protection
Read die temperature; if it crosses a threshold, reduce clock, throttle workload, or turn on a fan.
- Power rail supervision
Continuously monitor rails (e.g., VCCINT/VCCAUX). If undervoltage is detected, trigger a safe shutdown or error log.
- Analog sensor input
- Hook a potentiometer (through scaling to the supported input range) to a VAUX channel to create a hardware “knob” for gain/threshold tuning.
- Sample a current-sense amplifier output (scaled) to build an internal current monitor without an external ADC.
- Manufacturing test & calibration
Use XADC readings to validate board power/thermals during production test and store pass/fail data.
How people typically use it in Vivado
Most designers drop in the XADC Wizard IP (configures channels, sequencing, averaging, alarms) rather than hand-instantiating the primitive, then connect the DRP/output signals to their logic. (UG480 is the main technical reference.)

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