How to design your own FPGA board?

#fpga #fpgaboard #xc7a35t #stm32

Designing your own FPGA board = a set of clear decisions + a disciplined checklist. Here’s a practical, end-to-end guide you can follow from concept to bring-up.

1) Define the job first

Workload: soft-CPU? motor control? video? high-speed I/O?
Interfaces: how many LVDS, SPI/I²C/UART, DDR, MIPI, PCIe, Ethernet, HDMI?
Throughput & clocks: pixel rates / lane speeds / DDR data rates.
Power & thermals: max watts, airflow, enclosure.
Cost & longevity: target BOM, package availability, lifecycle.

2) Pick the FPGA family & package

Families to consider: Lattice (iCE40/ECP5/Nexus), Microchip PolarFire, Xilinx/AMD Artix-7/Kintex-7/Ultrascale, Intel Cyclone/Arria.
Package: BGA pitch/ball count drives PCB complexity. 0.8 mm BGAs route on 6–8 layers; 0.5–0.65 mm often need microvias/HDI.
Speed grade & SERDES: choose parts with the transceiver speed you need (e.g., 3.125/6.25/10+ Gb/s).

3) Pin planning & I/O banks

Bank voltages (VCCO) set I/O standards (LVCMOS 1.2–3.3 V, LVDS, SSTL, HSTL). Group signals by standard.
Dedicated pins: configuration pins, JTAG, clock-capable pins (MRCC/SRCC), VREF pins for SSTL/HSTL, transceiver refclks.
Length matching: set constraints for differential pairs (±5–10 mil typical) and buses (DDR: tighter).
SSO budget: spread high-toggle LVCMOS across banks to avoid ground bounce.

4) Configuration/boot

In-system programming: JTAG header (2×5 0.05" or 2×7 0.1").
Nonvolatile image: QSPI/BPI flash (often 3.3 V; some families also 1.8 V). Size = bitstream × 2–3 for multiboot/failsafe.
Boot mode pins/DIP: select JTAG vs. flash, normal vs. golden image.
Optional management MCU (tiny STM32/AVR/RP2040): controls boot, sensors, fans, and can update flash over USB.

5) Clocks & resets

Primary XO: low-jitter 25–100 MHz oscillator on a clock-capable pin. Keep short, guard with ground.
Additional refs: separate low-jitter refs for SERDES/PCIe/Ethernet if required.
Reset tree: open-drain POR/supervisor pulls FPGA PROG_B/CRESET and MCU /RST; add manual pushbutton.

6) Power architecture (most important)

Typical rails (names vary by vendor/series):

Core (VCCINT): 0.85–1.2 V, high current, fast transients.
Aux/PLL (VCCAUX/VDDA): 1.8 V/2.5 V, low noise.
BRAM/logic extras, Transceiver rails (e.g., 1.0 V/1.2 V core + 2.5 V/3.3 V I/O + 1.8 V PLL), Bank VCCO per I/O standard.

Design steps:

Estimate power with vendor tool (toggle rates, utilization, SERDES, DDR).
Choose regulators: synchronous bucks for core; LDOs or filtered bucks for analog/PLL.
Sequencing: many FPGAs allow any order if /POR held; if not, follow required order or use a sequencer/supervisor.
Target PDN impedance: 𝑍target=Δ𝑉/Δ𝐼. Pick bulk + MLCC network to meet it across 10 kHz–100 MHz.
Decoupling plan:

Bulk per rail (47–220 µF polymer).
Mid MLCCs (4.7–22 µF).
High-freq MLCCs (0.1 µF/0.047 µF) at every power pin group with short vias.
Keep loop area tiny; use via pairs to planes.

7) Memories & high-speed I/O

DDR3/DDR3L/DDR4/LPDDR: follow vendor layout guides; length-match (±5–25 mil by group), controlled impedance (e.g., 40/50 Ω). Keep stubs short; route fly-by with termination at the end (DDR3+). Provide VTT if SSTL.
QSPI/OSPI flash: place near configuration pins, short traces; consider dual/quad/octal for bandwidth.
Transceivers (PCIe/SGMII/DP):
- 85/100 Ω differential, AC-coupling caps where spec requires.
- Keep pair-to-pair skew tight; avoid stubs and unnecessary vias; back-drill if through-vias at high speed.
- Solid return path continuity under pairs; no splits under them.

8) Connectors & peripherals

JTAG (mandatory), USB-UART for console, LEDs (DONE/ERROR/USER), DIP switches or jumpers for boot.
Ethernet: PHY + magnetics; strap pins; ESD on connector.
Display/Camera: DVI/HDMI (use level shifting/PHY as needed), MIPI D-PHY usually needs a bridge/PHY (unless FPGA supports it).
Expansion headers: bring out multiple banks with clear VCCO labels and proper protection.

9) Schematic checklist (quick)

Correct bank VCCO per net class; VREF pins tied/decoupled per IO standard.
POR/supervisor thresholds set to rail voltages; reset widths meet datasheet.
Configuration: flash wired per vendor ref (pull-ups/downs on mode pins, CS#, D0..D3, CCLK); add golden image option.
JTAG chain order (if multiple devices) + TRST if required.
Test points on all rails, clocks, main I/Os.
ESD/EMI parts at external interfaces; series resistors (22–47 Ω) on noisy LVCMOS lines if needed.

10) PCB layout (what usually makes or breaks the board)

Layer stack: For mid-complexity, 6–8 layers:
SIG / GND / SIG / PWR / GND / SIG (6L) or add SIG/GND pairs for 8L+. Keep at least one solid GND plane contiguous.
Escape the BGA: dog-bones for 0.8 mm; microvias for ≤0.65 mm. Keep fanout consistent.
Impedance control: 50 Ω single-ended, 100 Ω differential (or per standard). Get fab stackup before routing.
Return paths: never cross plane splits with fast signals; add stitching vias near layer transitions.
PDN: place high-freq MLCCs next to balls (one via to rail plane, one to GND, or via-in-pad filled for HDI).
Clocks & refs: shortest, cleanest routes; guard with GND fences if needed.
Thermal: pour copper under regulators/FPGA; via arrays under power pads.

11) EMC/ESD & reliability

TVS arrays on USB/Ethernet/HDMI. Common-mode chokes where applicable.
Input filtering on DC jack/12 V buses; pi-filters for noisy rails going off-board.
Consider watchdog and brown-out supervisors; current-limit switches for USB power.
Creepage/clearance if higher voltages present.

12) DFM/DFT (manufacturing & test)

Fiducials, tooling holes, solder-paste apertures tuned for fine-pitch BGA.
Boundary-scan: get the BSDL, plan a JTAG test to wiggle IOs. Break out a few nets to LEDs or headers to sanity-check.
Bed-of-nails or pogo-pin pads for production programming.
Panelization notes and keepouts for the assembler.

13) Bring-up plan (step-by-step)

Visual & shorts check; power rails in isolation with current-limited bench supply.
Power sequence: verify each rail voltage & ripple; check POR timing.
Crystal/oscillator present on scope.
JTAG IDCODE read; configure with a known-good minimal bitstream.
Blink a user LED; then test UART console.
Exercise banks by IO standard; then DDR memory “march” test; then high-speed links loopback.
Log thermal rise at worst-case load; verify no throttling/reset.

14) Minimal reference BOM (starter dev-style board)

FPGA: e.g., Lattice ECP5-45 or AMD Artix-7 XC7A35T (moderate IO, no transceivers or low-end SERDES).
Config flash: 16–64 Mbit QSPI.
Mem: 64–256 MB DDR3L (x16), optional HyperRAM if simpler.
Power: 3–4 buck regulators (core, aux, 3.3 V, 1.8 V), one LDO for PLL/analog.
Clock: 50 MHz XO + optional 125 MHz for Ethernet/SGMII.
Connectivity: USB-UART bridge, JTAG header, RJ45 (if needed), PMOD/Arduino-style headers.
Misc: 4–8 user LEDs, 2 pushbuttons (reset, user), DIP for boot, ESD parts.

15) Rules of thumb (handy numbers)

Core rail ripple budget: ≤3% pp of rail voltage.
Decap density: 1 small MLCC per 2–4 balls for core/BRAM groups on 0.8 mm; more for HDI/fast parts.
DDR fly-by skew: keep DQS-to-DQ within vendor limit (often <±10–25 ps equivalent).
SERDES vias: limit to 2–4 layer transitions end-to-end; back-drill stubs above ~6 Gb/s.
Edge-rate control: add 22–33 Ω series resistors on long LVCMOS runs.

16) Common pitfalls (avoid these!)