FPGAs can get surprisingly small - from massive high-performance chips down to packages smaller than a fingernail. The physical size depends on the package type, pin count, and target application.
Physical Package Sizes
Ultra-Small FPGA Packages
Real-World Size Comparisons
- iCE40 UltraPlus WLCSP: 2.15×2.55mm (smaller than a SIM card chip)
- Lattice MachXO3 QFN: 3.5×3.5mm
- Gowin GW1N QFN: 4×4mm
- Xilinx Artix-7 CSG324: 15×15mm (larger, high-performance)
Ultra-Small FPGA Families
1. Lattice Semiconductor - The Size Leader
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iCE40 UltraPlus (WLCSP): 2.15 × 2.55 mm | ~5k LUTs
iCE40 LP/HX (QFN): 3.5 × 3.5 mm | ~1k-8k LUTs
CrossLink-NX (WLCSP): 2.5 × 2.5 mm | ~6k LUTs
MachXO3 (QFN): 3.5 × 3.5 mm | ~2k-9k LUTs
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GW1N series (QFN): 4 × 4 mm | ~1k-20k LUTs
LittleBee (QFN): 5 × 5 mm | ~1k-5k LUTs
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Max 10 (UQF): 7 × 7 mm | ~2k-50k LUTs
Cyclone 10 LP (UBGA): 8 × 8 mm | ~6k-20k LUTs
4. Xilinx (AMD)
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Spartan-7 (CSG): 8 × 8 mm | ~6k-100k LUTs
Artix-7 (CSG): 15 × 15 mm | ~15k-200k LUTs
Applications for Tiny FPGAs
Wearable Electronics
- Smart watches
- Fitness trackers
- AR/VR glasses
IoT and Embedded Systems
verilog
// Example: Tiny FPGA as I²C/SPI bridge
module i2c_spi_bridge(
input wire clk,
inout wire sda, scl, // I²C
input wire mosi, cs, sck, // SPI
output wire miso
);
// Small enough for 2×2mm package
endmodule
Mobile Devices
- Sensor aggregation
- Display interface bridging
- Power management
Medical Devices
- Hearing aids
- Portable monitors
- Implantable devices
Resource Constraints in Small FPGAs
Even the smallest FPGAs contain essential resources:
Typical iCE40 UltraPlus (2.15×2.55mm)
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Logic Cells: 5,280 LUTs
Memory: 1 Mb SPRAM + 120 Kb DPRAM
DSP: 8 16×16 multipliers
I/O: Up to 28 pins
PLL: 1-2 clock management
Design Considerations for Small FPGAs
verilog
// Efficient coding for small FPGAs
module tiny_design(
input wire clk,
input wire [7:0] data_in,
output reg [7:0] data_out
);
// Use distributed RAM instead of block RAM
(* ram_style = "distributed" *)
reg [7:0] buffer [0:15];
// Share resources when possible
always @(posedge clk) begin
if (enable) begin
data_out <= buffer[addr] + offset; // Combine operations
end
end
endmodule
Development Boards for Small FPGAs
Tiny FPGA Boards
- Lattice iCE40 UP5K Board: ~20×20mm
- TinyFPGA Boards: ~18×30mm
- iCEBreaker FPGA: ~40×40mm (with debugging)
- BlackIce MX: ~35×35mm
Comparison to Microcontrollers
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ATmega328P (Arduino): 7×7mm | 8-bit MCU
STM32F103: 7×7mm | 32-bit ARM Cortex-M
iCE40 UP5K: 2.5×2.5mm | 5k LUT FPGA
FPGA Advantage: Parallel processing, custom hardware
Technological Trends Making FPGAs Smaller
Advanced Packaging
- WLCSP: Bare die with solder balls
- Fan-Out Wafer-Level: Even smaller than chip-scale
- 3D Stacking: Multiple dies in one package
Process Technology
- 28nm FD-SOI: Better power efficiency
- 40nm LP: Low power for small devices
- FinFET: Higher density (in larger FPGAs)
Practical Limitations
I/O Count vs Size Tradeoff
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WLCSP 2.5mm: Max ~25-30 I/O pins
QFN 4mm: Max ~64 I/O pins
QFP 10mm: Max ~144 I/O pins
BGA 15mm: Max ~300+ I/O pins
Power Considerations
- Tiny FPGAs: 10-100mW typical
- Sleep modes: As low as 10-50μW
- Active power: Scales with utilization
Future Outlook
Near Future (2024-2026)
- 1×1mm packages for ultra-simple logic
- Heterogeneous integration with MCUs
- More specialized tiny FPGAs for specific interfaces
Application Growth Areas
- Edge AI: Tiny FPGAs for ML preprocessing
- Sensor Fusion: Multiple sensors → one tiny FPGA
- Protocol Conversion: USB, MIPI, Ethernet bridging
Summary
The smallest commercially available FPGAs are around 2×2mm in package size (Lattice iCE40 UltraPlus in WLCSP), containing thousands of logic elements while consuming minimal power. These tiny FPGAs enable hardware programmability in space-constrained applications where microcontrollers lack the parallel processing capabilities or interface flexibility.
The choice between a tiny FPGA vs microcontroller depends on your need for parallel processing, custom hardware acceleration, and interface flexibility versus software programmability and ecosystem maturity.
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