They Routed Power Through the Back of the Chip and 30% IR Drop Vanished
Every semiconductor chip has a front and a back. Transistors and wiring are built on the front side, and power delivery shares that same front surface with signal routing. It has been this way for over 60 years.
In 2026, Intel broke this convention. They implemented BSPDN (Backside Power Delivery Network) — branded PowerVia — in their 18A process node, shipping it in the Panther Lake processor as a mass-produced product.
The result: 30% IR drop reduction, 6% frequency uplift, and 5-10% standard cell utilization improvement (Intel's CES 2026 announced figures).
If the front side is congested, use the back. It sounds obvious in hindsight, but getting there required decades of process engineering. This article breaks down the physics behind BSPDN, the Intel vs TSMC vs Samsung race, and what it means for AI chips.
Why Power Delivery Became the Bottleneck
Front-Side Congestion
Look at a cross-section of any leading-edge chip: 10+ metal layers are stacked on top of the transistor layer.
Conventional chip cross-section (front-side only):
Surface
─────────────────────────
M12 Power rails (VDD/VSS) ← thick wires
M11 Power + signal ← shared
M10 Signal routing
...
M3 Signal routing ← thin
M2 Signal routing ← thinner
M1 Local interconnect ← thinnest
─────────────────────────
Transistor layer (FinFET/GAA)
─────────────────────────
Silicon substrate
─────────────────────────
Backside (nothing here)
The problem: power lines and signal lines share the same metal layers. Power rails demand thick wires, eating into the space available for signal routing.
Of the 12 metal layers, 3-4 (M10-M12) are consumed by power rails. The remaining 8-9 (M1-M9) carry signals, but power vias — vertical connections that punch through every layer — eat into signal space too.
It gets worse with every node shrink:
| Node | Signal Congestion | IR Drop |
|---|---|---|
| 5nm | Moderate | Manageable |
| 3nm | High | Design problem |
| 2nm | Critical | Design-limiting |
At the 2nm generation, signal routing density physically runs out. Power infrastructure consumes too much space to pack in more logic.
IR Drop: A Power Quality Problem
IR drop is the voltage loss caused by resistance in the power delivery network. The longer the path from the power pin to the transistor, the more voltage you lose.
Power delivery path (conventional):
Package → bonding pad → M12 → M11 → ... → M1 → transistor
Each metal layer connected vertically by vias
Horizontal runs add resistance too
Long path → high resistance → large voltage drop
The center of the chip suffers the most:
Pads are at the periphery → long distance to reach center
→ Center transistors operate at lower voltage than edges
→ Must raise global voltage to maintain margin
→ Increased power consumption
The Physics of BSPDN: Power From the Back
BSPDN is built on a simple idea: move the power wiring from the front to the back of the chip.
BSPDN chip cross-section:
Surface
─────────────────────────
M12 Signal routing ← power lines gone, space freed
M11 Signal routing ← all layers available for signals
M10 Signal routing
...
M1 Local interconnect
─────────────────────────
Transistor layer (GAA: gate wraps all around the channel)
─────────────────────────
nTSV (nano-TSV) ← vertical power feed from backside
─────────────────────────
Backside power grid (VDD/VSS) ← thick wires, plenty of room
─────────────────────────
Backside
How It's Built
1. Flip the wafer
Build transistors + signal wiring on the front side,
then thin the wafer and flip it over.
2. Nano-TSV (nTSV) formation
Etch tiny vias through the silicon substrate
reaching down to the transistor contact layer.
Power is delivered directly to the transistors.
3. Backside metallization
Form a VDD/VSS power grid on the backside.
Wires can be thicker than front-side (no signal contention).
IR drop is drastically reduced.
Quantified Gains (Intel 18A PowerVia)
| Metric | Conventional (front-side power) | BSPDN | Improvement |
|---|---|---|---|
| IR drop | Baseline | -30% | Better voltage stability |
| Clock frequency | Baseline | +6% | Higher speed at same power |
| Standard cell utilization | Baseline | +5-10% | Power vias removed, more room for logic |
A 6% frequency gain may look modest in isolation, but this is achieved without shrinking the process node. Normally, a 6% clock uplift is what you get from migrating to the next node. BSPDN alone delivers roughly half a node's worth of performance — for free, in architectural terms.
Intel vs TSMC vs Samsung: The BSPDN Race
Intel 18A: First Mover
Intel 18A PowerVia:
- Mass production started early 2026 (Panther Lake)
- Officially announced at CES 2026
- Combines RibbonFET (GAA) + PowerVia
- Foundry customers: Microsoft, Amazon
- Yield: 60-65% (early 2026; recent reports suggest 65-75%). Target: 70-80%
Technical details:
- nTSV connects to transistor contact layer
- Dedicated coarse-pitch power grid on backside
- Complete separation from signal routing
TSMC: Late but Ambitious
TSMC Super Power Rail (A16, H2 2026 target):
- TSMC's version of BSPDN
- Claims more advanced than Intel PowerVia
- Power connects directly to transistor source/drain
- N2 (2nm) ships without BSPDN → A16 introduces it
TSMC's strategy:
- Ship N2 first (no BSPDN, but GAA)
- Add BSPDN in A16 (improved N2)
- Offer customers a clean N2 → A16 migration path
Samsung is also planning BSPDN introduction with their SF2Z node in 2027, but specific technical details remain undisclosed.
The Competitive Landscape
| Foundry | Node | BSPDN Approach | Status | Risk |
|---|---|---|---|---|
| Intel | 18A | PowerVia (nTSV → contact layer) | In production (early 2026) | Yield improvement is key to profitability |
| TSMC | A16 | Super Power Rail (direct source/drain) | H2 2026 target | No shipping products yet. Yield unknown |
| Samsung | SF2Z | Undisclosed | 2027 target | 3nm yield issues still lingering |
On BSPDN specifically, Intel leads TSMC by roughly a year — the first time in nearly a decade that Intel has been ahead on a major process technology. It is not overall process leadership, but BSPDN is the lifeline of Intel's foundry business.
Three Reasons BSPDN Matters for AI Chips
1. Power Efficiency: Better J/token
AI chip power consumption keeps climbing. The H100 draws 700W, the B200 hits 1000W (1200W for the full-spec variant). Data center electricity costs are starting to dominate inference economics.
BSPDN impact on AI chip power:
30% IR drop reduction → smaller voltage margin → effective power savings
Example: hypothetical A100 with BSPDN
Current: 400W (~15% of which is IR drop margin)
BSPDN: 30% reduction in IR drop margin → ~18W savings
Inference cost: ~4.5% improvement
4.5% sounds small until you run the numbers at data center scale — it translates to millions of dollars annually.
2. Logic Density: Packing More Tensor Cores
With power vias removed from the front side, standard cell utilization improves 5-10%. That freed space can be filled with additional compute logic:
- Extra tensor cores ��� higher inference throughput
- Larger L2 cache → on-chip KV cache for LLM serving
- Dedicated PIM units → alleviate memory bandwidth bottleneck
3. Better Thermal Management
Moving power wiring to the backside reduces metal density on the front side. Dense metal creates localized hot spots.
Conventional: Power + signal on front → high metal density → heat traps
BSPDN: Power on backside → lower front-side metal density → better heat spreading
+ shorter cooling path from backside
AI chips have a specific problem:
Tensor cores run dense computation → localized heating
BSPDN: shorter power path → less Joule heating generated in the first place
The Cost of BSPDN: The Backside Has Walls Too
BSPDN is not free.
Additional Process Steps
Conventional process:
Front-side lithography + etch + metallization
→ Done
BSPDN process:
Front-side lithography + etch + signal metallization
→ Wafer thinning (backgrinding)
→ Wafer bonding (attach to carrier wafer)
→ nTSV formation (backside drilling)
→ Backside metallization
→ Additional lithography
→ Done
Additional steps: 5-8
Cost Implications
| Additional Step | Est. Cost Premium |
|---|---|
| Wafer thinning (backgrind + CMP) | +5% |
| Carrier wafer bonding | +3% |
| nTSV lithography + etch | +8% |
| Backside metallization | +5% |
| Backside patterning | +4% |
The total wafer cost increase is substantial, and yield loss risk compounds it. In return: +6% frequency, +5-10% cell utilization, ~4.5% power efficiency. For high-performance AI chips, the gains absorb the cost premium. For cost-sensitive mobile or IoT chips, BSPDN may be overinvestment.
When Does BSPDN Reach Consumer GPUs?
The timeline for BSPDN in consumer GPUs (GeForce, Radeon) is unclear.
NVIDIA:
Current (Blackwell): No BSPDN
Next gen Rubin (R100): TSMC N3P. No BSPDN
Rubin Ultra: TSMC N2 (2027). BSPDN adoption uncertain
Post-Rubin Ultra: A16 (with BSPDN) is a possibility
AMD:
Current (RDNA 4): No BSPDN
Next gen: Depends on TSMC N2 or A16
Consumer reality:
2026-2027: No BSPDN (N2 generation)
2028+: A16-based products may appear
Cost premium will be passed through to GPU prices
As an RTX 4060 8GB user, the tangible benefits of BSPDN probably won't arrive until the generation after next — a 2028-2029 GPU purchase, most likely. However, data center GPUs (successors to H100/B200) may adopt BSPDN as early as 2027. If you use inference APIs, you'll benefit from BSPDN indirectly.
The Backside Was Empty All Along
The essence of BSPDN is a deceptively simple insight: the backside of the chip was unused. Use it.
For 60 years, the back of a chip was a featureless plane. By relocating power infrastructure to that space:
- Front-side routing congestion is resolved
- The power delivery path gets shorter, reducing IR drop
- Frequency goes up, logic density increases
Intel leads, TSMC follows, Samsung waits in the wings. 2026 will be recorded as the first year BSPDN entered mass production in semiconductor history.
Of the three walls facing the 2nm generation — thermal, power, and scaling — BSPDN partially breaks through the power wall. The other walls will need their own innovations, but the paradigm shift of using the backside hints at where semiconductor design is headed.
There was space left after all. You just had to look at it from the other side.
References
- Intel. "Panther Lake: Intel 18A with PowerVia and RibbonFET" (CES 2026)
- fiisual. "What Is Backside Power Delivery Network (BSPDN)?" (2026) (industry analysis blog)
- TrendForce. "Intel's Clearwater Forest Unveils 18A Backside Power" (2025)
- "Backside Power Delivery: A Radical Shift in Chip Architecture" (2026)
- Lam Research. "Transistor Channel Stress in Backside Power Delivery Networks"
- TSMC. A16 Super Power Rail (H2 2026 planned)
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