DDR3 Memory Engine Architecture

Just discovered that 1GB DDR3 auxiliary pool on PS4 pro can be use on any workload.

Introducing: DDR3 Memory Engine Architecture

The Challenge:
The PS4 Pro isolates its primary 8GB high-bandwidth GDDR5 pool for graphics and system allocation. However, the secondary 1GB DDR3 BGA chip on a completely separate, undocumented bus handled via a custom PCIe Endpoint window on the Belize Southbridge co-processor. While the outbound posted write path bursts past 1 GB/s (and settles at a stable 156 MB/s), the non-posted read path hits an immutable, hardwired serialization bottleneck clamped directly at ~11 MB/s with an average 85ms round-trip latency penalty.

So, instead of accepting the read bottleneck, added custom 8-queue in my DDR3 driver directly into the Linux 6.8.12 kernel, explicitly mapping it to tap into all 8 AMD Jaguar CPU cores simultaneously.

To bypass the silicon-level read throttle and I designed a hybrid memory-tiering architecture inspired by the iconic PS3 Cell Broadband Engine's SPE Local Store layout:

LZ4 Compression Engine (zswap): Implemented an early-boot kernel caching layer to shrink memory blocks at a 4:1 ratio, effectively quadrupling the operational bandwidth over the restricted physical bus width.

Double-Buffered "DMA" Streaming Pipeline: Built an asynchronous thread allocation strategy where background threads pre-fetch contiguous 4MB memory chunks sequentially via the block layer's read-ahead tracking while the core CUs (compute units) crunch live tensor layers directly out of the shared L2 cache—completely hiding the hardware latency loop.

The Real Impact-
By treating this 1GB DDR3 pool as a cold fallback storage vault for background assets & static tensor layers, we can isolate and hand nearly 100% of the ultra-fast 8GB GDDR5 RAM pool directly to active compute tasks, transforming normal Gaming consumer hardware into optimized nodes for Edge AI model inference & distributed training.

Still need to add support of GFX8.0 on PS4 pro that's another part