Multiphase Buck Converters for High-Current Rails
Overview
Modern CPUs, GPUs, FPGAs, memory rails and high-current ASICs draw tens to hundreds of amperes at sub-1-volt core voltages. A single-phase buck at that current would need enormous FETs, a huge inductor, massive input capacitance, and a thermal design that concentrates all loss in one spot. Multiphase buck converters solve this by splitting the current across several interleaved phases. This article explains why parallel phases help, how interleaving and current sharing work, and how controllers and power stages differ.
- Why Parallel Phases A multiphase buck is several identical buck stages whose outputs tie together and drive the same load, with their switching clocks offset in time. Each phase handles a fraction of the total current. The benefits are:
- Ripple cancellation: the inductor currents ripple 180 degrees (or 360/N degrees) out of phase, so output capacitor ripple current and voltage ripple shrink dramatically.
- Thermal spreading: losses are distributed over multiple smaller FETs and inductors, avoiding a single hot spot.
- Faster transient response: each phase can slew its current quickly, and the control loop sees an effective higher bandwidth.
Smaller magnetics and capacitors: each phase uses a small inductor, and the input capacitor RMS current is reduced by interleaving.
Phase Interleaving
With N phases switching at frequency fSW, the effective input ripple frequency is N x fSW, while each phase still switches at fSW. The ripple in the summed inductor current is approximately canceled to first order at the output, so the output capacitor needs far less RMS rating. For example, in a two-phase 180-degree design, the input capacitor ripple current is about 30 percent of the single-phase value (typical, depending on duty cycle). This lets designers use smaller ceramic capacitors and shrink the input filter.Current Sharing
For the scheme to work, phases must share current evenly. Imbalance causes one phase to run hot, saturate its inductor, or hit current limit early. Modern controllers use either average-current-mode control per phase or sensed inductor DCR (or a sense resistor) to balance. Digital controllers, often connected over PMBus, also report per-phase current for telemetry. Current sharing accuracy is typically a few percent among phases (typical - refer to official datasheet).Controllers versus Integrated Power Stages
Two architectural choices dominate:Controller plus discrete FETs: the IC contains the control, PWM, and telemetry; external N-channel MOSFETs are chosen by the designer. This is flexible but requires layout care.
Controller plus smart power stage: a single power-stage module integrates the high-side and low-side FETs, the driver, and often current sensing and temperature reporting. It reduces board area and improves efficiency. The TI CSD95490Q5MC NexFET power stage used with the TPS53679 controller is an example of this pairing (per datasheet).
At the high end, controllers like the TI TPS53679 support up to six phases plus an auxiliary phase for VR13 server VCORE rails, with D-CAP+ control and PMBus telemetry (per datasheet). Reference designs around these parts deliver well over 200 A on a single core rail.Design Trade-offs
More phases cost more in ICs, gate drive, and board space; the number of phases is chosen by transient requirement and thermal limit.
Input voltage range and duty cycle limit phase count near dropout; when VIN approaches VOUT, each phase loses headroom.
Light-load behavior: at low total current, some controllers automatically drop phases to improve efficiency, a feature called phase shedding.
Output voltage accuracy under load steps is set by controller bandwidth and output capacitance; VR-type controllers are designed for fast DAC transitions as well.
Design Considerations
Sense the inductor DCR or use a sense resistor per phase; do not assume natural current sharing will hold across temperature.
Place input capacitors close to each power stage; the hot loop per phase must be small.
Route phase-switch nodes symmetrically so parasitics match; mismatched layout worsens current sharing.
Budget for the controller's current-share accuracy when sizing inductors; each inductor must handle its worst-case share plus margin.
Use the controller's phase-shedding feature for light-load efficiency, but verify ripple and transient when phases drop out.
Plan thermal vias and copper under each power stage; heat removal is distributed, but each stage still dissipates several watts.
Conclusion
Multiphase bucks are the enabling technology for high-current sub-1-volt rails. Interleaving cuts ripple, distributes heat, and speeds transient response, while modern controllers with integrated power stages make the design practical. The choice between discrete FETs and smart power stages, and between analog and digital controllers, is driven by current level, telemetry needs, and board area.
FAQ
Q: How do I choose the number of phases?
A: Start with the load current and a per-phase current target (often 20-40 A per power stage), then check transient response and thermal limits; more phases are added if ripple or transient requirements demand.
Q: Why does input ripple current decrease with interleaving?
A: The input capacitor only supplies the difference between overlapping phase currents; when phases are offset, their charging pulses partially cancel, reducing RMS current through the capacitor.
Q: What happens if current sharing is poor?
A: One phase takes more current, saturates thermally or magnetically, and can trigger protection while other phases are lightly loaded. Sense networks and symmetric layout are the fix.
Q: Can I use multiphase for lower-voltage, lower-current rails?
A: Yes, two-phase designs are common for GPU and memory rails well below 100 A; the ripple and transient benefits still apply.
For exact specifications and design guidance, refer to the official TI datasheets for TPS53679 and CSD95490Q5MC.
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