Key Takeaways
- TSMC projects the 2030 semiconductor market to reach $1.5 trillion, with AI and high-performance computing driving over half the demand.
- N2 volume production started in Q4 2025, introducing Gate-All-Around nanosheet transistors, and combined 2nm and A16 capacity will grow roughly 70% annually from 2026 to 2028.
- CoWoS packaging supply remains a bottleneck despite significant capacity growth, prompting customers to evaluate alternative integration paths. TSMC has raised its 2030 semiconductor market forecast to $1.5 trillion, with AI and high-performance computing projected to drive more than half of that demand. The revision, presented at the company’s North American Technology Symposium 2026, reflects how thoroughly AI infrastructure has displaced smartphones and PCs as the industry’s primary growth engine. First-quarter 2026 revenue rose more than 40% year-over-year, with gross margins reaching 66.2%.
The Logic Race: N2, A16 and What They Mean for AI Chips
N2 volume production began in Q4 2025, and the node matters for reasons beyond the process shrink. It is TSMC’s first implementation of Gate-All-Around (GAA) nanosheet transistors, replacing the FinFET architecture that has underpinned leading-edge chips for over a decade. GAA wraps the gate material around all four sides of the transistor channel, improving electrostatic control and reducing leakage, the practical result is better performance per watt at smaller geometries.
AMD‘s Instinct MI400 series is reportedly the first AI accelerator to use the N2 node, pairing it with 432GB of HBM4 memory for high memory bandwidth. Nvidia‘s current Blackwell architecture uses a custom TSMC 4NP process, with more advanced nodes expected in future generations. TSMC projects combined 2nm and A16 capacity will grow at roughly 70% compound annually from 2026 to 2028.
The A16 process adds Super Power Rail (SPR) backside power delivery, a meaningful architectural change for dense AI and HPC processors. Routing power through the back of the wafer frees up the front-side metal layers for signal interconnects, improving both routing density and power distribution at scale. A16 is targeted for production readiness in 2026 and volume production in 2027.
Advanced Packaging: The Bottleneck Nobody Solved
CoWoS supply is still the binding constraint. TSMC’s Chip-on-Wafer-on-Substrate technology is what makes modern AI accelerators possible, it integrates HBM stacks directly alongside logic dies on a single substrate, delivering the bandwidth and latency profile that GPU-scale AI workloads require. Without it, the chips coming off N2 and N3 lines cannot be assembled into deployable products.
Compared to 2024 high-end data centre configurations, that could represent substantial increases in compute transistors and memory bandwidth, according to TSMC’s own roadmap projections. The supply crunch has pushed at least one major customer toward alternatives.
The supply crunch has pushed at least one major customer toward alternatives. SK Hynix is reportedly evaluating Intel‘s Embedded Multi-die Interconnect Bridge (EMIB) as a 2.5D packaging path for integrating HBM with logic. EMIB eliminates the large silicon interposer used in CoWoS, which simplifies manufacturing and can improve yields. The trade-off is bandwidth and latency: EMIB’s interconnect density is lower than a full CoWoS interposer, which matters at the scale of a high-end AI accelerator. Whether SK Hynix’s evaluation leads to a production design is not yet public.
Global Footprint and the Arizona Question
TSMC’s Arizona facility began volume production of Nvidia Blackwell wafers in October 2025, according to reports. That is a real milestone for US-based advanced manufacturing. The catch is that finished wafers still need CoWoS packaging to become deployable accelerators, and that packaging capacity sits primarily in Taiwan. The Arizona complex is planned to eventually support N3, N2 and A16 process technologies, which would address more of the supply chain end-to-end, but that buildout spans years, not quarters.
Beyond N2 and A16, TSMC’s published roadmap includes A14, A13 and A12 nodes, with A13 and A12 targeted for 2029. A13 is described as offering roughly 6% area reduction compared to A14. At that point, transistor scaling, advanced packaging and chiplet architecture converge as the three levers TSMC is pulling simultaneously, each compensating for the diminishing returns of the others. For more coverage of AI chips and infrastructure, visit our AI Hardware section.
Originally published at https://autonainews.com/tsmc-raises-ai-market-forecast-ramps-2nm-and-a16-production/
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