Ask anyone outside the industry what limits chip progress and you will hear about transistor size. Ask anyone inside it, in 2026, and the answer is more likely to be a rectangle roughly 26 by 33 millimetres. That is the size of the field a lithography tool can expose in one pass, and it is the hard boundary that every large accelerator has been circling for a decade.
The wall is not new. What is new is that the industry has stopped trying to climb it and started building around it. The consequence is that the most contested part of the supply chain is no longer the fab that prints transistors. It is the packaging house that assembles several dies into one logical device, and the capacity there is measured in wafers per month rather than in nanometres.
Why the reticle limit is a yield story, not a design story
A die has to fit inside one exposure field, so its maximum area is fixed. Within that limit, designers can put whatever they want. Beyond it, they cannot print a single continuous die without stitching, which is expensive and imperfect.
The reason the limit bites is yield. Defects land on a wafer at a roughly constant density per unit area, so the probability that a die is free of fatal defects falls exponentially with its area. A die at the reticle limit is already several times less likely to be good than a die at a quarter of that area. Doubling the area again would not just be difficult to print, it would be economically absurd: you would be paying full wafer cost for a small number of good parts.
This is the arithmetic that killed the monolithic mega-die. Not physics, economics. Once a die approaches the reticle limit, the marginal cost of adding area rises faster than the marginal value of the transistors it holds, and that is the moment the industry starts splitting designs apart.
Chiplets move the problem, and create a new one
Splitting a design into several smaller dies improves yield dramatically, because each die is smaller and the defect-density penalty is lower. It also lets each function be built on the process node that suits it: logic on the leading edge, SRAM or analog on something older and cheaper.
What it does not do is make the parts disappear. The dies still have to be connected, and the connection has to carry an enormous amount of data with very little energy per bit. That is what advanced packaging provides, and it is why the interposer, the bridge, and the assembly step have become the scarce resources.
The economics shift accordingly. In a monolithic world, cost is dominated by wafer cost and yield. In a chiplet world, cost is dominated by known-good-die testing, package yield, and the assembly capacity itself. A package that combines four dies has four opportunities to lose a part, and the failure of one die wastes the other three unless testing catches it first.
Why the bottleneck moved to assembly
Packaging capacity is hard to add because it is not a single machine. It is a sequence: interposer fabrication, bumping, die placement at micron accuracy, underfill, substrate supply, and test. Each step has its own qualification cycle, and the whole line has to be qualified as a unit before a customer will accept it.
That is why the announced expansions in advanced packaging take years and why the constraint shows up as allocation rather than price. A fab can be built in two to three years; an assembly ecosystem takes longer because it depends on specialised suppliers who are themselves capacity-constrained.
The mechanism connecting this to product prices is direct. If package capacity grows more slowly than accelerator demand, the marginal accelerator is limited by packages, and its price reflects the scarcity of the whole chain rather than the cost of the silicon inside it. This is the opposite of the usual story where Moore's law pushes prices down.
The cost of a good package is also increasingly a pricing signal. When a customer buys an accelerator, an increasing share of the bill is not the logic die but the assembly around it, and that share is visible in gross margins: a product built on a mature monolithic die can be priced near its wafer cost, while a product built on four dies and a large interposer carries a floor set by packaging yield. That floor is why accelerator prices have stopped falling at the rate the process roadmap implies, and why the cheapest way to add performance is now to add dies rather than to shrink them.
Roughly half of the manufacturing cost of a leading accelerator package now sits in assembly and test rather than in the logic die, and that ratio is the clearest signal that the industry's centre of gravity has moved.
What it means for the next five years
The plausible trajectory is that the reticle limit stays where it is, the number of dies per package rises, and the interposer grows until it too hits a manufacturing limit. At that point the industry moves to something else: bridge-based connections between smaller packages on a substrate, or optical links between packages on a board.
The market consequence is a shift in where value accrues. If the differentiator is no longer who can print the smallest transistor but who can assemble the largest working package with acceptable yield, then the bargaining power moves toward the assembly houses and the substrate suppliers, and away from the designers who can be replicated.
Stated with its reasoning: advanced packaging revenue is currently in the low tens of billions annually. If die-per-package counts double again by 2030 while accelerator unit growth continues, packaging and substrate revenue lands between thirty and seventy billion dollars a year by the end of the decade, with the range set mostly by how quickly optical interconnect displaces copper at the package edge.
The companies that win the next cycle will be the ones that can guarantee package yield at scale, because that is now the scarcest input in the entire stack.
What is actually transferable
The general lesson is that constraints migrate. When one limit is solved, the system does not become unconstrained; it becomes constrained somewhere else, and the new constraint is usually in the least glamorous part of the chain.
The same pattern appears in software: when compute became cheap, the constraint moved to memory bandwidth; when bandwidth improved, it moved to interconnect; when interconnect improved, it moved to the energy cost of moving data. Each fix relocates the bottleneck rather than removing it.
For anyone planning capacity, the practical implication is to find the step in the chain with the longest qualification cycle and treat that as the real schedule. That step is rarely the one on the marketing slide, and it is almost always the one nobody wants to talk about.
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