Implementing data transfer acceleration via "multi-channel interleaving" to unlock the maximum throughput of enterprise SSDs.

Accelerating SSD data transfer

---

Sample Code

#include <stdint.h>
#include <stdbool.h>
#include <stddef.h>

/* [ESCR] Eliminate magic numbers: Always append 'U' suffix */
#define FTL_NAND_CHANNELS           (8U)    /* Number of NAND channels on the controller */
#define FTL_MAX_DMA_DESCRIPTORS     (64U)   /* Max DMA descriptors issued per transaction */
#define FTL_SECTORS_PER_PAGE        (8U)    /* Logical sectors per physical page (4KB / 512B) */

/* Hardware DMA Request Structure */
typedef struct {
    uint32_t pba;           /* Physical Block Address */
    uint16_t sector_count;  /* Number of sectors to transfer */
    uint8_t  channel_id;    /* Target hardware channel (for parallel execution) */
    uint8_t  is_write;      /* Write(1) or Read(0) */
} HW_DmaRequest_t;

/* --- Mock declarations for external HAL/FTL functions --- */
/* Translates LBA to PBA and retrieves the physical channel ID attached to it */
extern uint32_t FTL_TranslateLbaToPbaAndChannel(uint64_t lba, uint8_t* p_out_channel);
/* Submits the built DMA descriptor to the hardware submission queue */
extern bool HAL_SubmitDmaRequest(const HW_DmaRequest_t* p_request);

/**
 * @brief Dispatches a host I/O request across multiple channels for parallel DMA transfer (Interleaving).
 * 
 * @param[in] start_lba      Starting Logical Block Address
 * @param[in] total_sectors  Total number of sectors to transfer
 * @param[in] is_write       True for Write, False for Read
 * @return true: All DMA queued successfully, false: Argument error or hardware queue full
 */
bool FTL_DispatchInterleavedTransfer(uint64_t start_lba, uint32_t total_sectors, bool is_write) {
    /* [ESCR] Single Exit Principle */
    bool b_is_success = false;
    bool b_has_error = false;

    HW_DmaRequest_t dma_req;
    uint32_t sectors_processed = 0U;
    uint32_t current_chunk;
    uint8_t  target_channel;
    uint32_t target_pba;
    uint32_t dma_count = 0U;

    /* [ESCR] Defensive Programming: Reject invalid size requests */
    if ((total_sectors > 0U) && (total_sectors <= (FTL_MAX_DMA_DESCRIPTORS * FTL_SECTORS_PER_PAGE))) {

        while ((sectors_processed < total_sectors) && (b_has_error == false)) {

            /* Calculate current chunk size without crossing page boundaries */
            current_chunk = FTL_SECTORS_PER_PAGE - ((start_lba + sectors_processed) % FTL_SECTORS_PER_PAGE);
            if (current_chunk > (total_sectors - sectors_processed)) {
                current_chunk = total_sectors - sectors_processed;
            }

            /* Address translation and channel assignment (Interleaving distribution happens here) */
            target_pba = FTL_TranslateLbaToPbaAndChannel(start_lba + sectors_processed, &target_channel);

            /* Build DMA descriptor */
            dma_req.pba          = target_pba;
            dma_req.sector_count = (uint16_t)current_chunk;
            dma_req.channel_id   = target_channel;
            dma_req.is_write     = is_write ? 1U : 0U;

            /* Asynchronously submit DMA request to hardware (parallel execution starts per channel) */
            if (HAL_SubmitDmaRequest(&dma_req) == true) {
                sectors_processed += current_chunk;
                dma_count++;
            } else {
                b_has_error = true; /* e.g., Hardware queue exhaustion */
            }

            /* Infinite loop prevention: DMA submission upper bound guard */
            if (dma_count >= FTL_MAX_DMA_DESCRIPTORS) {
                b_has_error = true;
            }
        }

        /* Success is only granted if all sectors were dispatched without error */
        if ((b_has_error == false) && (sectors_processed == total_sectors)) {
            b_is_success = true;
        }
    }

    return b_is_success;
}

Test Code

#include <stdint.h>
#include <stdbool.h>
#include <stddef.h>

/* [ESCR] Eliminate magic numbers: Always append 'U' suffix */
#define FTL_NAND_CHANNELS           (8U)    /* Number of NAND channels on the controller */
#define FTL_MAX_DMA_DESCRIPTORS     (64U)   /* Max DMA descriptors issued per transaction */
#define FTL_SECTORS_PER_PAGE        (8U)    /* Logical sectors per physical page (4KB / 512B) */

/* Hardware DMA Request Structure */
typedef struct {
    uint32_t pba;           /* Physical Block Address */
    uint16_t sector_count;  /* Number of sectors to transfer */
    uint8_t  channel_id;    /* Target hardware channel (for parallel execution) */
    uint8_t  is_write;      /* Write(1) or Read(0) */
} HW_DmaRequest_t;

/* --- Mock declarations for external HAL/FTL functions --- */
/* Translates LBA to PBA and retrieves the physical channel ID attached to it */
extern uint32_t FTL_TranslateLbaToPbaAndChannel(uint64_t lba, uint8_t* p_out_channel);
/* Submits the built DMA descriptor to the hardware submission queue */
extern bool HAL_SubmitDmaRequest(const HW_DmaRequest_t* p_request);

/**
 * @brief Dispatches a host I/O request across multiple channels for parallel DMA transfer (Interleaving).
 * 
 * @param[in] start_lba      Starting Logical Block Address
 * @param[in] total_sectors  Total number of sectors to transfer
 * @param[in] is_write       True for Write, False for Read
 * @return true: All DMA queued successfully, false: Argument error or hardware queue full
 */
bool FTL_DispatchInterleavedTransfer(uint64_t start_lba, uint32_t total_sectors, bool is_write) {
    /* [ESCR] Single Exit Principle */
    bool b_is_success = false;
    bool b_has_error = false;

    HW_DmaRequest_t dma_req;
    uint32_t sectors_processed = 0U;
    uint32_t current_chunk;
    uint8_t  target_channel;
    uint32_t target_pba;
    uint32_t dma_count = 0U;

    /* [ESCR] Defensive Programming: Reject invalid size requests */
    if ((total_sectors > 0U) && (total_sectors <= (FTL_MAX_DMA_DESCRIPTORS * FTL_SECTORS_PER_PAGE))) {

        while ((sectors_processed < total_sectors) && (b_has_error == false)) {

            /* Calculate current chunk size without crossing page boundaries */
            current_chunk = FTL_SECTORS_PER_PAGE - ((start_lba + sectors_processed) % FTL_SECTORS_PER_PAGE);
            if (current_chunk > (total_sectors - sectors_processed)) {
                current_chunk = total_sectors - sectors_processed;
            }

            /* Address translation and channel assignment (Interleaving distribution happens here) */
            target_pba = FTL_TranslateLbaToPbaAndChannel(start_lba + sectors_processed, &target_channel);

            /* Build DMA descriptor */
            dma_req.pba          = target_pba;
            dma_req.sector_count = (uint16_t)current_chunk;
            dma_req.channel_id   = target_channel;
            dma_req.is_write     = is_write ? 1U : 0U;

            /* Asynchronously submit DMA request to hardware (parallel execution starts per channel) */
            if (HAL_SubmitDmaRequest(&dma_req) == true) {
                sectors_processed += current_chunk;
                dma_count++;
            } else {
                b_has_error = true; /* e.g., Hardware queue exhaustion */
            }

            /* Infinite loop prevention: DMA submission upper bound guard */
            if (dma_count >= FTL_MAX_DMA_DESCRIPTORS) {
                b_has_error = true;
            }
        }

        /* Success is only granted if all sectors were dispatched without error */
        if ((b_has_error == false) && (sectors_processed == total_sectors)) {
            b_is_success = true;
        }
    }

    return b_is_success;
}