We manufacture industrial DDR5 DRAM. One of the most common questions we get from design teams bringing up a DDR5 memory subsystem is some version of: "My board passes at 4800 but fails at 5600. What am I missing?"
Almost always, the answer is signal integrity. Here's what we look at when we review a DDR5 bring-up, and the checks we recommend before you burn a board spin.
The speed bin changes the rules
DDR5 runs at 4800, 5600, and 6400 MT/s. The CAS latency scales with the bin — CL40 at 4800, CL46 at 5600, CL52 at 6400 — but tRCD, tRP, and tRAS stay constant in nanoseconds across all three. That makes layout planning simpler than DDR4, but it doesn't make signal integrity easier. If anything, the tighter eye at 5600 and 6400 means your layout has less margin to hide.
Speed bin CL tRCD tRP tRAS
DDR5-4800 40 16 ns 16 ns 32 ns
DDR5-5600 46 16 ns 16 ns 32 ns
DDR5-6400 52 16 ns 16 ns 32 ns
Impedance control is not optional
At DDR4 data rates, a four-layer board with "good enough" impedance control often worked. At DDR5-4800 and above, the DQS and DQ pairs need controlled impedance over a solid reference plane.
The targets we use in design review:
- DQS pairs: 80Ω differential, routed as a coupled pair with consistent spacing
- DQ bits: 50Ω single-ended to ground reference
- Stubs: keep under 50 mils. A long stub on a DQS line is the #1 cause of the "passes at 4800, fails at 5600" pattern
If your PCB vendor can't hold the impedance spec, that's a bigger problem than any memory part choice.
The DFE helps, but it's not a layout fix
DDR5 has a 4-tap decision feedback equalizer on the receiver. It improves the eye by filtering post-cursor ISI, which is useful. What it doesn't do is remove the need for a clean return path.
Think of it this way: the DFE is like a good noise-cancelling headset. It makes a noisy environment tolerable, but it's not a substitute for a quiet room. If your layout has a 40-ohm impedance step on the DQS line, the DFE will mask it at 4800 and struggle at 5600.
Training: use it early, not as a crutch
DDR5 supports VrefDQ, VrefCA, and VrefCS training modes natively. The mistake we see is teams treating training as a last resort — "let's just train it in and hope it works."
Training finds the optimal VREF point for your specific board. It doesn't fix a layout problem. If your board needs aggressive training to pass, the layout has a margin issue that will show up as temperature dependence or unit-to-unit variation.
What we recommend:
- Run VrefDQ training during initial bring-up, not after you've chased a flaky read
- Log the trained VREF values. If they're at the edge of the range, your layout has a problem
- Verify the trained point is stable across the temperature range, not just at 25°C
The ball map check
Before any of the above, verify the ball map. WBGA-82 for x8, WBGA-102 for x16. The package is standard, but the ball assignment is where silent failures hide.
We've reviewed a customer design where DQS_t and DQS_c were swapped on the second bank group. The board passed every test at 4800 MT/s. At 5600 MT/s, it produced intermittent read errors that only reproduced above 60°C case temperature. Nine days to trace.
The 16Gb DDR5 part in WBGA-82 has the full ball assignment in the datasheet. The Micron DDR5 16Gb cross-reference maps it against the incumbent part so you can verify pin by pin without opening three documents.
The checklist
Before you spin a DDR5 board:
- [ ] DQS pairs routed as 80Ω differential over solid reference
- [ ] DQ bits at 50Ω single-ended
- [ ] Stubs under 50 mils
- [ ] Ball map verified pin by pin against host controller docs
- [ ] VrefDQ training run at bring-up, values logged
- [ ] Trained VREF stable across temperature range
The DDR5 signal integrity guidance for industrial controllers has the full impedance targets and routing rules we use in our design reviews.
Get the impedance right, verify the ball map, and train early. The DFE will help you, but it's not going to save a bad layout.
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