DEV Community

Cover image for Efficient 10G/25G Ethernet PCS & Link IP Cores
PlurkoTech
PlurkoTech

Posted on • Edited on

Efficient 10G/25G Ethernet PCS & Link IP Cores

PlurkoTech announces the launch of its highly configurable, ultra-low latency Ethernet MAC Link and PCS IP cores, designed to meet the rigorous demands of modern networking and data center environments. These silicon-agnostic IP cores offer high performance, compact implementation, and easy integration across both ASIC and FPGA platforms.

High-Performance Ethernet MAC Link Core
The MAC Link core utilizes a cut-through architecture to achieve ultra-low latency while maintaining a small footprint. It supports a 64-bit AXI-S Client interface on the MAC side and XGMII on the PHY side, ensuring smooth compatibility with IEEE 1588 TSUs and PCS cores.


Key Features:

  • 10G/25G full-duplex support
  • Ultra-low latency with cut-through operation
  • Jumbo frame support & flexible FCS generation
  • Deficit Idle Count for maximum throughput
  • AXI4-Lite/APB control interface options
  • Optional advanced features: stats, status vectors, programmable MTU

Standards-Compliant PCS IP Core
PlurkoTech’s PCS IP core fully complies with IEEE 802.3-2018 (Clauses 49 & 107), supporting 10GBASE-R and 25GBASE-R protocols. It features high configurability, FEC, and robust synchronization capabilities.


Highlights:

  • 64b66b encoding/decoding and scrambling
  • Test pattern generator & checker
  • MDIO management interface
  • Energy Efficient Ethernet (EEE) support
  • IEEE 1588 PTP sync (1-step, 2-step, eCPRI, transparent clock modes)
  • Compatible with various SerDes configurations

Availability
The IP cores are available for immediate licensing with full documentation, test environments, and support.


Contact Information

📧 sales@plurkotech.com
🌐 www.plurkotech.com
📍 New Delhi, India

Top comments (0)