I'm a CSE student who learned what SRAM is today. While trying to figure that out, I accidentally traced a path from U-Boot all the way down to sand. This is that path.
What is an SRAM?
SRAM (Static RAM) is a fast form of memory commonly found inside CPU caches and embedded systems. During boot, a Boot ROM may load a secondary bootloader such as SPL into SRAM before larger DRAM has been initialized.
Okay, so how is it different from Dynamic RAM?
Both are volatile memories. However, other than the size and location, SRAM is way faster and more expensive than DRAM. Why? Because SRAM is made of 6 transistors while a DRAM is made of one transistor and one capacitor, materials that are way cheaper.
Now being a CSE student, transistors were one of those vague words that I keep hearing engineers toss around but had never really looked into what they are or how they actually function.
What is a transistor?
Basically, an electrical switch. Which means based on the electric power that we provide it, we can turn the switch 'on' or 'off'. Well, while that is great, why does one SRAM require six of these electrical switches instead of like... one? They could just turn it on and off going from there.
Turns out, one bit in SRAM is represented by something called a latch. The latch is how the SRAM remembers values like 0 or 1.
The idea is that memory needs to hold a value, not just pass one through. A latch does this by having two inverters argue with each other until one wins.
A latch comprises of two 'NOT' gates, connecting two electronic nodes, A and B. Each NOT gate is connected so that its output feeds the input of the other, creating a feedback loop.
An electronic node is part of an electrical component which has the same voltage. So in the practical sense, A and B are wires.
Since both are connected via NOT gates,there are only two valid states: A=0, B=1 and A=1, B=0.
That brings us to the question: what exactly does A=0 or B=1 mean if they are literally wires?
As it turns out, A=0 or B=1 does not literally mean that the voltage is exactly 0 or 1 volts. Instead, digital circuits define ranges of voltages that are interpreted as logical 0 and logical 1. Whether a node is considered high or low depends on threshold voltages built into the circuit.
But then, wouldn't the two NOT gates need some comparison mechanism to be able to determine if they are at a voltage higher than the threshold?
For that we need to understand how these NOT gates are made.
What makes up a NOT gate?
Transistors.
There are two types of transistors that are used for one NOT gate.
PMOS and NMOS. Both of these are types of MOSFETs.
PMOS is a p-channel MOSFET, while NMOS is a n-channel MOSFET. What they mean will make sense soon enough. Now, take a look at the diagram below. That is how these two transistors comprise of one NOT gate.
When the voltage is low, the PMOS 'switches on' while NMOS remains 'off'. Which means current flows from the voltage source to the output. Thus, B is 1.
When the voltage is high, i.e. A=1, NMOS 'switches on' while PMOS remains off. The voltage from the source, which here is GND, flows to the output. Thus B becomes 0.
This architecture for creating a NOT gate is called a CMOS inverter, where CMOS stands for Complementary Metal Oxide Semiconductor.
That makes 4 transistors, 2 for each NOT gate. The other two are access transistors : they act like controlled doorways for the latch.
I keep saying when voltage is high, or low, but how does any transistor, whether it be PMOS or NMOS, sense it?
To understand this, we need to go a layer deeper and look into the terminals that make up these transistors.
The three terminals of a MOSFET
A terminal is an end point through which an electrical component connects to the rest of the circuit. A MOSFET has three of those.
- Source : terminal from which charge carriers enter the channel.
- Drain : terminal through which charge carriers leave the channel.
- Gate : what generates the electric field
Now, here's the interesting part. The gate is never in contact with the circuit. However, the input, A, is connected to both the gates of the NMOS as well as the PMOS for a particular CMOS inverter.
This gate uses the voltage to generate an electronic field that allows the movement of electrons or holes from one side to the other.
Once this starts happening, the space that was previously occupied by the transistor becomes a conductive region. This region is now called a channel.
Now, why does the gate work the way it does? Why does a higher voltage at the gate cause NMOS to open up, while a lower voltage causes PMOS to open up?
For that we need to understand how NMOS and PMOS transistors are made.
Doped Silicon
That means we take a semiconductor called Silicon and intentionally introduce impurities in it. Depending on the type of impurity introduced, it becomes either n-type or p-type.
N-type is when we add Phosphorus, which has 5 valence electrons, to Silicon which has only 4. So there is one extra electron, that is only weakly bound and can move through the material, increasing conductivity.
P-type is when we add Boron, which has only 3 valence electrons. So only three of four bonds of Silicon are formed, which leaves an absence of a electron, that we call a hole.
A silicon is doped at the correct places with the correct impurities to create an NMOS or PMOS transistor.
An NMOS consists of:
N+ Source
P-type Body
N+ Drain
Which looks like this:
Now, imagine putting a positively charged plate above this silicon.
The gate doesn't touch the silicon, it sits above an insulating oxide layer.
The electrons currently can't flow because there's a p-type body between two N+ source and drain. However, when the gate exerts positive electric field, the electrons get attracted and start gathering at the surface, i.e. above the p-type body.
We started with N+ Source --- P Body --- N+ Drain
Now we have created N+ Source --- N-type channel --- N+ Drain.
That is N-N-N all the way across. Now the electrons have a path.
This layer is called the inversion layer since we successfully turned a p-type body into an n-type channel.
This is also why MOSFETs are Metal Oxide Semiconductor Field Effect Transistors.
Similarly, for a PMOS, this is how the Silicon is doped.
So, coming back to our original question.
How does a NOT gate compare voltages between two wires?
It doesn't.
Each CMOS inverter only observes the voltage at its own input node. If the input is high, the NMOS transistor turns on while the PMOS turns off, pulling the output toward ground. If the input is low, the PMOS turns on while the NMOS turns off, pulling the output toward the supply voltage.
How does it determine this 'high' or 'low' though?
For an NMOS transistor, a conducting channel forms only when the voltage applied to the gate exceeds a certain value known as the threshold voltage (Vth). Below this threshold, the electric field is too weak to attract enough electrons to create a channel, and the transistor remains effectively off. Above it, a conductive path forms between the source and drain, allowing current to flow.
Digital logic is built on top of this analog behavior. Engineers define ranges of voltages that are guaranteed to be interpreted as logical 0 and logical 1. For example, in a system with a 1 V supply, voltages near 0 V may be treated as a logical 0, while voltages near 1 V are treated as a logical 1.
Values in between form a transition region where the circuit's behavior is less certain. The role of a CMOS inverter is to push voltages away from this ambiguous region and toward one of the stable extremes. In this sense, digital computation emerges from analog physics: the silicon only ever sees electric fields and voltages, while the familiar 0s and 1s arise from carefully chosen thresholds and voltage ranges.
Before we move on, there's one more thing worth sitting with: what happens when the latch can't decide?
For example, instead of one node being near 1 V and the other near 0 V, what if both A and B were sitting at roughly 0.5 V?
This turns out to be a real phenomenon called metastability.
In this situation, neither inverter sees a clearly high or clearly low input. Both are hovering around the threshold region where the transistors are only partially on. As a result, the feedback loop has not yet "made up its mind" about which stable state it should settle into.
However, this balanced state is extremely fragile. Even the tiniest disturbance, like a bit of electrical noise, a temperature fluctuation, or a few stray electrons moving around, will make one node slightly higher than the other. Once that happens, the cross-coupled inverters amplify the difference.
If A becomes even a little higher than B, one inverter starts pushing B lower, which causes the other inverter to push A higher, and the gap rapidly grows until the cell settles into either (A = 1, B = 0) or (A = 0, B = 1).
Metastability is therefore best thought of as a temporary state where the circuit has not yet decided which of its two stable states to occupy.
This is the knife-edge that a memory cell balances on. And it's made of Silicon.
It makes you wonder how disastrous it would be if we were to ever run out of Silicon.
Fortunately for us, Silicon is the second most abundant element on Earth, since it is literally found in sand.
This sand is doped, using which we get transistors, which we use to create NOT gates, which is used to create latches, and six transistors and two wires represent one bit of SRAM.
A bunch of these bits together represent our executable machine code.
Before the linker ran, it was relocatable machine code.
Before the assembler ran, it was assembly.
Before the compiler ran, it was the code you actually typed.
Sand, all the way up.
It is difficult not to be impressed by the fact that modern computing ultimately depends on engineers taking purified sand, introducing carefully chosen impurities into regions measured in nanometers, and somehow arranging the result into a machine capable of running an operating system.
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