Bottom line: India's IT Minister Ashwini Vaishnaw says the country will develop 7nm to 3nm chip technology within the next 8 years, backed by Semicon 2.0, a newly approved ₹1,27,500 crore program. This is a technology roadmap, not a production announcement: India's only running fab, SCL Mohali, still fabricates at ~180nm, and its first major commercial fab (Tata–PSMC, Dholera) is under construction for mature nodes. The plan is credible on design, talent, and packaging — and genuinely hard on leading-edge manufacturing.
TL;DR — Last verified: 2026-09-02
- India targets 7nm–3nm chip technology in 8 years (India Today, 2026-08-27).
- Current claim is 40nm technology (design know-how), not 40nm production. No Indian fab commercially ships 40nm today.
- SCL Mohali runs a ~180nm, 8-inch line (SCL).
- Semicon 2.0 outlay: ₹1,27,500 crore; covers design, equipment, materials, packaging, R&D, talent (India Semiconductor Mission).
- ~70,000 students trained on chip-design tools across 332 universities; first new fab commissioning targeted for 2028.
What exactly did India announce?
Vaishnaw's statement, published in late August 2026, commits India to developing advanced 7nm–3nm chip technology within 8 years and states that the country "now has 40nm technology" (India Today). The announcement sits inside Semicon 2.0, the second phase of the India Semiconductor Mission, which the Union Cabinet approved with a fiscal outlay of ₹1,27,500 crore (India Semiconductor Mission).
The critical distinction — easy to miss in headlines — is between having a technology and manufacturing it at scale. India's 40nm claim refers to design capability and process know-how acquired through partnerships and R&D, not a commercial fab outputting 40nm wafers.
Does India actually make 40nm chips today?
No. India's only operational fab, the government-owned Semi-Conductor Laboratory (SCL) in Mohali, runs an 8-inch wafer line at roughly 180nm (SCL) — a workhorse for strategic and space-grade chips, but about fifteen technology generations behind the leading edge. The India Semiconductor Mission itself describes India's current production-relevant node range as 28nm–110nm, and that range is prospective for the new fabs, not what SCL ships today.
The country's first major commercial fab — Tata Electronics with Taiwan's PSMC in Dholera, Gujarat, at roughly ₹91,000 crore — is still under construction and is built around mature process nodes (India Today; Tata Group). Semicon 2.0 lists the first new fab commissioning for 2028 (India Semiconductor Mission).
What is Semicon 2.0, and why does it go beyond fabs?
Semicon 2.0 is an ecosystem program, not a fab subsidy. Its six pillars, per the India Semiconductor Mission:
| Pillar | What it funds | Headline number |
|---|---|---|
| Design | Chip IP/SoCs for compute, memory, power, networking, RF, sensors; risk capital for startups/MSMEs | DLI scheme ₹1,000 crore |
| Machines & materials | Domestic semiconductor equipment, chemicals, gases, materials R&D | supply-chain integration |
| Fabs | New silicon, compound, and display fabs | 40% of capex (CMOS silicon), 35% others |
| ATMP/OSAT packaging | Advanced packaging hub ambitions | 35% of capex (advanced), 25% other |
| R&D | Moving from 28–110nm toward advanced nodes | with domestic and global research centres |
| Talent | Chip-design training at universities | 332 universities, ~70,000 students trained |
The design pipeline is already moving: under the Design Linked Incentive (DLI) scheme, 23 chip-design projects have been sanctioned (₹803.08 crore in project outlay including EDA tools), with 72 startups and 278 academic institutions given access to commercial EDA software (PIB, July 2025). This pairs with the broader India–Japan deep-tech corridor, where Japanese process and materials partnerships are one of the realistic paths for India to climb nodes faster.
Why does the 3nm target matter — and why is it so hard?
Advanced nodes concentrate in applications where performance-per-watt is decisive: AI accelerators, flagship smartphones, advanced vehicles, telecom infrastructure, and defense electronics. India's sovereign AI ambitions — from the India Semiconductor Mission's governance layer to private AI data-centre buildouts — all ultimately run on silicon the country does not yet make.
The reason "8 years to 3nm" is a hard promise, not a marketing one:
- Manufacturing experience compounds slowly. TSMC, Samsung, and Intel took decades of process-learning cycles to master each node. You can buy design know-how; you cannot buy a production team's accumulated yield knowledge.
- Leading-edge fabs are the most expensive factories on Earth. A single advanced fab routinely runs into the tens of billions of dollars — Semicon 2.0's entire ₹1.27 lakh crore (~$15 billion) budget (India Semiconductor Mission) is meant to seed a whole ecosystem, not one leading-edge line.
- The input stack is missing. EUV lithography tools, ultra-pure chemicals and gases, and specialty materials all need domestic suppliers — which is precisely what Semicon 2.0's machines-and-materials pillar is trying to build.
- Ecosystem precedes node. Realistically, the sequence is: mature-node fab running at volume (Dholera) → advanced packaging → 28nm-class production → faster node progress with partners. India is doing these in the right order, which is encouraging even if the 8-year frame is optimistic.
India's electronics sector has already shown what a staged build-up looks like: the mobile-phone manufacturing push went from assembly to increasingly domestic value-add over a decade. Semiconductors are the same playbook at much higher difficulty. Even the space sector shows the pattern — the shift we covered in ISRO's exit from commercial launches only worked after the private supply chain matured.
What this means for you
- If you build AI products in India: don't plan around Indian-made advanced silicon arriving before ~2034. Plan around India-made mature nodes (power, sensors, automotive, IoT) becoming available much sooner — Dholera's first output is expected within this decade.
- If you're an engineer or student: chip design is the short-term opportunity. With 332 universities on EDA tools and ~70,000 students already trained, the talent pipeline is real, and DLI backing means Indian design startups genuinely get to tape-out.
- If you're an investor: the highest-confidence Semicon 2.0 bets are in packaging, materials, and design services — packaging incentives alone run 25–35% of capex (India Semiconductor Mission) — and demand is already global. Leading-edge fab equity is a much longer, riskier arc.
FAQ
Q: Is India really making 3nm chips by 2034?
A: The government has targeted developing 7nm–3nm chip technology within 8 years — a roadmap commitment, not a production guarantee. India's first commercial fab (Dholera) hasn't opened yet and will start with mature nodes, so treat 3nm as an aspiration to build toward, not a date to plan around.
Q: Does India have 40nm semiconductor capability?
A: It has 40nm design technology — process know-how gained through partnerships and research. It does not commercially manufacture chips at 40nm; the running SCL Mohali fab operates around 180nm.
Q: What is Semicon 2.0?
A: The second phase of the India Semiconductor Mission, approved with a ₹1,27,500 crore outlay. It funds chip design, manufacturing equipment and materials, new fabs, advanced packaging, R&D, and talent development — treating the chip supply chain as one ecosystem rather than subsidizing fabs alone.
Q: When will India's Dholera fab start making chips?
A: The Tata Electronics–PSMC fab in Dholera (about ₹91,000 crore) is under construction and focused on mature process nodes. Under Semicon 2.0, the first new fab is scheduled for commissioning in 2028.
Q: How many startups are in India's chip-design program?
A: Per the government's July 2025 statement, 72 startups have DLI access to commercial EDA tools and 23 chip-design projects have been sanctioned for financial support, with a total approved project outlay of ₹803.08 crore.
Q: Why do advanced nodes (7nm, 3nm) matter for AI?
A: Smaller nodes pack more transistors per chip with better power efficiency — the decisive factor in AI accelerators, where compute-per-watt defines both capability and data-center operating cost. Advanced vehicles, phones, and defense systems depend on them for the same reason.
Sources
- India to develop 7nm to 3nm chip technology within 8 years: IT minister Ashwini Vaishnaw — India Today (2026-08-27)
- Semicon 2.0 — India Semiconductor Mission (official)
- 23 Chip-Design Projects Sanctioned under the Design Linked Incentive Scheme — PIB, Ministry of Electronics & IT (2025-07-30)
- Tata Group to Build the Nation's First Fab in Dholera — Tata Group
- CMOS Fabrication Facility — Semi-Conductor Laboratory, Mohali
Updates
- 2026-09-02 — Initial publication. Plans, outlays, and fab timelines are volatile facts; this page is re-verified on schedule. Spot an error? See how we work at /how-we-work.
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