Introduction: Life Inside the DV Lab
As a verification engineer working on RISC-V processor designs, I have come to accept one thing: no two projects are ever the same. With new extensions, evolving specs, growing pressure for faster cycles, and a continuous flow of tool innovations, it constantly balances rigour and speed.
Following Synopsys’ technical presentation on RISC-V verification at Verification Futures 2025, I wanted to share what this workflow looks like and how Synopsys tools have helped me and my team at Alpinum Consulting navigate complexity, stay organised, and catch critical bugs earlier.
Figure 1: RISC-V processor verification flow from feature scoping to full toolchain management.
From Specification to Silicon: The Daily Workflow
Every RISC-V project starts with a maze of spec updates, architecture extensions, and integration requirements. I always begin by interpreting the specifications, extracting features, and identifying those that require coverage and compliance.
Once I’ve scoped the features, it’s time to develop the test bench, setting up a reusable infrastructure that can flexibly verify multiple scenarios. The differing privilege levels, ISA subsets, extensions, and various hardware configurations make this stage vital. Time invested in preparation at this stage pays off later.
I deploy SystemVerilog Assertions (SVA) and custom checks to catch bugs early. These checks and assertions are woven into the test benches to flag issues like ordering violations or privilege misbehaviours.
Next comes coverage modelling. Functional coverage is essential, especially for privilege transitions, interrupt behaviour, and multicore synchronisation. Without complete coverage visibility, we might miss corner cases.
Debugging is a constant task: tracing assertion failures, cycle-by-cycle misalignments, and race conditions. Then comes reporting, where we summarise coverage status, failure rates, and open issues across our verification dashboard.
We also rely on formal verification using VC Formal in parallel with simulation. Formal tools help with corner cases missed in simulation, mathematically proving unreachability, thus saving time on further fruitless simulations.
Managing this flow end-to-end requires juggling simulation engines, formal tools, regression environments, and version control. Synopsys tools bring immense value.
Figure 2: RISC-V use cases are enabled by fast, configurable processor models, from compliance testing and debugging to virtual prototyping and software development.
How Synopsys Helps Me Get the Job Done
I use Verdi® Verification Manager daily. It simplifies my regressions and debug sessions by allowing me to dive into waveform views, cross-probe signals, and view assertion triggers in context. It connects the DUT activity with assertion failures and regression results.
Accurate co-simulation between the DUT and the reference model is essential. Whether validating user-defined instructions or multicore consistency, model lockstep integration.helps ensure instruction-by-instruction accuracy throughout the pipeline.
Figure 3: Lockstep co-simulation methodology compares RTL and reference model states after each instruction retires, enabling fast and accurate bug detection.
Figure 4: Modular architecture of the ImperasFPM Synopsys RISC-V processor models, showing core components, debug logic, configuration layers, and verification interfaces.
Another key asset is ImperasFPM, the highly configurable RISC-V reference model. It is both ISA-compliant and adaptable. I can modify it for custom instructions or privileged extensions and validate it against our implementation in real-time.
Figure 5: Full verification stack using ImperasDV — integrating the ImperasFPM reference model with RVVI tracer, coverage, and debug for simulation and emulation.
We use emulation to run OS-level tests or a firmware stack. Synopsys tools can run full software-on-hardware scenarios to catch system-level bugs that don’t appear in unit tests.
Real-World Complexity and How We Handle It
We don’t just verify cores — we verify use cases. In the last project alone, we had to deal with:
- Multicore processor interactions: ensuring coherency across L1 and shared memory spaces
- Security extensions: verifying ring transitions, secure boot flows, and access control
- ISA variants: testing optional extensions with targeted microarchitectural coverage
- Custom instructions: how to add custom instructions to the reference model and functional coverage, and generate tests to verify those instructions
- Privilege mode transitions: making sure exceptions and interrupts respect the configured privilege levels
- Software emulation: testing OS bring-up and bare-metal routines with RTL-level fidelity
Synopsys tools support all these cases with scalability and visibility. I can switch between simulation, formal, and emulation as the project demands.
Using RISC-V AIP to Catch More Bugs, Earlier
One component I’ve grown to depend on is the RISC-V AIP. It includes a set of reusable SVA assertions and synthesisable RTL logic that integrates directly with our DUT.
During a recent integration phase, AIP identified an illegal access condition where a background task unintentionally escalated privileges during an interrupt return. The issue would have escaped notice in a basic simulation, but the AIP assertion caught it immediately.
This saved us an entire debugging cycle and avoided a downstream software bug that would have taken days to trace.
Verifying custom RISC-V ISA extensions
One advantage of the RISC-V ISA is the ability to add custom instructions. But this capability comes with a duty to verify the extension and to ensure that adding it does not break existing functionality. Synopsys offers a workflow for this..
Figure 6: Workflow for exploring custom RISC-V ISA extensions — enabling domain-specific enhancements while maintaining verification integrity
Conclusion: From Stress to Confidence with the Right Tools
Working in RISC-V DV isn’t easy. Between shifting specifications, design complexity, and time pressure, engineers need more than just scripts; they need a comprehensive verification ecosystem.
The Synopsys tool ecosystem works seamlessly. Whether I’m formalising safety conditions, comparing model vs. DUT results, or reviewing multicore regressions, I spend less time chasing setup issues, debugging, and reporting, leaving me with more time verifying what matters.
Figure 7: RISC-V verification flow with Synopsys tools applied at each stage.
Whether you attended or missed Synopsys’ session at Verification Futures at Reading University on 1st July 2025, I recommend the online recording on the Verification Futures conference website. If your workflow looks anything like mine, you’ll come away with practical ideas to improve coverage, speed up debugging, and boost confidence in your next RISC-V design.
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