How is an FPGA LUT made?

Inside the chip, an FPGA LUT is basically “a tiny RAM + a multiplexer” built from transistors.

Let’s walk through what that really means.

1. Conceptual view: LUT = stored truth table

An N-input LUT can implement any logic function of N inputs.

• It has 2ᴺ configuration bits that store the output for every possible input combination.
• When you apply an input vector (e.g. A,B,C,D), the LUT:

1. Interprets [A,B,C,D] as an address
2. Selects the corresponding stored bit
3. Drives that bit out as the LUT output

So a 4-input LUT has:

• Inputs: I0, I1, I2, I3
• 2⁴ = 16 stored bits (truth table entries)
• 1 output: O

2. Physical building blocks

Inside the FPGA fabric, those pieces are built from standard CMOS circuits:

2.1 Configuration memory (the “table”)

For mainstream SRAM FPGAs (Xilinx, Intel/Altera, Lattice, etc.):

• Each truth-table bit is stored in a small SRAM cell:

Typically a 6-transistor (6T) cell (two cross-coupled inverters + two access transistors).

• For an N-input LUT you get 2ᴺ SRAM cells:

  • 4-input LUT → 16 cells
  • 6-input LUT → 64 cells

On power-up, a configuration bitstream is loaded into all these SRAM cells via the FPGA’s configuration network. After that, the LUT’s “function” is fixed until you reconfigure it.

In flash- or antifuse-based FPGAs, those bits aren’t SRAM but flash cells or antifuses.
The idea is the same: a programmable memory bit that feeds into a selection network.

2.2 Multiplexer tree (the “selector”)

To pick one of those 2ᴺ bits based on the inputs, the LUT uses a multiplexer tree.

Take a 4-input LUT as an example (16 bits, I0–I3):

1. The 16 SRAM bits feed into a first stage of 2:1 MUXes controlled by I0

16 bits → 8 outputs

1. Next stage controlled by I1

8 → 4 outputs

1. Next stage controlled by I2

4 → 2 outputs

1. Final stage controlled by I3

2 → 1 output

So you get a 4-level MUX tree: each input chooses between pairs, until one single bit remains at the output.

Physically, each 2:1 MUX is just a small transistor network:

• Implemented with transmission gates or standard CMOS logic (a few MOSFETs).
• The address bits (I0–I3) and their complements control which transistor path is on.

For a 6-input LUT (common in modern FPGAs), it’s the same idea, just a deeper / wider multiplexer structure: 64 stored bits and a MUX tree controlled by 6 input lines.

3. Optional extras around the LUT

A LUT rarely stands alone. In a logic element / slice / ALM you typically get:

1. LUT output register

• A flip-flop right after the LUT
• You can choose registered or combinational output via a small multiplexer.
• This is crucial for synchronous design and timing closure.

2. Carry chain logic

• Special fast path that bypasses the LUT MUX tree for adders / counters / comparators.
• The LUT still provides sum/logic bits, but carry propagation uses dedicated hardware to be much faster than going through normal routing and LUT logic.

3. LUT as distributed RAM or shift register

• Because it’s structurally “tiny RAM + MUX”, you can reconfigure some LUTs to behave as:
  • Small distributed RAM (e.g. 32×1, 64×1)
  • Shift-register LUTs (SRL)
• In this mode, some of the configuration bits become dynamic storage elements rather than fixed configuration.

4. How LUTs are organized in the FPGA fabric

Chips don’t sprinkle LUTs randomly; they are grouped into logic blocks:

• Xilinx: Slices / Configurable Logic Blocks (CLBs) with multiple LUTs + FFs + carry logic.
• Intel: Adaptive Logic Modules (ALMs) with fracturable LUTs, FFs, adders.

Inside a block:

Fracturable LUTs:
A 6-input LUT might be usable as:

• One 6-input function, or
• Two 5-input functions, or
• Smaller combinations, by sharing some internal SRAM cells + MUXes.

Local routing & control:
There are small local multiplexers to choose which signals feed each LUT input and where the outputs go (to FFs, carry, general routing, etc.).

But at the lowest level, every one of those “logical functions” is still just:
stored bits + a MUX tree selecting one bit based on the inputs.

5. Summary in one sentence

An FPGA LUT is built from:

• 2ᴺ configuration memory cells (usually SRAM / flash / antifuse),
  feeding into

• a tree of CMOS multiplexers,
  controlled by the LUT’s N input signals,
  often followed by an optional flip-flop and carry logic inside a logic block.