Every leading-edge fab that plans to ship a 2nm-class node in the next three years is having the same argument behind closed doors. The question is not whether High-NA EUV works. It works, it is installed, and it exposes features that low-NA systems can only reach with multiple passes. The question is whether the fourth and fifth patterning pass costs more than the tool does, and the honest answer is that almost nobody outside the fab can compute it.
This piece is an attempt to lay out the trade in the open, using published tool specifications, publicly discussed overlay budgets, and the arithmetic that any process engineer would recognise. The conclusion is uncomfortable for both camps.
Part One: What High-NA actually changes
A 0.33 numerical-aperture EUV scanner prints a resolution around 13nm half-pitch. A 0.55 NA system prints around 8nm. That single number, resolution, is what the entire argument is about, because a smaller half-pitch means fewer passes to define a given feature.
The price of that improvement is mechanical. High-NA optics use anamorphic magnification: 4x in one axis and 8x in the other. The consequence is a exposure field of 26 by 16.5 millimetres instead of 26 by 33. Half the field means two exposures for any die larger than a mobile SoC, and two exposures means stitching, and stitching means an overlay budget that eats directly into yield.
There is a second cost that gets less attention. High-NA tools are heavier, consume more power, and require a thicker resist stack because the usable depth of focus shrinks. A thinner process window is not a purchasing problem; it is a daily operational tax paid in rework.
Part Two: The arithmetic of the fourth pass
Multi-patterning is a way of buying resolution with time. Instead of printing one layer in one pass, you print it in two, three, or four passes with spacers or cuts between them. Each pass adds a deposition, an etch, a clean, and a metrology step. On a 7nm layer, quadruple patterning was already the norm. On a 2nm layer without High-NA, the industry expects six passes for the tightest metal layers.
The cost model is simple enough to write on a whiteboard:
- Cost per layer = (passes x scanner hours per pass x cost per scanner hour) + (passes x process steps x cost per step) + yield loss from overlay error accumulation.
- Yield loss is not linear in the number of passes. Overlay errors accumulate as the square root of the number of independent alignment steps, but the killer is the tail: a single misaligned critical layer destroys the die, and the probability of at least one such event grows roughly with the pass count.
That last term is where the argument actually lives. A fab running four passes at 92% per-pass overlay compliance is not running at 92% yield; it is running at 0.92 to the fourth power, or about 72%, before any other defect mechanism is counted. Getting from 92% to 97% per pass moves that number to 89%. The difference between a good process engineer and a great one is worth seventeen points of yield, which is more money than the tool discount.
Part Three: Where the tool premium is recovered
High-NA scanners are quoted in the range of 350 to 400 million dollars, against roughly 180 to 220 million for a current low-NA system. If you only compare capital cost per wafer per hour, High-NA loses badly. Throughput on the first generation is lower, around 185 wafers per hour against 220 for a mature low-NA tool, and the uptime ramp on a new platform is always worse in the first two years.
The comparison only flips when you count the steps that disappear. A layer that needs four passes on low-NA needs one on High-NA. Four passes at 220 wph with three interleaved process loops is not four times the scanner time; it is four times the scanner time plus twelve extra process steps plus the queue time between them. In a fab where a single wafer visits the litho area forty times, removing twenty of those visits is a cycle-time improvement that shows up as working capital, not as a line item.
This is the part that financial models usually miss. A 300mm wafer starts costing money the day it enters the line and does not become revenue until it ships. Cutting the number of passes cuts the days-in-line, and days-in-line is inventory. At a 20,000 wafer-per-month ramp, one week of cycle time is roughly five thousand wafers of work in progress. Nobody capitalises that on a tool purchase order, but it is real money.
Part Four: The stitching problem is a design problem
The half-field limitation is often described as a lithography issue. It is really a design issue that lithography forces onto designers. A die larger than 26 by 16.5 millimetres must be split, and the split must land somewhere the circuit can tolerate a seam. That means the physical design team has to reserve a stitching corridor, route around it, and accept a small area penalty in exactly the region where area is most expensive.
For a mobile SoC at 100 square millimetres, this is manageable. For a reticle-limited AI accelerator at 800 square millimetres, it is a redesign. This is why the first High-NA adopters are phone chips and CPU tiles, not the giant accelerators that dominate the news. The accelerator vendors will get there, but they will get there through chiplet decomposition first, which is a different strategy with its own yield arithmetic.
Part Five: What this means for the rest of us
The lithography argument has a downstream consequence that reaches well beyond fabs. If the cost per transistor stops falling, the entire industry's assumption of deflation breaks. Software gets more expensive to run because the hardware it runs on stops getting cheaper per unit of work. That is already visible in cloud pricing: the per-hour price of a GPU instance has not fallen the way CPU instances did, because the underlying economics changed.
The social version of this is simpler. Every service that assumed compute would get cheaper, from real-time translation to on-device assistants to cheap inference for small businesses, is now betting on a cost curve that depends on whether a 400-million-dollar scanner can replace four 200-million-dollar scanners and still yield. That is not a supply chain detail. It is the price of the next decade of software.
A market sizing sanity check
Leading-edge logic capex is running at roughly 100 to 130 billion dollars a year across the three remaining advanced manufacturers, and lithography is historically 20 to 25% of that. If High-NA takes half of the litho budget by 2029, the tool market alone is a 12 to 16 billion dollar annual business, before masks, resist, metrology and the service contracts that follow. The interesting number is not the tool revenue; it is the yield consultancy and metrology revenue that grows with every additional pass that gets removed or added.
The comparison that matters
Low-NA with aggressive multi-patterning optimises for capital efficiency and process maturity. High-NA optimises for cycle time, overlay headroom, and design simplicity. A fab that is capacity-constrained and selling everything it makes should prefer the option that removes steps. A fab that is yield-constrained and still learning its node should prefer the option it already knows how to run.
The mistake is treating this as a technology race. It is a queueing problem wearing a lab coat. The winning manufacturer is the one that knows which of its constraints is binding this quarter, and buys the tool that relaxes that constraint, not the tool with the better specification sheet.
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