RTLRoast
Peer code review for Verilog and SystemVerilog.
A friendly code-review platform for VLSI students writing Verilog and SystemVerilog. Get feedback on your RTL from peers and a built-in lint pass.
Features
- Syntax-aware diff
- Built-in lint pass
- Mentor & peer review
- Rubric scoring
- Threaded design comments
Try it: https://rtlroast.vercel.app
Built by NicheFactory
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