I have started working on a new language similar to verilog ( for defining logic circuits) but more simpler. I have posted it on the dev, but after working on it for sometime I have came across lot of difficulties. And understood the mistakes in the way I have defined it. Fortunately I have found the solutions for them . And I would mention them in the coming post.
Here previous post:
I have started working on a new language similar to verilog ( for defining logic circuits) but more simpler. I have posted it on the dev, but after working on it for sometime I have came across lot of difficulties. And understood the mistakes in the way I have defined it. Fortunately I have found the solutions for them . And I would mention them in the coming post.
Here previous post:
Creating a new language for logic circuits
SachinDas246 ・ Nov 11 ・ 2 min read