Steven Alex Yeung Posted on Feb 26, 2021 Is there a way to implement 6x64 decoder in verilog WITHOUT 2 by 4 and 3 by 8? #verilog https://stackoverflow.com/q/66388286/14432462 Top comments (0) Subscribe Personal Trusted User Create template Templates let you quickly answer FAQs or store snippets for re-use. Submit Preview Dismiss Code of Conduct • Report abuse Are you sure you want to hide this comment? It will become hidden in your post, but will still be visible via the comment's permalink. Hide child comments as well Confirm For further actions, you may consider blocking this person and/or reporting abuse
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