From the Space Race to the AI Chip Race: Inside the US and China's Battle for Computing Power

A technical analysis of semiconductor manufacturing, EUV lithography, HBM, advanced packaging, accelerator architectures, interconnect technologies, software ecosystems, and the economics of large-scale AI infrastructure.

Updated: October 2026

Introduction: The Next Technological Race Is Almost Invisible

During the Space Race, technological progress was relatively easy to recognize.

The Soviet Union launched Sputnik in 1957 and sent Yuri Gagarin into orbit in 1961. The United States landed astronauts on the Moon in 1969.

Each achievement provided a visible demonstration of scientific and engineering capability.

Today's competition for leadership in artificial intelligence infrastructure is less visible.

There are no rockets to watch.

Instead, progress is measured through transistor density, semiconductor yields, memory bandwidth, advanced packaging capacity, optical interconnects, and the number of accelerators that can operate together efficiently.

But one similarity remains.

The competition is pushing entire technology ecosystems toward faster innovation and massive industrial investment.

The United States and its international technology partners lead in several critical components of advanced computing infrastructure.

China is investing in alternative manufacturing capabilities, domestic AI accelerators, memory technology, and large-scale system architectures.

The central question is no longer simply who can build the fastest chip.

It is which ecosystem can design, manufacture, package, connect, and operate enough computing hardware to support the next generation of AI models.

To understand this competition, we need to examine the entire infrastructure chain.

1. Semiconductor Manufacturing: The Foundation of AI Computing

Every modern AI accelerator begins with semiconductor manufacturing.

GPU and AI accelerator designers create increasingly complex architectures, but those designs must ultimately be fabricated using advanced industrial processes.

This is one of the areas where access to technology differs most significantly.

1.1. TSMC and the leading-edge manufacturing ecosystem

Taiwan Semiconductor Manufacturing Company, or TSMC, produces advanced semiconductors for customers including NVIDIA, AMD, and other leading chip designers.

TSMC's 2 nm process entered high-volume manufacturing in the fourth quarter of 2025.

During the same quarter:

• 3 nm accounted for 28% of wafer revenue.
• 5 nm accounted for 35%.
• 7 nm accounted for 14%.

In July 2026, TSMC increased its planned annual capital expenditure to $60 billion to $64 billion.

A significant portion of that investment supports advanced manufacturing technologies, while other spending is directed toward specialty processes, packaging, testing, and related operations.

These numbers illustrate the fundamental economics of advanced semiconductors.

Leading-edge manufacturing requires continuous investment in equipment, facilities, process development, and production capacity.

TSMC is headquartered in Taiwan and operates an expanding international manufacturing network, including facilities in Arizona.

However, diversification does not immediately eliminate the concentration of the most advanced semiconductor production in Taiwan.

1.2. SMIC and China's domestic manufacturing progress

China's leading contract semiconductor manufacturer, SMIC, has been developing advanced processes without access to the same equipment ecosystem.

Huawei's Ascend 910B has been associated with SMIC's N+2 process, commonly classified as a 7 nm class technology.

In December 2025, TechInsights published a physical analysis of Huawei's Kirin 9030 processor.

Its findings confirmed that SMIC had progressed to N+3.

This represents an improvement over its previous manufacturing generation.

However, process names should be interpreted carefully.

Terms such as 2 nm, 3 nm, 5 nm, and 7 nm are commercial technology-node labels rather than direct measurements of one physical transistor dimension.

Different manufacturers' node names do not necessarily imply identical transistor density, performance, or energy efficiency.

A meaningful comparison requires examining actual circuit density, power consumption, transistor performance, manufacturing yields, and production cost.

TechInsights characterized N+3 as an important step forward but not equivalent to the leading commercial manufacturing technologies available from TSMC.

1.3. EUV lithography: Why manufacturing equipment matters

Extreme ultraviolet lithography is one of the most important technologies used in leading-edge semiconductor production.

EUV systems use light with a wavelength of 13.5 nm to pattern extremely small features on semiconductor wafers.

These machines are produced by ASML, based in the Netherlands.

They incorporate highly sophisticated optical systems, light sources, vacuum technology, precision positioning, and control systems.

Export restrictions have prevented the sale of ASML EUV systems to Chinese manufacturers.

Without EUV, advanced semiconductor production increasingly depends on techniques involving deep ultraviolet lithography and multiple patterning.

1.4. Why multiple patterning is expensive

Multiple patterning divides a complex circuit layer into multiple exposure and processing steps.

This can extend the capabilities of older lithography technologies.

However, additional steps can introduce:

1. Longer manufacturing cycles.
2. Greater equipment utilization.
3. More materials and consumables.
4. Increased alignment requirements.
5. Additional opportunities for defects.
6. Reduced manufacturing yields.

The result is a complex economic problem.

Even if a manufacturer can produce a functioning advanced chip, commercial competitiveness depends on the number of usable chips produced per wafer and the total manufacturing cost.

1.5. Domestic EUV development

Reuters reported in December 2025 that China had developed an experimental EUV system in Shenzhen.

According to that reporting, the prototype could generate EUV radiation but had not demonstrated commercial chip production.

This is a significant distinction.

Building an experimental light source is one milestone.

Manufacturing high-performance semiconductors reliably at industrial scale is another.

Production equipment must meet demanding requirements for overlay accuracy, throughput, optical performance, process control, maintenance, and uptime.

A working prototype demonstrates technological progress. Commercial yields and sustained throughput determine industrial competitiveness.

2. High-Bandwidth Memory: Why Compute Needs Data

Modern AI accelerators are designed to perform enormous numbers of mathematical operations.

However, their performance depends on keeping processing units supplied with data.

Without sufficient memory capacity and bandwidth, processing resources can spend significant time waiting.

High-bandwidth memory addresses this problem.

2.1. How HBM works

HBM integrates multiple DRAM dies into vertically stacked structures.

Through-silicon vias and high-density interfaces help connect the layers, enabling a very wide memory interface.

The memory stacks are placed close to the compute dies through advanced packaging technologies.

The objectives are:

• High memory bandwidth.
• Improved energy efficiency per transferred bit.
• Greater memory density near the accelerator.
• Reduced communication distance compared with conventional external memory systems.

For AI workloads, HBM has become a critical component rather than an optional performance enhancement.

2.2. The global HBM market

According to Counterpoint Research, revenue market shares in Q2 2026 were:

Company	HBM revenue share
SK hynix	50%
Samsung	33%
Micron	18%

Figures are rounded and may not total exactly 100%.

At that point, HBM3E still represented most industry HBM revenue, while HBM4 shipments were beginning to become more significant.

These three companies form the core of the advanced HBM supply chain.

For Chinese accelerator manufacturers, reliance on memory suppliers outside mainland China creates additional complexity under export controls.

2.3. Export restrictions and domestic HBM development

In December 2024, the US Bureau of Industry and Security introduced additional semiconductor export controls.

The measures covered advanced manufacturing equipment, certain semiconductor-related software, and specified categories of high-bandwidth memory.

They also added 140 entities to the Entity List.

This increased the strategic importance of domestic HBM development for Chinese manufacturers.

CXMT has become one of the most important companies in China's memory industry.

Its expansion into advanced DRAM and HBM technologies represents a potential alternative supply route.

However, memory self-sufficiency requires far more than a technically functioning design.

Manufacturers must also establish:

1. Reliable wafer production.
2. Advanced DRAM process technology.
3. Vertical stacking capabilities.
4. Thermal and mechanical integration.
5. Testing and quality control.
6. Packaging compatibility.
7. Consistent delivery volumes.

A production bottleneck in any of these areas can limit the number of completed accelerators.

2.4. Comparing accelerator memory specifications

Published accelerator specifications illustrate how important memory technology has become.

Accelerator	HBM capacity per accelerator	Peak memory bandwidth
NVIDIA B200	180 GB	Approximately 8 TB/s
AMD MI355X	288 GB HBM3E	8 TB/s
Huawei Ascend 950 generation	144 GB HiZQ 2.0	4 TB/s
NVIDIA Rubin	288 GB HBM4	22 TB/s

These are vendor-published hardware specifications. Availability, implementation, and achieved application performance vary. Rubin and certain Ascend configurations represent newer announced product generations.

The differences are substantial.

But memory bandwidth alone does not establish which accelerator is faster for a real application.

Actual performance also depends on the processor architecture, model structure, precision, memory-access patterns, kernels, and software optimizations.

It is equally important to distinguish memory specifications per accelerator from those per individual HBM stack.

Comparisons must use equivalent units and system boundaries.

3. Advanced Packaging: The Manufacturing Stage Most People Overlook

A modern AI accelerator package may combine multiple compute dies and several HBM stacks.

Connecting these components requires extremely dense and reliable electrical interfaces.

This is the domain of advanced semiconductor packaging.

3.1. Why packaging is now a strategic technology

Traditional semiconductor packaging was primarily associated with protecting chips and connecting them to circuit boards.

Modern advanced packaging performs a much more demanding role.

It enables:

• High-density chip-to-chip connections.
• Integration of compute dies and HBM.
• Large interposers and complex substrates.
• High aggregate memory bandwidth.
• Multi-die accelerator architectures.

These capabilities are essential to many leading AI accelerator designs.

3.2. TSMC's CoWoS technology

TSMC's Chip-on-Wafer-on-Substrate technology, commonly known as CoWoS, is a major enabler of modern AI computing packages.

CoWoS allows compute components and memory stacks to be integrated within a high-performance package.

But this technology also creates manufacturing dependencies.

Even with enough compute dies and HBM memory, a shortage of advanced packaging capacity can prevent those components from becoming completed accelerator products.

As demand grows, packaging availability can become a limiting factor in the entire supply chain.

TSMC has been expanding its advanced packaging capacity, and its leadership acknowledged capacity pressure during 2026.

3.3. China's advanced packaging industry

Chinese companies including SJ Semiconductor, JCET, Tongfu, and Huatian are developing and expanding advanced packaging technologies.

Their challenge involves not only increasing capacity but also supporting increasingly complex accelerator packages.

This requires specialized equipment, high-density substrates, thermal management, process integration, and dependable yields.

The strategic lesson is that semiconductor leadership depends on manufacturing completed systems, not simply producing silicon dies.

4. AI Accelerator Architectures: Comparing the Building Blocks

Accelerator specifications often emphasize peak floating-point performance.

However, FLOPS comparisons can be misleading if they combine different numerical formats or sparsity assumptions.

4.1. FP8, BF16, and FP4 are not interchangeable

Modern AI processors support different numerical formats.

BF16

A 16-bit floating-point format commonly used for model training.

FP8

An 8-bit floating-point format designed to reduce memory and compute requirements for supported workloads.

FP4

A 4-bit format used in increasingly aggressive quantization and low-precision computing.

Hardware specifications may also include performance with structured sparsity.

This can increase theoretical throughput under qualifying conditions.

A comparison between BF16 throughput on one accelerator and FP8 throughput on another is not a direct performance comparison.

Likewise, sparse and dense FLOPS should not be mixed without explanation.

4.2. Selected AI accelerator specifications

Accelerator	Memory	Memory bandwidth	Performance reference
NVIDIA B200	180 GB	About 8 TB/s	About 4.5 PFLOPS dense FP8
AMD MI355X	288 GB	8 TB/s	5 PFLOPS dense FP8
Huawei Ascend 910C	128 GB	About 3.2 TB/s	Estimated BF16 performance, not directly comparable to FP8
Huawei Ascend 950DT	144 GB	4 TB/s	Huawei-announced next-generation specifications
NVIDIA Rubin	288 GB	22 TB/s	New architecture with support for lower-precision formats

Figures describe selected vendor specifications and independent estimates. They are not a unified benchmark dataset. Performance comparisons require matched precision, sparsity, workload, and deployment configurations.

The important observation is not simply which accelerator has the largest number.

It is that accelerator performance depends on the combination of compute throughput, memory bandwidth, connectivity, and software.

5. China's Alternative Strategy: Scaling at the System Level

China's semiconductor manufacturing constraints have contributed to a distinct approach to AI infrastructure.

If individual accelerators cannot immediately match the strongest available competitors, one alternative is to connect more of them.

Huawei's large-scale accelerator systems demonstrate this strategy.

5.1. CloudMatrix 384

Huawei's CloudMatrix 384 uses 384 Ascend 910C processors.

SemiAnalysis compared the design with NVIDIA's GB200 NVL72 system.

The comparison found several notable differences.

Metric	CloudMatrix 384 relative to GB200 NVL72
Accelerator count	384 vs. 72
Aggregate dense BF16 compute	Nearly 2 times higher
Aggregate memory capacity	About 3.6 times higher
Aggregate memory bandwidth	About 2.1 times higher
System power consumption	About 4.1 times higher
Performance per watt	Significantly lower

These are SemiAnalysis estimates from its April 2025 system comparison. They are not universal application-level benchmark results.

This illustrates a fundamental engineering trade-off.

The system uses more accelerators and a larger interconnect network to provide high aggregate computing capability.

But the energy cost rises substantially.

5.2. Why interconnect architecture matters

Large-scale AI training frequently requires accelerators to exchange parameters, gradients, activations, and other data.

Network communication can become a significant fraction of total execution time.

An accelerator that waits for data from another processor is not fully using its computing capacity.

Consequently, system-level performance depends on:

1. Interconnect bandwidth.
2. Communication latency.
3. Network topology.
4. Collective communication efficiency.
5. Memory accessibility.
6. Congestion behavior.
7. Hardware and software coordination.

Huawei's UnifiedBus is designed to improve communication across large accelerator systems.

The objective is to make multiple physical processors operate as parts of a more tightly integrated computing environment.

5.3. The energy trade-off

More accelerators require more electrical power.

They also create additional demands for cooling, racks, networking hardware, and maintenance.

System efficiency therefore becomes increasingly important.

In the CloudMatrix comparison, the larger aggregate computing capability came with substantially higher total power consumption.

This may be acceptable in environments where large amounts of electricity are available at relatively low cost.

In power-constrained locations, however, infrastructure efficiency becomes more important.

The useful metric is not simply total peak FLOPS. It is useful computing output relative to electricity, cost, and operational complexity.

6. The Next Generation: UnifiedBus, Atlas SuperPoDs, and Optical Interconnects

Huawei has continued expanding its system-level strategy.

Its September 2025 roadmap outlined ambitious configurations for future Atlas systems.

The Atlas 950 SuperPoD roadmap described configurations reaching 8,192 processors.

A larger Atlas 960 roadmap described a system reaching 15,488 processors.

These figures were roadmap targets, not evidence that every configuration had already entered large-scale commercial deployment.

6.1. The September 2026 update

At HUAWEI CONNECT 2026, Huawei introduced the Atlas 960E SuperPoD.

Its announced architecture supports:

• Up to 4,096 AI processors.
• 8 EFLOPS of FP8 computing capability.
• 16 EFLOPS of FP4 computing capability.
• Up to 1 PB of HBM.
• UnifiedBus-based interconnection.
• Near-packaged optical modules.

These figures are theoretical manufacturer specifications.

Actual performance depends on the implemented system, workload, software, and operating conditions.

6.2. Hi-ONE and near-packaged optics

One of the most technically interesting developments is Huawei's Hi-ONE optical technology.

The company uses near-packaged optics, or NPO, to improve interconnection density and efficiency.

Traditional large-scale optical networks rely heavily on pluggable optical transceivers.

As clusters grow, these modules consume electrical power, occupy physical space, and introduce additional complexity.

Huawei states that the Atlas 960E design uses approximately 5,500 Hi-ONE units rather than around 48,000 conventional 800G optical modules.

The company claims this reduces interconnect power consumption by more than 550 kW for the compared configuration.

These are vendor-provided estimates and should be interpreted within the scope of the stated comparison.

Nevertheless, the engineering direction is important.

Reducing networking overhead can improve the practical economics of very large AI systems.

6.3. Updated accelerator roadmap

In September 2026, Huawei announced that development of its Ascend 960 processors was progressing ahead of schedule.

The updated plan includes:

1. Ascend 960DT availability in Q1 2027.
2. Ascend 960PR availability in Q3 2027.
3. Additional Ascend generations planned for 2028 and 2029.

This demonstrates continued investment in individual processor capabilities alongside system architecture.

However, roadmap specifications must be distinguished from production shipments and independent benchmarks.

7. NVIDIA's Platform Strategy: Beyond the Individual GPU

Huawei is not alone in shifting attention toward system-level computing.

NVIDIA has increasingly presented its AI infrastructure as an integrated computing platform.

Its architectures combine processors, memory, high-speed interconnects, networking equipment, and software.

7.1. Blackwell and rack-scale systems

NVIDIA's Blackwell generation emphasized multi-GPU computing, high aggregate memory bandwidth, and tightly connected accelerator systems.

The GB200 NVL72 design connects 72 GPUs within a rack-scale configuration.

This enables large AI workloads to use a substantial pool of accelerator resources.

System design is especially important for large-model training and inference, where communication overhead can limit scaling.

7.2. Rubin and NVLink 6

NVIDIA's Rubin generation further develops this approach.

Its published specifications include:

• 288 GB HBM4 per GPU.
• Up to 22 TB/s of HBM bandwidth.
• NVLink 6 with 3.6 TB/s of scale-up bandwidth.
• Integration with the wider Vera Rubin platform.

These capabilities target the increasing demands of large-scale AI training and inference.

NVIDIA is attempting to improve the efficiency of the complete computing platform rather than treating every GPU as an isolated component.

7.3. Why hardware integration matters

A large AI computing system contains several sources of overhead:

• Data movement between accelerators.
• Memory access.
• Synchronization.
• Network communication.
• Power delivery.
• Cooling.
• Distributed workload scheduling.

Optimizing individual processors while ignoring these costs can limit real system performance.

The strongest infrastructure designs address these constraints together.

8. Software Ecosystems: CUDA, ROCm, and CANN

Hardware performance is only useful when applications can access it efficiently.

This is where software becomes a strategic advantage.

8.1. NVIDIA CUDA

CUDA is one of NVIDIA's most important strengths.

Over many years, developers have built software around the platform.

The ecosystem includes:

1. Optimized computational libraries.
2. Machine learning framework integrations.
3. Compiler and kernel development tools.
4. Distributed training support.
5. Debugging and profiling utilities.
6. Broad deployment experience across AI infrastructure.

This creates an advantage that cannot be captured in a simple accelerator specification table.

8.2. AMD ROCm

AMD is also investing in accelerator software through ROCm.

Its objective is to provide tools, libraries, and framework support for AMD GPU computing.

ROCm is an important component of AMD's effort to compete in large-scale AI infrastructure.

As with any accelerator ecosystem, performance depends on workload support, maturity, and optimization.

8.3. Huawei CANN

Huawei is developing its CANN software ecosystem for Ascend accelerators.

In September 2026, Huawei reported that Ascend supported more than 90 third-party open-source projects, including PyTorch, Triton, and vLLM.

The company is also pursuing more open development of its software stack.

This can reduce barriers to adoption.

However, framework compatibility should not be confused with complete performance parity.

A workload may run correctly while still requiring substantial optimization.

8.4. What developers actually need

Before selecting an accelerator platform, engineering teams should evaluate:

1. Framework compatibility.
2. Kernel performance.
3. Compiler maturity.
4. Distributed training support.
5. Available debugging tools.
6. Memory management behavior.
7. Infrastructure orchestration.
8. Vendor support and ecosystem activity.

The real performance of an accelerator is determined by hardware and software working together.

9. Export Controls and Industrial Policy

The semiconductor supply chain has become increasingly influenced by trade restrictions and industrial policy.

The US introduced major advanced computing and manufacturing export controls in October 2022.

Additional measures followed in subsequent years.

Selected developments

Period	Development
October 2022	Major US restrictions on advanced computing chips and semiconductor manufacturing technologies
December 2024	Expanded US controls covering specified HBM, equipment, software, and additional entities
April 2025	Additional licensing restrictions affected selected NVIDIA AI accelerators
December 2025	Reuters reported development of an experimental domestic EUV prototype in China
2026	Limited licensed shipments of NVIDIA H200 hardware to China were reported
September 2026	Huawei announced an updated Ascend roadmap and Atlas 960E architecture

These developments have created a complex environment for manufacturers, suppliers, and customers.

The United States has used export licensing as one means of restricting access to selected advanced technologies.

China has increased investment in domestic alternatives while also using trade and regulatory measures affecting the technology supply chain.

Neither side operates independently of the rest of the world.

9.1. The international nature of semiconductor manufacturing

A modern AI accelerator can depend on contributions from several countries.

For example:

• US companies design accelerators.
• Taiwanese foundries manufacture leading-edge dies.
• Dutch lithography systems enable advanced fabrication.
• South Korean and US memory suppliers produce HBM.
• Japanese companies supply important equipment and materials.
• Packaging operations may span several countries.

This specialization supports technological progress but creates supply-chain concentration.

9.2. Semiconductor equipment spending

According to SEMI, semiconductor manufacturing equipment spending in China reached approximately $49.3 billion in 2025.

This was higher than the amount reported for any other individual region.

Large equipment spending does not automatically mean access to the most advanced manufacturing technology.

Much of the investment also supports mature-node production and other manufacturing capabilities.

Nevertheless, it demonstrates the scale of China's effort to expand its domestic semiconductor industry.

10. Comparing the Two Technology Ecosystems

A useful comparison must look beyond individual chip specifications.

Technology layer	US and international partner ecosystem	China's domestic ecosystem
Advanced manufacturing	TSMC high-volume 2 nm production	SMIC N+3 development
EUV lithography	Commercial ASML EUV equipment	Experimental domestic development
Advanced HBM	SK hynix, Samsung, Micron	CXMT and domestic alternatives
Advanced packaging	CoWoS and other established solutions	Expanding domestic 2.5D packaging
AI accelerators	NVIDIA, AMD, and other designers	Huawei Ascend and other local developers
Interconnects	NVLink, Infinity Fabric, networking platforms	UnifiedBus and optical interconnect development
Large computing systems	Blackwell and Rubin platforms	CloudMatrix and Atlas SuperPoDs
Software ecosystems	CUDA, ROCm, and supporting frameworks	CANN and expanding open-source integration
Key constraints	Advanced packaging, infrastructure power, geographic concentration	Leading-edge lithography, HBM supply, manufacturing yields, software maturity

This table is a simplified picture.

The ecosystem is highly international, and the capabilities described are not necessarily available at equivalent production volumes.

11. Five Metrics That Will Matter More Than Peak FLOPS

Peak theoretical FLOPS remain useful for understanding processor capabilities.

But they are insufficient for evaluating large AI infrastructure.

11.1. Useful throughput

How many training or inference operations can the system complete under realistic workloads?

For inference, this may include tokens generated per second under specified latency constraints.

For training, it may include time to complete a training run or processing throughput for a defined model.

11.2. Performance per watt

How much useful computation does the system deliver for the electricity consumed?

This matters as data centers face constraints in power availability and cooling.

11.3. Memory efficiency

Does the system have sufficient memory capacity and bandwidth to support its workloads?

A processor with high theoretical computing throughput can be underutilized when memory access becomes the bottleneck.

11.4. Communication efficiency

How effectively can processors exchange data?

A large cluster with poor communication efficiency may deliver disappointing scaling even when aggregate theoretical compute is enormous.

11.5. Total cost of ownership

The cost of operating AI infrastructure includes far more than the purchase price of accelerators.

A proper analysis should account for:

• Hardware acquisition.
• Electricity.
• Cooling.
• Networking.
• Facility requirements.
• Software development.
• Maintenance.
• Reliability.
• Utilization.
• Replacement cycles.

The winning architecture is not necessarily the one with the highest theoretical performance. It is the one that delivers the required work reliably and economically.

12. What Happens Next?

Several developments will shape the next phase of competition.

Manufacturing

Can China improve domestic advanced-node production yields and develop commercially competitive lithography equipment?

Can international suppliers expand leading-edge capacity while reducing geographic concentration?

Memory

Will Chinese manufacturers be able to produce advanced HBM in sufficient volumes?

Can global memory suppliers expand output fast enough to match accelerator demand?

Packaging

Will advanced packaging capacity grow quickly enough to avoid limiting finished accelerator supply?

Interconnects

How much can optical technologies and improved network architectures reduce communication overhead?

Software

Can alternative accelerator ecosystems achieve the maturity needed to support demanding production workloads?

Energy

Will data center electricity availability become a more important constraint than raw processor production?

These questions are closely connected.

Progress in one area can expose bottlenecks in another.

Conclusion: Two Paths Toward the Same Computing Problem

The AI chip race is becoming a competition between industrial systems.

The US and its international partners possess important advantages in advanced semiconductor manufacturing, HBM supply, accelerator design, and software maturity.

China is developing its own manufacturing capabilities, memory supply, accelerator designs, packaging, and software.

It is also pursuing a system-level strategy that uses larger numbers of interconnected processors to compensate for some individual hardware limitations.

That strategy has demonstrated substantial aggregate computing potential.

But it also creates trade-offs in electricity consumption, cooling, networking complexity, and infrastructure cost.

The most important lesson is that the future of AI computing cannot be understood through one GPU benchmark.

Compute performance depends on an entire chain, from lithography and manufacturing yields to memory bandwidth, packaging, interconnects, software, and power availability.

During the Space Race, technological competition was measured through launch vehicles and missions.

In the AI chip race, the outcome may be measured through a much less visible metric.

How efficiently can an entire computing ecosystem convert electricity and semiconductor technology into useful AI performance?

That may ultimately matter more than which manufacturer produces the fastest individual chip.

References and Further Reading

Semiconductor manufacturing and lithography

1. TSMC: 2025 Annual Report
2. TSMC: Q4 2025 Financial Results
3. TechInsights: SMIC N+3 Confirmed Through Kirin 9030 Analysis
4. Reuters: China's Experimental EUV Development

Memory and AI accelerator specifications

1. Counterpoint: Global DRAM and HBM Market Share
2. [AMD: Instinct MI355X Specifications](https://www.amd.com/en/products/accelerators/instinct/mi350