My Final Project
We use antennas for all communication purposes like mobile, WiFi, etc. While using antenna array, we may not need to send power to all the antennas. This project aims to reduce power consumption by turning off and on the antennas at some regular intervals (usually different for each of the antenna) while achieving the same result.
How I built it
For the project I used Verilog for the project on the Xilinx Vivado platform to control the FPGA. We used ZC706 board.
Additional Thoughts / Feelings / Stories
It was quite an interesting project on FPGA and antenna especially a nice integration between hardware and software.
Oldest comments (1)
Very interesting šš