How to place and wire microcontrollers beside each other on PCB?

Here’s a practical blueprint for placing two (or more) microcontrollers side-by-side on a PCB—what to place where, how to wire buses, and what to watch for so it routes cleanly and works first try.

1) Floorplan first

• Face the pins you’ll interconnect toward each other. Rotate parts so SPI/I²C/UART pins align; it saves vias and length.
• Leave a routing alley between MCUs (at least one trace+via channel per signal group). 10–20 mm part-to-part spacing is a good start.
• Crystals/oscillators go near each MCU, short guarded traces, away from each other and from hot/high-dv/dt nodes.
• Put program/debug headers (Tag-Connect or 2×5/2×3) at the board edge for probes; don’t bury them between MCUs.
• Keep high-current / noisy power parts (buck inductors, FETs) a little away; run their return currents straight to the power entry, not under logic.

2) Power distribution (one plane, local isolation)

• Use a solid GND plane under both MCUs. If 4-layer: L1 signals, L2 GND, L3 power, L4 signals.
• Feed 3V3 (or 5V) with a plane or fat spine. Add a ferrite bead per MCU power island + local bulk: FB (≥600 Ω@100 MHz) → 4.7–10 µF → MCU VDD pins.
• Decoupling per VDD pin: 0.1 µF (0402/0603) within 1–3 mm of the pin, via directly to the GND plane. Add one 1–4.7 µF nearby.
• If rails differ, level-shift all cross-domain nets; prefer translators with Ioff so they don’t back-power an unpowered MCU.

3) Reset, boot & power-up

• Give each MCU an RC reset (or supervisor IC). Provide a test pad for NRST.
• If one MCU must reset the other, do it with open-drain + pull-up on the target’s reset line.
• Strap boot/config pins with resistors (10–100 k). Break them out to pads or 0 Ω links for bring-up changes.

4) Choose the interconnect pattern
I²C (multi-drop, easy)

VDD ──4.7k── SDA ───────── MCU_A
          └─────────────── MCU_B
VDD ──4.7k── SCL ───────── MCU_A
          └─────────────── MCU_B

• One set of pull-ups for the segment (2.2–4.7 k at 100–400 kHz). Keep traces short and on one layer over solid GND.
• Ensure unique addresses (strap ADDR pins or use an I²C mux if conflicts).

SPI (fast, point-to-point or shared)

Peer link (A master, B slave):

A_MOSI → B_MOSI   (a.k.a. A_TX → B_RX)
A_MISO ← B_MISO
A_SCLK → B_SCLK
A_CS_B → B_CS
(22–47 Ω series at the driver ends)

• For one master ↔ multiple slaves, share SCLK/MOSI, give each slave its own CS, and ensure slaves tri-state MISO; series 22–47 Ω on SCLK/MOSI and each MISO helps ringing/contention.
• Keep the clock short, over a continuous GND plane. Avoid stubs.

UART (simple, robust)

A_TX → B_RX   (add ~100 Ω series near A_TX if edges ring)
A_RX ← B_TX
GND ↔ GND

For >2 nodes, use RS-485 transceivers (A/B differential), 120 Ω termination at the two ends, short stubs.

CAN FD (when you want multi-MCU robustness)

Place the 60 Ω total (two 120 Ω ends) at the segment ends, stubs just a few cm. Common-mode choke + TVS near connector.

5) Clocking guidance

• Separate crystals per MCU are simplest. Keep crystal traces <20 mm, no vias, matched length to pins, guard with GND.
• If sharing a clock, buffer it and route point-to-point (no T-stubs). Treat like a high-speed net.

6) Signal-integrity & EMC

• Keep every signal over an unbroken reference plane; don’t cross plane splits. Stitch ground with vias at layer transitions and around bus entries.
• Use series damping (22–47 Ω) on fast edges (SPI SCLK/MOSI, GPIO handshakes).
• Add ESD/TVS near external connectors, not deep inside near MCUs.
• For analog pins (ADC refs), give them a quiet moat/plane and rejoin to main GND at a single point near the MCU.

7) Handling unpowered neighbors (back-powering)

• Cross-MCU GPIOs should have series ~100–1k Ω or be open-drain with pull-ups so an unpowered chip isn’t fed via ESD diodes.
• Prefer bus switches/level shifters with Ioff on shared buses.
• If one MCU can power down, isolate its IOs (or place it downstream of a switch).

8) Programming & debug (don’t skimp)

• SWD/JTAG: easiest is one header per MCU.
  • SWD doesn’t daisy-chain; if you must share, add a small SWD mux or jumpers.
  • JTAG can chain (TDI→TDO), but only if both support it and tools are set up.
• Keep SWD/JTAG, NRST, BOOT pins accessible; label test pads.

9) Thermal & mechanical

• Give each MCU a copper pad under the package with thermal vias to spread heat to inner/other layers.
• Don’t park crystals over hot areas; avoid placing sensitive analog pins near inductors or transformers.

10) Bring-up-friendly checklist (values you can copy-paste)

• Decoupling per VDD pin: 0.1 µF X7R + one 1–4.7 µF nearby.
• Ferrite bead per MCU rail: ≥600 Ω@100 MHz; bulk 4.7–10 µF after bead.
• I²C pull-ups: 2.2–4.7 k to rail used by both MCUs.
• Series resistors: 22–47 Ω on SPI clock/data; 100 Ω on one-way GPIO handshakes; 0–4.7 k on reset drives (open-drain).
• Level shifting: SN74LVC/LV1T/LVCH; for open-drain I²C use MOSFET translators (e.g., BSS138-style) or dedicated ICs.
• Test pads: SWDIO/SWCLK/NRST/TX/RX and key power rails.

Minimal two-MCU example (3.3 V, SPI + I²C + UART)

• Power: 3V3 plane → FB → local bulk (10 µF) → decaps at pins.

• Buses:

  • I²C (SDA/SCL) shared, 4.7 k pull-ups.
  • SPI (A master): SCLK/MOSI shared; CS_B to B; MISO from B; 33 Ω series at A on SCLK/MOSI and at B on MISO.
  • UART cross between them for bootloader logs.

• Control: A has a GPIO (open-drain) to reset B through 0 Ω link + pull-up on B.

• Debug: two Tag-Connects (or a 10-pin shared header with jumpers).