China's 14nm AI chip claims 520 TFLOPS and 6.4TB/s bandwidth via software-defined and 3D near-memory architecture, bypassing advanced node restrictions.
China's new AI chip delivers 520 TFLOPS at 14nm using software-defined computing and 3D near-memory architecture. The design achieves 6.4 TB/s memory bandwidth through architectural innovation rather than process node scaling, according to Pandaily.
Key facts
- 520 TFLOPS peak performance at 14nm node
- 6.4 TB/s memory bandwidth via 3D near-memory stack
- Software-defined compute fabric for reconfigurable AI workloads
- No independent benchmarks or third-party verification published
- Power consumption and die size not disclosed
The chip, whose manufacturer has not been publicly named, targets AI inference and training workloads with a software-defined compute fabric that can be reconfigured for different neural network topologies. The 3D near-memory computing approach stacks memory dies directly atop the compute logic, reducing data movement latency and power consumption compared to traditional chiplet or PCB-based memory architectures.
Architecture Details
The chip employs a 'software-defined computing' paradigm where the hardware logic is not fixed at fabrication time but can be reconfigured via software for specific AI operations. This allows the same silicon to optimize for convolutional layers, transformer attention mechanisms, or sparse matrix operations without separate hardware accelerators. According to the source, the 3D near-memory stack achieves 6.4 TB/s memory bandwidth, approximately 5x higher than typical HBM2e implementations at similar power envelopes.
Process Node vs. Architecture Trade-off
Using a 14nm process node is significant because China faces export restrictions on advanced EUV lithography equipment needed for 7nm and below. By achieving 520 TFLOPS at 14nm, the design demonstrates that architectural innovation can partially compensate for process node disadvantages. For comparison, NVIDIA's A100 delivers 312 TFLOPS at 7nm, while the H100 achieves 1,979 TFLOPS at 4nm. The Chinese chip's performance per watt has not been disclosed.
Verification Status
The claimed 520 TFLOPS figure has not been independently verified. No third-party benchmarks or peer-reviewed publications have been released. The manufacturer has not disclosed the chip's power consumption, die size, or manufacturing yield. [Per the source], the chip is in early production with unspecified domestic Chinese customers.
What to watch
Watch for independent benchmark results from Chinese AI labs (Baidu, Alibaba, Tencent) or third-party evaluations like MLPerf. The chip's real-world performance against NVIDIA's H100 in inference-heavy workloads will determine whether architecture can truly substitute for process node leadership.
Source: pandaily.com
[Updated 14 Jul via pandaily]
The chip is developed by Shanghai-based start-up Dongfang Suanxin, backed by state funds and domestic tech giants, according to a report by the South China Morning Post. The company announced on Monday that its strategy relies on software-defined computing and 3D-stacked near-memory architecture to reduce dependence on advanced manufacturing processes and circumvent US export controls. [per SCMP]
Originally published on gentic.news
Top comments (0)