Google booked Intel to package 3M+ TPUs in 2028 as TSMC CoWoS capacity caps out. SK hynix tests HBM on Intel EMIB, potentially unlocking Nvidia's Feynman architecture.
Google booked Intel to package more than 3 million TPUs in 2028, per The Information. The order comes as TSMC's CoWoS lines remain sold out through 2027, forcing hyperscalers to qualify a second packaging source.
Key facts
- Google ordered 3M+ TPUs from Intel for 2028 packaging.
- TSMC CoWoS sold out through 2027 per CEO C.C. Wei.
- SK hynix testing HBM integration with Intel EMIB.
- Nvidia evaluating Intel for Feynman architecture in 2028.
- Intel EMIB achieves ~90% package utilization vs CoWoS.
Google placed an order for Intel to package more than 3 million of its TPUs in 2028 after months of testing Intel's advanced packaging, according to The Information, citing four people familiar with the matter. The deal moves discussions from April's rumors of active talks between Google, Amazon, and Intel to a concrete unit figure and production timeline.
Why Intel's EMIB Matters
TSMC's CoWoS (chip-on-wafer-on-substrate) is the industry-standard packaging for AI accelerators, but CEO C.C. Wei told shareholders at the June 4th annual meeting that demand will exceed supply for years, even as TSMC builds out U.S. capacity. Nvidia consumes roughly 60% of global CoWoS output this year, with Broadcom and AMD taking another 26%, leaving custom-ASIC designers like Google waiting in a queue that won't clear soon.
Intel's embedded multi-die interconnect bridge (EMIB) embeds small silicon bridges in the organic substrate only where dies need to connect, achieving package utilization near 90% versus CoWoS's larger interposer that wastes silicon at the edges. SK hynix is now testing whether its high-bandwidth memory works reliably with Intel's packaging, a qualification that would determine whether EMIB can serve Nvidia accelerators too.
Nvidia's Feynman Architecture
Nvidia is reportedly evaluating Intel to build a future processor that fuses four GPU dies into one unit, tied to its Feynman architecture due in 2028. If SK hynix qualifies HBM on EMIB, Intel could become a second packaging supplier for Nvidia's next-generation chips, breaking TSMC's near-monopoly on high-volume AI packaging.
Historical Context
Google's order follows a pattern of hyperscalers diversifying supply chains. Amazon was reported in active discussions with Intel for its custom AI processors in April. The TPU order also aligns with Google's broader infrastructure push: the company committed $11B/year to SpaceX for compute at xAI data centers and finalized an $11B acquisition of energy developer Intersect for data center power.
What to Watch
SK hynix's HBM qualification results on Intel's EMIB, expected in late 2026 or early 2027, will determine whether Intel's packaging can serve Nvidia's Feynman architecture. Also watch for Amazon's Trainium and Inferentia packaging decisions, as AWS remains the third major hyperscaler evaluating Intel's EMIB.
Source: tomshardware.com
Key Takeaways
- Google booked Intel to package 3M+ TPUs in 2028 as TSMC CoWoS capacity caps out.
- SK hynix tests HBM on Intel EMIB, potentially unlocking Nvidia's Feynman architecture.
Originally published on gentic.news
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