A logical gate on a surface code is not a pulse. It is a region of spacetime: so many physical qubits held stable for so many error-correction cycles. lattice-surgery patch merges and braided defect pairs implement the same CNOT with very different shapes for that region. The headline number people quote is code distance, but what a machine actually buys is the product of width and depth, and that product is where the two architectures separate.
Under braided defect pairs, a pair of defects is created, dragged around one another through the lattice and then annihilated. The route length sets the number of syndrome-extraction rounds, and the defects must stay separated by a distance comparable to the code distance or the logical information leaks. Under lattice-surgery patch merges, two planar patches are instead held still and a joint parity measurement is performed along their shared boundary. Nothing has to travel, but the boundary measurement must be repeated for roughly a full code distance of rounds to suppress measurement errors.
The resource that decides logical-gate throughput is spacetime volume, not code distance, and the two architectures spend that volume in completely different places.
Part One: What is actually being compared
Before comparing lattice-surgery patch merges with braided defect pairs, it helps to name the unit of account. In surface-code logical-gate scheduling the tempting unit is the headline specification, because it is printed on a datasheet and can be ranked. The unit that actually appears in a budget is the sum of three things: the cost paid before the first unit of value, the cost paid on each unit, and the cost of the occasions when the system behaves badly. Once those three are written on one line, most of the specification argument stops being interesting.
The cost structure diverges in a way that a per-unit comparison hides. With lattice-surgery patch merges, a meaningful part of the spend is committed before the first useful result; with braided defect pairs, the spend arrives as a variable charge attached to each operation. A committed cost rewards volume and punishes a bad quarter, because it stays even when utilisation collapses. A variable cost is gentler operationally but removes the incentive to build spare capacity before it is needed.
Part Two: The arithmetic that decides it
Put numbers on the shape. At distance 11, a braided CNOT in a planar layout occupies a region on the order of a few thousand qubit-rounds once the defect corridors are counted; a surgery-based merge typically lands near a thousand to fifteen hundred qubit-rounds for the same target error. The ratio is not a constant, though. It improves as the code grows, because braid route length grows with distance while the merge boundary grows more slowly. That is why a demonstration at distance 3 says almost nothing about a machine at distance 25.
The mechanism behind the trade is about information rather than physics. lattice-surgery patch merges makes one part of the problem observable and therefore cheaper to plan around, while braided defect pairs leaves it implicit and pays for it in variance. Whenever a design makes something measurable, somebody still has to build the instrument, keep it calibrated and act on its readings, and those three obligations are where a theoretical advantage is usually spent.
The second-order consequence is organisational rather than technical. Choosing lattice-surgery patch merges creates a dependency on a capability that must be staffed, monitored and kept current. Choosing braided defect pairs keeps that capability outside the team and converts it into a vendor relationship. Both are real costs, and the option that looks cheaper in a spreadsheet is frequently the one that adds a standing meeting to the calendar.
Part Three: Where the simple model breaks
The saving has a bill attached. Every merge requires a stabiliser-measurement schedule that changes mid-circuit, plus a decoder that can interpret a discontinuous syndrome history. If the decoder is tuned for a static patch it will misclassify the boundary rounds, and a single misclassified parity can propagate a logical error into both patches at once. Braiding is slower but its syndrome stream is uniform, which is a real engineering advantage when the decoder is implemented in hardware with a fixed latency budget.
At distance 11 a merge can replace a few thousand qubit-rounds of braid corridor with roughly a thousand to fifteen hundred boundary rounds, but that ratio improves with distance rather than staying fixed.
Part Four: The cost that arrives later
There is also a floor-space argument. A machine built around lattice-surgery patch merges wants many small patches that can be brought adjacent to one another, which pushes toward a regular grid with a routing layer and a large number of switchable couplers. A machine built around braided defect pairs wants long unobstructed corridors. Both consume physical area that does not appear in the qubit count, and at a few hundred logical qubits the interconnect and switch fabric can dominate the die or the cryostat layout more than the qubits themselves.
Expect a split by scale rather than by industry. Large operators can amortise the fixed side of lattice-surgery patch merges and will move first; smaller ones keep braided defect pairs because their load is spiky and their tolerance for operational complexity is low. The genuinely contested ground is the middle, where a managed service can make either option look like the other.
Part Five: What this changes outside the engineering team
The everyday consequence is about who gets a usable machine. A compiler that spends fewer qubit-rounds per gate delivers more logical operations per hour on identical hardware, which is the difference between a chemistry workload finishing overnight and finishing next week. It also changes staffing: a surgery-based toolchain needs a compiler team that understands lattice topology, while a braiding-based one needs a control team that understands long calibrated pulse schedules.
Outside the engineering team the consequence is about who gets access. A system that needs less of the scarce resource can be replicated by organisations that could not have afforded the original, which changes procurement, staffing and the kinds of work that get scheduled. That is a quieter but more durable effect than any single performance number.
For a team choosing a roadmap, the practical question is not which gate has the lower published spacetime volume. It is whether their decoder, their coupler fabric and their compiler can all sustain the merge schedule at the distance they actually intend to run.
A market sizing sanity check
A defensible sizing: if by 2032 a few hundred fault-tolerant machines or large shared installations are in operation, and each spends a low-single-digit million dollars per year on the compiler, decoder and control-plane stack that turns physical qubits into logical gates, the scheduling and decoder-tooling layer sits roughly in the $1B to $3B annual range. The lower bound assumes that layer stays bundled inside vertically integrated vendors; the upper bound assumes independent toolchains are licensed across several hardware families. The biggest uncertainty is the number of distinct hardware architectures that survive, not the qubit count.
All figures here are an author's synthesis of published ranges and a stated model, not a measurement of a shipped system. The point of the arithmetic is to locate the crossover and expose which assumption drives it. A vendor quote will differ, and the direction of that difference is usually more informative than the final number.
The comparison that matters
The comparison that matters is between routing time removed and control complexity added. Patch merges win when the decoder and the switch fabric can keep up and the workload is gate-heavy; braided defects win when a uniform syndrome stream and a simple fixed schedule are worth more than raw gate throughput. A roadmap that quotes only the spacetime volume has priced half of the machine.
The honest caveat is that this ranking is sensitive to one assumption: that the workload keeps its present shape. Shift the mix toward the case where braided defect pairs is strong and the result changes without any technology changing at all. That is why the durable output of an evaluation is not a verdict but the threshold at which the verdict would flip.
Choose the gate implementation by costing the decoder, the switchable couplers and the compiler together at your target distance, not by quoting a small-device demo.
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