Inside PCIe PHY: End-to-End Transmit and Receive Path

This article builds on the PCIe overview and physical layer fundamentals by presenting an end-to-end view of how data flows through the transmit and receive paths. The focus is on how a Transaction Layer Packet (TLP) is transformed into a high-speed serial bit stream and reconstructed at the receiver.

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TRANSMITTER (e.g., Root Complex sending a Memory Write TLP)
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[Data Link Layer]
    Seq# + TLP Header + Data + LCRC (parallel bytes)
            |
            v
[Physical Layer]

    [Framing / Block Formation]
        Gen1/2:
            STP + TLP + END (control symbols embedded in stream)
        Gen3+:
            Data organized into 128-bit blocks
            (packet boundaries inferred, no explicit STP/END)

            |
            v

    [Scrambler]
        Bit stream XOR’d with LFSR sequence
        -> Randomized data for transition density and EMI reduction

            |
            v

    [Encoder / Block Encoding]
        Gen1/2 (8b/10b):
            8-bit -> 10-bit symbol (DC balance + control encoding)

        Gen3/4/5 (128b/130b):
            128-bit block + 2-bit sync header -> 130-bit block

            |
            v

    [Transmit PLL / Clock Generation]
        Reference clock (e.g., 100 MHz)
        -> Generates high-speed serial rate (e.g., 8.0 GT/s for Gen3)

            |
            v

    [Serializer]
        Parallel block -> serial bit stream
        Bit time ≈ 125 ps (Gen3)

            |
            v

    [Differential Driver]
        Drives Tx+ / Tx− pair
        Bit encoded as polarity (Tx+ > Tx− or Tx+ < Tx−)
        (~800 mVpp differential, implementation-dependent)

            |
============|===============================================================
            |
            |
    Tx+ ----|---- Tx−   (PCIe serial link, e.g., 8.0 GT/s)
            |
            |
============|===============================================================
            |
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RECEIVER (e.g., Endpoint receiving the Memory Write TLP)
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[Physical Layer]

    [Differential Receiver]
        Senses (Rx+ − Rx−)
        -> Recovers serial bit stream (noise rejection)

            |
            v

    [Clock Data Recovery (CDR)]
        Extracts clock from data transitions
        Phase Detector -> Loop Filter -> VCO
        -> Sampling aligned to center of Unit Interval (UI)

            |
            v

    [Deserializer]
        Serial stream -> parallel blocks
        (e.g., 130-bit blocks in Gen3+)

            |
            v

    [Decoder / Block Decoding]
        Gen1/2:
            10-bit -> 8-bit symbols

        Gen3/4/5:
            Remove 2-bit sync header
            -> Recover 128-bit scrambled data

            |
            v

    [De-scrambler]
        XOR with same LFSR sequence
        -> Restores original data

            |
            v

    [De-framing / Packet Reconstruction]
        Gen1/2:
            Detect STP / END symbols

        Gen3+:
            Packet boundaries inferred from protocol structure

            |
            v

[Data Link Layer]
    Seq# + TLP Header + Data + LCRC
        -> LCRC validation
        -> Sequence tracking
        -> ACK/NACK via DLLP

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