A passing testbench confirms that the firmware finished. But did the RTL execute every instruction correctly?
Subtle processor defects—such as stale operands, incorrect branch decisions, compressed-instruction mismatches, or broken forwarding paths—can remain hidden even when the final software test passes.
This creates a difficult verification gap: the destination may be correct even when something went wrong during execution.
RTL versus a golden reference
FSiMX Studio addresses this through hardware–software co-simulation.
It runs the RTL processor alongside a golden instruction-set simulator and compares both retirement streams.
RTL execution ↔ Golden ISA reference
For every retired instruction, the comparison can examine:
- Retirement order
- Program counter
- Instruction encoding
- Register writeback
- Execution alignment
At the first meaningful mismatch, the comparison stops and points engineers toward the instruction and pipeline behaviour that caused the divergence.
MATCH → Executions agree
DIVERGENCE → Investigate the first mismatch
CANNOT COMPARE → Check the environment or trace
Keeping these outcomes separate is important. A broken comparison environment should never be reported as a successful execution.
Alignment matters
The RTL and golden reference may not always begin from the same execution point.
Different reset vectors, boot ROM instructions, simulation limits, and compressed-instruction representations can produce false mismatches if the traces are compared without proper alignment and normalization.
A useful co-simulation flow must distinguish between:
- A real RTL defect
- A harmless representation difference
- A limitation in the available trace data
- A problem in the comparison setup itself
Without that discipline, engineers may spend time investigating processor bugs that do not actually exist.
Why it matters
Traditional testbenches tell you whether the program completed.
Retirement-level co-simulation helps reveal whether the processor executed the program correctly throughout the run.
When connected with source code, disassembly, and waveforms, the first divergence can guide engineers toward the relevant instruction, operand, or pipeline stage.
That can turn hours of waveform investigation into a focused debugging exercise.
The takeaway
A passing firmware test is the destination.
Co-simulation verifies the journey.
👉 Explore the complete RISC-V co-simulation debugging workflow on WIOWIZ
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