WIOWIZ SOCVP : Architecture Is Not a Directory Listing

Architecture Is Not a Directory Listing

A folder containing hundreds of HDL files does not tell you what the chip actually builds.

When evaluating an SoC or semiconductor IP, a repository listing answers only one question:

Which files exist?

It does not tell you:

1. Which modules are instantiated
2. How the blocks connect
3. What sits below the design top
4. How deep the hierarchy extends
5. Which files are unused That distinction matters.

Files are not architecture

Consider a simplified repository:

rtl/
├── cpu.sv
├── decode.sv
├── execute.sv
├── memory.sv
├── pcie.sv
└── experimental_block.sv

This directory shows available source files. It does not prove that every module participates in the final design.

A real architectural hierarchy follows instantiated relationships:

soc_top
├── cpu
│ ├── fetch
│ ├── decode
│ ├── execute
│ └── writeback
└── interconnect

If a module is not reachable from the design top, it should not be presented as part of the architecture.

Inspecting hierarchy without exposing RTL

WIOWIZ Studio lets evaluators navigate the hierarchy that a design actually builds—from complete systems down to individual module instances.

The view can expose:

• Module and instance names
• Parent–child relationships
• Hierarchical depth
• Short source-relative filenames

At the same time, it keeps sensitive implementation details protected:

• No RTL source text
• No proprietary algorithms
• No absolute development paths
• No netlists or timing data

This creates a practical middle ground between a high-level block diagram and complete RTL delivery.

From CPU pipelines to complete systems

The same approach can be used to inspect designs ranging from an 18-module CPU pipeline to a 139-module sensor-fusion system.

The objective is not to claim that every inspected design is executing. Hierarchy inspection proves architectural structure; functional execution requires separate evidence.

Keeping those claims separate is essential for credible semiconductor evaluation.

Architecture is not the number of HDL files in a repository—it is the structure the design actually builds.

👉 See how WIOWIZ Studio enables architecture inspection without exposing RTL