LDO Layout Techniques: Ground, Sensing, and Capacitor Placement

LDO Layout Techniques: Ground, Sensing, and Capacitor Placement

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A good LDO on paper can still behave badly on a bad printed circuit board. The devices themselves are forgiving, but the currents they carry, the grounds they reference, and the high-frequency paths they rely on are easy to get wrong. Layout choices determine whether the measured PSRR, transient response, and noise match the datasheet, and whether the regulator oscillates or behaves. This article walks through the practical layout rules that separate a clean supply from a noisy one.

1. The Ground Pin Carries Real Current

The LDO's ground pin is not a quiet reference. The quiescent current, the bias current for the internal circuits, and the return current of the external feedback divider all flow through it. Any resistance in that path appears as a voltage drop, and that drop is subtracted from the regulated output, because the internal reference is measured relative to the ground pin. The practical consequence is that the ground pin must be connected to the board ground with the lowest possible impedance, directly under the package, without sharing a narrow trace with other return currents. Star grounding, where the regulator's ground pin connects to a quiet local ground that then joins the system ground at one point, avoids pulling noisy currents through the sensitive node.

1. Input and Output Capacitor Placement

The input capacitor must sit as close as possible to the input and ground pins, because it supplies the fast currents that the regulator demands during transients and reduces the high-frequency impedance of the source. A long trace between the capacitor and the pin adds inductance that the capacitor cannot offset. The output capacitor must likewise sit close to the output pin, because it is the local energy reservoir for the load step and the stability element of the loop. Ceramic capacitors are preferred because of their low ESR, but multiple smaller capacitors in parallel can be used when a single large part would be bulky. The loop stability depends on the output capacitor's ESR and capacitance, so substituting parts without checking the datasheet is a common cause of oscillation.

1. Sense and Kelvin Connections

When the load is far from the regulator, the trace resistance between the device and the load adds a millivolt-scale voltage drop under load. Adjustable LDOs allow remote sensing: the feedback trace is connected directly at the load, so the regulator compensates for the drop in the trace. The sense trace must be a Kelvin connection, taken from the load's output node and routed separately from the power trace, and it must be kept away from switching traces because it is a high-impedance node. Remote sensing is not available on every fixed part, so for long or heavy loads the trace resistance should be calculated and kept below a few tens of milliohms.

1. Minimizing Parasitic Inductance

Every trace has inductance, and at the fast edges of a load transient even a few nanohenries matter. The input and output loops, formed by the capacitor, the pin, and the ground return, should be as small as possible, with the capacitor ground placed directly under the package ground. Vias placed near the pads reduce inductance, but too many vias under a small part can complicate soldering. The feedback trace should be short and direct, with no unnecessary vias, because any extra series inductance or shunt capacitance shifts the loop poles.

1. Avoiding Ground Bounce and Coupling

The ground bounce caused by large digital return currents on the same plane as the analog ground can couple into the LDO and appear on the output. The usual remedy is to split the layout into quiet and noisy areas, with the LDO and its load on the quiet side, and to connect the two grounds at a single point under the regulator. Digital return paths should never run under the LDO package. Likewise, the LDO should be kept away from crystal oscillators, switching converters, and high-speed data lines, whose fields can couple into the sensitive feedback node.

1. The Bypass and Noise-Reduction Pins

Many LDOs include a bypass pin, which connects to the internal reference through an external capacitor. That capacitor filters the reference noise and is one of the most important components for low-noise performance. It must be placed directly at the pin, and its ground must be a quiet local ground, not the noisy digital return. A long trace on the bypass pin turns the capacitor into an antenna rather than a filter, and defeats the purpose of the part.

1. A Layout Checklist

Before sending a board for fabrication, it is worth running through a short list. The input capacitor is within a few millimeters of the input pin. The output capacitor is close to the output pin and its ground returns to the LDO ground. The feedback trace is short, quiet, and Kelvin if remote sensing is used. The ground pin connects directly to a quiet local ground. The thermal pad, if present, has multiple vias to a ground plane. The LDO is kept away from switching and clocking circuits. Following these rules does not guarantee success, but violating them is a common way to turn a good regulator into an unstable one.

Summary

• The LDO ground pin carries real bias current and must be connected to a low-impedance quiet ground.
• Input and output capacitors must be placed close to their pins to keep loop inductance low.
• Remote sensing uses a Kelvin feedback connection to compensate for trace drops at distant loads.
• The bypass pin capacitor must be local and referenced to quiet ground to actually reduce output noise.
• Keeping the LDO away from noisy digital circuits and using a clean ground plan is as important as the schematic.