Reviewed by AtlasPCB Engineering Team
Every PCB design eventually confronts a fundamental manufacturing question: can the fabricator hold your trace geometry with conventional etching, or does the design require a fundamentally different process? For decades that question rarely came up, because most designs stayed comfortably within the capability window of subtractive etching. That is changing. As package densities increase, as 5G mmWave antenna arrays demand tighter pitch, and as system-in-package architectures push interconnect density toward IC substrate territory, the line between "subtractive can handle it" and "you need mSAP" has become one of the most consequential decisions in PCB engineering.
We manufacture both ways. Our subtractive lines run hundreds of panels a day across the full range of standard and HDI constructions, and our mSAP-capable lines handle the designs that have moved beyond what etching can reliably produce. This article shares what we have learned from operating both processes side by side — where each one excels, where each one fails, and exactly where the crossover point falls in real production.
How Subtractive Etching Defines Most PCBs Made Today
The subtractive process is the foundation of modern PCB manufacturing, and for good reason. The concept is straightforward: start with a copper-clad laminate where a full sheet of copper foil has been bonded to the dielectric substrate during lamination. Apply a photosensitive resist layer, expose it through a phototool or with a laser direct imaging system to define the circuit pattern, develop away the unexposed resist to reveal the copper that needs to be removed, etch the exposed copper in a chemical bath, and finally strip the remaining resist to leave behind the finished traces.
This process has been refined over more than fifty years of industrial production. The chemistry is well understood, the equipment is mature, and the supply chain for materials — standard FR-4 laminates, copper foils in standard thicknesses from half-ounce to two-ounce, alkaline and acidic etchant systems — is deep and globally distributed. A competent fabricator can run subtractive etching with high yield, tight process control, and predictable costs. When we quote a standard 4-layer or 6-layer board with 100-micron (4 mil) trace and space, we know exactly what the panel yield will be, how long the etch cycle takes, and what the per-unit cost looks like at any volume from prototype to mass production.
The dominance of subtractive etching is not just about tradition. It is genuinely the most cost-effective way to produce the vast majority of PCB designs. If your traces are 75 microns (3 mil) or wider, if your copper weight is half-ounce or one-ounce on outer layers, and if your impedance tolerances are within the standard plus-or-minus ten percent window, subtractive etching delivers exactly what you need at a price point that no other process can match. For a deeper look at what fabricators need in your design package to run subtractive production smoothly, see our guide on PCB manufacturing files and the complete package your manufacturer needs.
Where Subtractive Hits Its Limits — The Etch Factor Problem
The physics of chemical etching impose a hard constraint that no amount of process optimization can fully overcome. When etchant dissolves copper, it attacks the metal isotropically — meaning it etches laterally underneath the resist mask at the same rate it etches downward through the copper thickness. This lateral undercut is described by the etch factor, which is the ratio of etch depth to lateral etch distance. In a well-controlled production environment, typical etch factors range from 2.5 to 3.5 for alkaline cupric chloride etchants, with the best acidic systems reaching etch factors of 3.5 to 4.0 under ideal conditions.
The practical consequence is that every trace produced by subtractive etching has a trapezoidal cross-section. The top of the trace, protected by the resist, is narrower than the base where the etchant first contacts the copper. For a standard half-ounce copper foil (approximately 17 microns thick) with an etch factor of 3.0, the lateral undercut on each side is roughly 5.7 microns. On a trace with a 75-micron design width, that undercut reduces the top width to approximately 63.6 microns — a manageable deviation that impedance modeling can accommodate.
Now consider what happens as you push toward finer geometries. On a 50-micron (2 mil) trace with the same half-ounce copper, the same 5.7-micron undercut per side reduces the top width to about 38.6 microns. The trace now has a top-to-bottom width ratio of roughly 0.77, producing a noticeably trapezoidal profile. Impedance modeling can still handle this, but the tolerance band narrows considerably, and any variation in etch uniformity across the panel directly impacts impedance consistency.
Push further to 38 microns (1.5 mil) and the situation becomes critical. The top width drops to approximately 26.6 microns, a top-to-bottom ratio of 0.70, and the copper cross-sectional area has been reduced so significantly that current-carrying capacity and conductor loss both suffer. At 30 microns, assuming you could even resolve and develop the resist pattern at that pitch, the top width would be around 18.6 microns — less than two-thirds of the designed width, with a cross-section so far from rectangular that impedance prediction becomes unreliable.
We see this play out in production every week. Boards designed at 50-micron trace and space on standard half-ounce copper run with acceptable yield in our subtractive lines, though they require tighter process monitoring than designs at 75 microns. Boards at 38 microns require ultra-thin foils and modified chemistry, which we will discuss later. Below 30 microns, we do not attempt subtractive etching — the physics simply do not support it.
How mSAP Works — Building Traces Up Instead of Etching Them Down
The modified semi-additive process inverts the logic of subtractive etching. Instead of starting with a thick copper layer and removing everything you do not need, mSAP starts with a very thin copper seed layer — typically 2 to 5 microns — and adds copper only where the traces are supposed to be.
The process begins with a dielectric substrate that already has a thin copper foil laminated to its surface. This seed layer is far thinner than the half-ounce (17-micron) or quarter-ounce (9-micron) foils used in subtractive processing. A layer of photoresist is applied and patterned using the circuit artwork, but here the resist acts as a negative image: it covers the areas where copper should not be deposited, leaving the trace locations exposed. The panel then goes through an electroplating bath where copper is built up in the exposed areas to the desired final thickness, typically 15 to 25 microns depending on the design requirements.
After plating, the photoresist is stripped away, revealing the thin seed copper between the plated traces. This seed layer is then removed by a brief flash etch — a short, carefully controlled etching step that dissolves the 2-to-5-micron seed layer without significantly attacking the much thicker plated traces. Because the flash etch only needs to remove a few microns of copper, the lateral undercut is minimal — on the order of 1 to 2 microns — preserving the near-vertical sidewall profile that electroplating naturally produces.
The result is a trace with a substantially rectangular cross-section. The sidewall angle in mSAP traces typically measures 85 to 88 degrees from horizontal, compared to 65 to 75 degrees in subtractive traces. This near-vertical profile means the designed trace width and the actual trace width are nearly identical, impedance prediction is highly accurate, copper cross-sectional area matches design intent, and conductor loss is minimized.
It is worth distinguishing mSAP from full SAP, the fully additive semi-additive process used in IC substrate manufacturing. In full SAP, there is no pre-laminated copper foil at all. Instead, a catalytic seed layer — typically electroless copper deposited on a roughened or chemically activated dielectric surface — serves as the plating base. Full SAP can achieve the finest features, down to sub-10-micron trace and space, but it demands extremely smooth dielectric surfaces and a much more sensitive electroless copper adhesion mechanism. mSAP trades a small amount of resolution capability for substantially better process robustness and adhesion reliability, making it the practical choice for most fine-line PCB applications above 15 microns. For more on how flash copper plating supports both HDI microvias and mSAP seed layer processing, see our technical article on flash copper plating for HDI microvias and mSAP seed layers.
Line and Space Capabilities — The Real Numbers
Understanding where each process sits on the resolution spectrum is essential for making the right manufacturing decision. The capabilities are not theoretical maximums from laboratory demonstrations — they reflect what volume production can sustain with acceptable yield.
Standard subtractive etching with half-ounce copper foil and conventional etch chemistry handles trace and space down to approximately 50 microns (2 mil) in reliable production. Below 50 microns, yield drops and impedance variation increases to the point where many fabricators either refuse the job or quote significant premiums for the tighter process control required.
Advanced subtractive techniques — using ultra-thin copper foils of 5 to 9 microns, modified etch chemistry, and laser direct imaging — can push subtractive capability down to approximately 38 microns (1.5 mil) trace and space with acceptable production yield. Some fabricators claim 30-micron capability with advanced subtractive, but in our experience, the yield and impedance consistency at that geometry do not support volume production.
mSAP reliably produces trace and space geometries down to 15 to 20 microns in production. The finest features we run in volume are 20-micron trace and space for substrate-like PCB constructions, with 25-micron being a more common and higher-yield target for most fine-line applications.
Full SAP pushes into sub-10-micron territory, but this is IC substrate manufacturing — a different class of facility, equipment, and cost structure. For PCB-level applications, mSAP covers the range between 15 and 30 microns that subtractive cannot reach.
The zones, in practical terms, break down clearly. Above 50 microns, standard subtractive is the obvious choice. Between 38 and 50 microns, advanced subtractive techniques are the most cost-effective approach. Between 20 and 38 microns, the decision depends on your exact geometry, impedance requirements, and volume — but mSAP becomes increasingly attractive as you move toward the lower end of this range. Below 20 microns, mSAP or full SAP are the only viable options.
When to Choose mSAP Over Subtractive — The Decision Framework
The crossover point where mSAP becomes necessary rather than optional falls at approximately 30 microns (1.2 mil) trace and space. This is not an arbitrary number. It reflects the geometry at which subtractive etch factor limitations make it physically impossible to maintain an adequate copper cross-section for reliable impedance control, acceptable conductor loss, and consistent yield.
Above 30 microns, advanced subtractive techniques can still deliver acceptable results at significantly lower cost than mSAP. The engineering rationale is straightforward: with a 5-micron ultra-thin foil and an etch factor of 3.5, the lateral undercut per side is only about 1.4 microns, which preserves trace geometry well enough for impedance control at 35-to-50-micron features. The cost of ultra-thin foil processing is substantially less than the full mSAP process with its specialized materials and additional plating steps.
Below 30 microns, no amount of subtractive process optimization can compensate. Even with the thinnest available foils and the most selective etch chemistry, the remaining copper cross-section after etching is too small to deliver the designed impedance with acceptable tolerance, and the trapezoidal profile introduces enough geometric uncertainty to make impedance prediction unreliable.
Several application categories reliably require mSAP today. Smartphone-like PCBs (SLP, or substrate-like PCBs) are perhaps the most prominent, where the combination of thin form factor and high interconnect density demands trace geometries of 25 to 30 microns. System-in-package modules integrate multiple die on a common substrate and frequently require fine-pitch redistribution routing that only mSAP or SAP can produce. 5G antenna-in-package designs, where mmWave antenna elements must be precisely positioned with controlled-impedance feed structures at tight pitch, are another growing application. Advanced wearable devices and medical implant electronics also increasingly push into mSAP territory as their form factors shrink.
Conversely, many high-performance applications still belong on subtractive lines. High-layer-count server boards at 50-micron trace and space, automotive radar modules at 75-micron features on specialized low-loss laminates, aerospace avionics boards with conservative design rules — all of these are better served by the mature subtractive process with its lower cost, shorter lead times, and broader material selection.
Volume and cost also play a role in the decision. For prototype and low-volume production, the NRE costs of mSAP tooling and process qualification can add several thousand dollars to a project. At high volume, the per-unit premium narrows because material costs amortize and process yield stabilizes, but it never disappears entirely.
Material Considerations — ABF, Low-Dk Prepreg, and Copper Foil Selection
The material requirements for mSAP are fundamentally different from subtractive processing, and this difference is one of the primary cost drivers. The critical factor is dielectric surface roughness. In subtractive processing, moderate surface roughness is actually desirable because it promotes copper adhesion through mechanical interlocking between the copper foil and the resin surface. Standard FR-4 laminates have surface roughness values (Rz) in the range of 3 to 8 microns, which provides excellent adhesion for conventional foils.
In mSAP, that roughness becomes a liability. The thin seed copper layer of 2 to 5 microns cannot conformally cover a surface with roughness features approaching or exceeding the seed layer thickness itself. Incomplete coverage leads to adhesion failures, open circuits during flash etching, and unreliable plating nucleation. mSAP therefore requires dielectric surfaces with Rz roughness below 2 microns, and preferably below 1.5 microns.
Ajinomoto Build-up Film (ABF) is the dominant dielectric material for mSAP processing. Originally developed for IC substrate manufacturing, ABF provides an extremely smooth surface after lamination and curing, with Rz values typically below 1 micron. It also offers good dielectric properties (Dk around 3.3 to 3.5 at 1 GHz) and is well-characterized for fine-line processing. The drawback is cost — ABF is substantially more expensive than standard FR-4 prepreg, and it requires vacuum lamination equipment rather than standard hydraulic presses.
Modified prepreg systems from major laminate suppliers have expanded the material options for mSAP. Panasonic Megtron series and Mitsubishi BT resin systems both offer low-roughness variants engineered for mSAP compatibility. These materials can be processed on modified conventional lamination equipment, reducing the capital investment required compared to ABF-only facilities. Their dielectric properties are competitive with ABF, and some formulations offer lower loss tangent for applications where signal integrity at high frequency is critical.
Standard FR-4 remains unsuitable for mSAP. Its relatively rough copper-dielectric interface, which is an advantage for adhesion in subtractive processing, prevents reliable seed layer deposition and adhesion in the mSAP flow. We occasionally receive inquiries from designers who want mSAP resolution on FR-4 substrates, and the answer is always the same: the material system and the process are inseparable in fine-line manufacturing.
DFM Guidelines for mSAP Designs
Designing for mSAP fabrication requires several adjustments to the DFM practices that engineers have developed around subtractive processing. The differences are not dramatic, but ignoring them leads to yield issues, unnecessary cost, and sometimes outright manufacturing failures.
Pad design is the first area where mSAP diverges from subtractive conventions. In subtractive processing, annular ring specifications account for the etch factor by designing pads larger than the minimum needed for via capture. In mSAP, where the trace geometry is more faithful to the design intent, pad sizes can be reduced — but they must account for the alignment tolerance of the plating resist pattern to the drilled or laser-ablated via. We recommend maintaining at least 25 microns of annular ring on mSAP designs, compared to the 50-to-75-micron annular rings typical in subtractive HDI.
Via structures in mSAP designs need careful attention. Laser-drilled microvias are the standard interconnect in mSAP constructions, and the via diameter, capture pad, and plating aspect ratio must be coordinated with the mSAP process flow. Microvias are typically laser-drilled before seed layer deposition, and the via fill plating occurs simultaneously with trace plating. This means the via aspect ratio must be compatible with the plating bath chemistry and current density used for trace formation. We generally recommend via diameters of 50 to 75 microns for mSAP layers, with aspect ratios below 1:1 for reliable fill.
Copper balance across the panel is more critical in mSAP than in subtractive processing. In subtractive etching, large copper areas and fine traces are processed simultaneously — the etchant removes copper everywhere at roughly the same rate (with some loading effects). In mSAP, the electroplating step is sensitive to current density distribution. Large open areas adjacent to fine traces will plate faster, potentially producing over-thick copper in wide areas and under-thick traces in dense regions. Designing with uniform copper distribution, using hatched fills instead of solid pours in non-critical areas, and avoiding large disparities in feature density across the panel all improve plating uniformity and yield.
The most common mistake we see from designers new to mSAP is treating it as a drop-in replacement for subtractive processing with smaller numbers. It is not. The design rules, stackup construction, material selection, and via structures all interact with the mSAP process in ways that require intentional design choices. For guidance on HDI stackup design practices that complement mSAP fabrication, see our article on HDI PCB stackup design for advanced applications.
Cost and Lead Time Implications
mSAP carries a cost premium that designers and procurement teams need to understand in concrete terms. At comparable layer counts and board complexity, mSAP fabrication typically costs 40 to 80 percent more than conventional subtractive fabrication. The premium is not a single line item but rather the accumulation of several cost drivers.
Materials account for a significant portion. ABF or modified low-roughness prepreg systems cost two to three times more per panel than standard FR-4. The ultra-thin copper foils used as seed layers are also more expensive than standard foils, and they require more careful handling throughout the lamination and processing steps, which increases labor and scrap costs.
The additional process steps in mSAP — seed layer preparation, precise photoresist application and patterning for the plating mask, electroplating with tight thickness control, resist stripping, and flash etching with narrow process windows — each add cycle time and require specialized equipment. The flash etch step in particular demands precise timing and chemistry control, because over-etching the seed layer will damage the trace edges while under-etching leaves conductive residue that causes shorts.
Process yield is another factor. mSAP process windows are tighter than subtractive, meaning a higher percentage of panels may require rework or scrap, particularly during initial production ramp-up. As production volume increases and the process stabilizes for a given design, yield improves and the per-unit cost premium decreases — but it remains meaningfully above subtractive costs at any volume.
Lead times for mSAP are typically one to two weeks longer than equivalent subtractive constructions, reflecting the additional process steps and the more limited availability of mSAP-capable production capacity. Prototype quantities may see even longer lead times if the design requires material procurement or process qualification.
The Middle Ground — Advanced Subtractive Techniques
Before committing to the cost and complexity of mSAP, it is worth understanding how far advanced subtractive techniques can push conventional processing. In many cases, the design requirements fall in a gray zone between standard subtractive capability and mSAP territory, and advanced subtractive provides a cost-effective solution.
Ultra-thin copper foils are the single most impactful change. Replacing standard half-ounce (17-micron) foil with 5-micron or 9-micron foil dramatically reduces the etch depth and therefore the lateral undercut. With a 5-micron foil and an etch factor of 3.5, the undercut per side is only 1.4 microns — compared to 4.9 microns with half-ounce foil under the same conditions. This transforms the achievable trace geometry. A 38-micron trace on 5-micron foil retains a top width of approximately 35.2 microns, a top-to-bottom ratio of 0.93 that produces a nearly rectangular cross-section with predictable impedance behavior.
Modified etch chemistry further improves the picture. Formulations with enhanced vertical-to-lateral selectivity, sometimes described as anisotropic etch enhancers, can push the effective etch factor from the standard 3.0-3.5 range up to 4.0-4.5 under optimized conditions. These chemistries typically involve additives that preferentially inhibit lateral etching at the copper-resist interface. Combined with ultra-thin foils, modified chemistry extends reliable subtractive capability into the 35-to-40-micron range with production-worthy yield.
Laser direct imaging replaces traditional phototool-based exposure with a focused laser that writes the pattern directly onto the resist. LDI eliminates the dimensional errors introduced by phototool film instability and off-contact exposure, improving feature resolution and registration accuracy. For fine-line subtractive work, LDI is effectively mandatory — the registration and resolution requirements below 50 microns exceed what conventional phototool exposure can reliably deliver.
The combination of ultra-thin foils, modified etch chemistry, and LDI represents the practical frontier of subtractive processing. In our production experience, this combination can reliably produce 38-micron (1.5 mil) trace and space with good yield and impedance control. At 35 microns, yield begins to drop. At 30 microns, we see unacceptable variation in trace geometry and impedance, confirming the crossover point where mSAP becomes necessary.
For designs that fall in the 35-to-50-micron range, advanced subtractive is almost always the right answer. The materials are less expensive, the process is more forgiving, lead times are shorter, and the number of qualified fabricators is larger. Only when the design genuinely requires sub-30-micron features — or when the near-vertical sidewall profile of mSAP is needed for signal integrity reasons even at wider geometries — does the premium for mSAP become justified.
The choice between mSAP and subtractive is ultimately an engineering and economic decision, not a technology preference. Both processes produce excellent PCBs within their capability windows. The key is understanding exactly where those windows overlap, where they diverge, and what your specific design demands. We have run both processes long enough to know that the right answer is always the one that meets your electrical, mechanical, and cost requirements with the best balance of margin and value.
Originally published on AtlasPCB. AtlasPCB manufactures advanced PCBs using both subtractive and mSAP processes for HDI, SiP, and fine-line applications.
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