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The Hidden Hardware Cost of Multi-Tasking: Context Switching & TLB Flushes

#linux #programming #operatingsystems #tutorial

The Hidden Hardware Cost of Multi-Tasking: Context Switching & TLB Flushes

When your laptop runs hundreds of background processes on an 8-core CPU, the operating system creates the illusion of simultaneous execution through rapid Context Switching.

However, context switching is not free. Beyond the few microseconds it takes to swap CPU registers, there is a massive hidden penalty: Memory Cache Coldness and TLB Invalidation.

⚡ What Happens During a Context Switch? 

Physical CPU Silicon
┌──────────────────────────────────────────────┐
│  PC | SP | RAX | RBX | RDI | CR3 Page Dir    │
└──────────────────────────────────────────────┘
       │                               ▲
1. SAVE to PCB(P1)             2. RESTORE from PCB(P2)
       ▼                               │
Kernel Memory: Process Control Blocks (PCB)
┌───────────────────────┐      ┌───────────────────────┐
│ PCB for Process P1    │      │ PCB for Process P2    │
│ • State: READY        │      │ • State: RUNNING      │
│ • Saved CPU Registers │      │ • Saved CPU Registers │
│ • Memory Maps (CR3)   │      │ • Memory Maps (CR3)   │
└───────────────────────┘      └───────────────────────┘
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  1. Hardware State Preservation: The kernel saves P₁'s Program Counter (PC), Stack Pointer (SP), general-purpose registers, and flags into its Process Control Block (PCB) in kernel memory.
  2. Scheduler Execution: The scheduler decides which thread to run next based on priority or CPU burst estimates.
  3. Hardware State Restoration: The kernel loads P₂'s register state into the physical CPU silicon and updates the CR3 register to point to P₂'s page tables.

🧠 The Hidden Killers: TLB & Cache Coldness

Saving 16 registers takes less than 100 nanoseconds. The real performance degradation comes from the memory subsystem:

1. TLB Invalidation (Translation Lookaside Buffer)

The CPU's MMU uses the TLB to cache virtual-to-physical address mappings. Because P₁ and P₂ have completely different virtual address spaces, switching processes flushes the TLB entries.

  • Every subsequent memory access suffers a TLB Miss, forcing the MMU into slow 4-level DRAM page table walks!

2. L1/L2 Cache Pollution

P₁'s working set filled the ultra-fast L1 and L2 CPU caches (which respond in ~1–4 cycles). When P₂ begins executing, it encounters an avalanche of cache misses, stalling the CPU on main DRAM (100–300 cycles per miss).

🛠️ Why Threads Are Cheaper Than Processes

Threads within the same process share the same virtual memory space (same page directory).

  • When the kernel switches between threads of the same process, it swaps CPU registers, but does NOT need to flush the TLB.
  • This makes thread context switches significantly faster than full process context switches.

🚀 Inspect PCB Data Structures Interactively

You can inspect raw Linux PCB structures, track register snapshots, and calculate switching latency on Binary Dose.

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