NVIDIA quietly revises shipping specs for Rubin GPU as first production hardware arrives

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📅 October 31, 2026 • ServeTheHome

NVIDIA has quietly revised the published specifications of its Rubin GPU, and the updated figures now describe hardware that is actually shipping. According to a ServeTheHome report published on October 31, 2026, the changes appeared in the September update of the NVIDIA architecture datasheet, where they were spotted by the publication IT Home. The revision lands at the same time as the first Vera Rubin NVL72 systems become generally available at hyperscalers. For a chip that headlines the next generation of NVIDIA systems, even quiet updates to bandwidth numbers draw attention across the datacenter industry.

The core configuration stays as announced. Rubin keeps 288GB of HBM4 memory organized as 8 stacks of 36GB each, along with 50 PFLOPS of NVFP4 inference performance and 35 PFLOPS of NVFP4 training performance. What changed is memory bandwidth, now listed at 19.2 TB/s, based on 8 stacks running at 9.375 Gbps per pin. The preliminary figure was 22 TB/s, so the per-pin data rate comes out roughly 13 percent lower than originally presented. The total capacity and the compute targets are therefore unchanged, and the correction is confined to how fast the memory can actually feed the chips.

The interconnect numbers moved in both directions. NVLink scale-up bandwidth, the links that tie GPUs together inside one system, was revised down from 3.6 TB/s to 3.0 TB/s. Scale-out networking bandwidth, which connects a node to the rest of the cluster, was revised up from 0.4 TB/s to 0.45 TB/s.

Taken together, the updates sketch a product that trades a little per-chip bandwidth for a slightly stronger external network position, while the compute promises remain untouched. Because the figures now describe shipping hardware rather than a preview, they also give buyers a firmer basis for planning clusters and for comparing Rubin against competing accelerators.

IMPACT: For teams planning AI infrastructure, these corrections matter more than their modest size suggests. A 13 percent cut to memory bandwidth and a lower NVLink scale-up figure change the arithmetic for workloads that are limited by memory and for training across many GPUs, even though the compute numbers are unchanged. The increase in scale-out bandwidth points to a design that leans on cluster-level networking, which fits the large NVL72 deployments now reaching general availability. Vendors and buyers can finally plan against shipping specifications instead of preview numbers, and datasheet updates that land once hardware ships become the reference point for procurement decisions.