TPS546D24A VRM: 40A Point-of-Load Design for Xilinx Ultrascale+

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Powering Xilinx Ultrascale+ FPGAs: A 40A Point-of-Load Design with the TPS546D24A

Why Xilinx Ultrascale+ Power Demands a 40A Point-of-Load Solution

When you design a board around a Xilinx Ultrascale+ FPGA, the core voltage rail (VCCINT) immediately becomes the most demanding supply on the board. Modern Ultrascale+ devices can draw 30 A to over 60 A on VCCINT alone, depending on logic utilization and the specific device. The voltage tolerance is brutally tight—typically ±3 % from DC to the full bandwidth of load transients—and the current can step from near-zero to full load in nanoseconds as thousands of logic cells switch simultaneously. Traditional multi-phase controllers with discrete MOSFETs can meet the current, but they eat up board area, complicate layout, and often require careful tuning of compensation networks.

A single-phase 40 A point-of-load (POL) module like the TPS546D24A from Texas Instruments changes the equation. It integrates the controller, power MOSFETs, inductor, and most of the passives into a compact 5 mm × 7 mm QFN package, delivering a clean 40 A continuous output with the transient response needed to keep VCCINT within spec. For many Ultrascale+ designs, one TPS546D24A can replace a whole multi-phase converter, simplifying the power tree and freeing up board space for high-speed transceivers and memory.

Beyond the raw current, Ultrascale+ power sequencing is non-negotiable. The VCCINT rail must ramp before VCCAUX (1.8 V) and VCCBRAM, and all supplies must reach their final values within a defined window. The TPS546D24A’s enable pin, power‑good output, and programmable soft‑start let you orchestrate this sequence without external sequencers. And if your FPGA supports SmartVID (adaptive voltage scaling), the device’s AVS interface can trim VCCINT on the fly with 2.5 mV resolution, squeezing out additional power savings.

Key takeaway: A 40 A POL module that combines high current density, fast transient response, PMBus telemetry, and native AVS support is no longer a luxury—it’s a practical necessity for modern Ultrascale+ power trees.

Inside the TPS546D24A: Key Specs and Control Architecture for 40A Rails

The TPS546D24A is a fully integrated synchronous buck converter that uses TI’s D‑CAP4™ control topology. Unlike traditional voltage‑mode or peak‑current‑mode controllers, D‑CAP4 emulates a constant on‑time ripple‑based control loop that responds to load steps within a single switching cycle. This eliminates the need for external compensation components and delivers a nearly flat impedance profile across frequency, which is exactly what you want when powering an FPGA core that can throw a 30 A load step in 100 ns.

The device operates from a 4.5 V to 16 V input bus, making it compatible with standard 12 V intermediate rails. The output voltage is adjustable from 0.6 V to 5.5 V via PMBus or pin‑strapping, and the switching frequency can be set anywhere from 300 kHz to 2 MHz. At 40 A load, 12 V input, and 0.85 V output, the efficiency typically peaks above 92 %—a figure that holds up well even at 1 MHz switching.

What truly sets the TPS546D24A apart for FPGA power is its digital interface. The PMBus 1.3‑compliant engine gives you read‑back of output voltage, output current, internal temperature, and fault status, while also letting you adjust the output voltage, warning thresholds, and fault responses. The AVS (Adaptive Voltage Scaling) block accepts either a PWM or I²C command from the FPGA and translates it into a voltage adjustment with 2.5 mV resolution—no external DAC required.

Parameter	Value / Range	Notes
Input voltage range	4.5 V to 16 V	12 V nominal, 5 V tolerant
Output voltage range	0.6 V to 5.5 V	Set via PMBus or pin‑strap
Continuous output current	40 A	No derating up to 85 °C ambient with airflow
Output voltage accuracy	±0.5 % over temperature	Includes line, load, and temperature drift
Switching frequency	300 kHz to 2 MHz	Resistor or PMBus selectable
Peak efficiency (12 V→0.85 V, 40 A)	>92 %	Measured on TI EVM, 1 MHz
Transient response (10 A step)	<30 mV deviation	D‑CAP4 control, no external compensation
PMBus command set	VOUT_COMMAND, READ_VOUT, READ_IOUT, READ_TEMPERATURE_1, etc.	Full PMBus 1.3 compliance
AVS resolution	2.5 mV	PWM or I²C input from FPGA
Package	5 mm × 7 mm QFN, 0.5 mm pitch	Exposed thermal pad

Data from TI TPS546D24A datasheet and EVM user guide.

The D‑CAP4 control loop deserves a closer look. Because the on‑time is modulated directly by the input voltage and the output ripple, the converter maintains a constant switching frequency in steady state while reacting to load transients with a near‑instantaneous duty‑cycle change. This eliminates the phase lag introduced by an error amplifier and compensation network, so the output capacitance can be smaller than what a voltage‑mode converter would demand. For an Ultrascale+ VCCINT rail, you can often meet the transient window with just a few 100 µF ceramic capacitors and a single bulk polymer capacitor, saving both cost and board area.

Alternative 40A POL Regulators: How the TPS546D24A Stacks Up

No single POL regulator fits every design, so it’s worth comparing the TPS546D24A with other 40 A‑class solutions that you might encounter in FPGA power trees. The table below contrasts it with three alternatives that represent different integration philosophies: a multi‑channel µModule (LTM4644), a 30 A digital module (ISL8273M), and a discrete DrMOS power stage (TDA21470). Each has its place, but for a single‑rail 40 A Ultrascale+ core supply, the trade‑offs become clear.

Feature	TPS546D24A	LTM4644 (Analog Devices)	ISL8273M (Renesas)	TDA21470 (Infineon)	Selection Notes
Output current (per device)	40 A continuous	4 A per channel, 4 channels	30 A	70 A (power stage only)	TPS546D24A hits 40 A without paralleling; LTM4644 would need 10 channels to reach 40 A
Integration level	Full converter (controller + FETs + inductor)	Full converter, 4 independent outputs	Full converter	DrMOS power stage + external controller	TPS546D24A and ISL8273M are complete POLs; TDA21470 requires a separate PWM controller and inductor
Control interface	PMBus + AVS (I²C/PWM)	Analog only (resistor divider)	PMBus	PWM input (analog)	Only TPS546D24A and ISL8273M offer digital telemetry; TPS546D24A adds native AVS
Transient response	D‑CAP4 constant on‑time, <30 mV for 10 A step	Current‑mode, requires external compensation	Digital control loop, configurable via PMBus	Depends on external controller	D‑CAP4 eliminates compensation design; ISL8273M’s digital loop can be tuned but adds complexity
Footprint	5 mm × 7 mm QFN	15 mm × 15 mm BGA	15 mm × 15 mm QFN	5 mm × 6 mm QFN (power stage only)	TPS546D24A saves significant board area vs. ISL8273M or a multi‑channel LTM4644
PMBus telemetry (V/I/T)	Yes	No	Yes	No	Essential for remote debug and margining in FPGA systems
AVS support	Yes (2.5 mV steps)	No	No	No	Direct FPGA SmartVID interface without extra DACs

Datasheet references: TPS546D24A (ti.com), LTM4644 (analog.com), ISL8273M (renesas.com), TDA21470 (infineon.com).

The LTM4644 is an excellent choice when you need four independent, low‑current rails in a single package, but it’s not a 40 A solution. To reach 40 A you would have to parallel all four channels and still fall short, or use multiple modules, which quickly erodes the integration advantage. The ISL8273M comes close with 30 A and a full PMBus suite, but its larger footprint and lack of AVS mean you’ll need an external DAC for SmartVID and possibly a second module to reach 40 A. The TDA21470 is a high‑efficiency power stage, but you must add a controller, inductor, and compensation network; the design effort and board space approach that of a discrete multi‑phase converter, defeating the purpose of a compact POL.

For a dedicated 40 A VCCINT rail with PMBus visibility and AVS, the TPS546D24A provides the most integrated, single‑chip path from 12 V to the FPGA core.

Layout, Sequencing, and Sourcing Tips for TPS546D24A Designs

A 40 A POL demands careful PCB layout to keep noise low and thermals under control. The TPS546D24A’s QFN package with an exposed thermal pad simplifies heat sinking, but you still need to move that heat into the board. Here are the practices that have proven themselves in multiple Ultrascale+ designs:

Power stage layout

Place the input ceramic capacitors (10 µF, X7R) as close as possible to the VIN and PGND pins. Use multiple vias to the inner power plane to minimize loop inductance.
Keep the SW node copper area small—just enough to carry the 40 A current—to reduce radiated EMI. Route the inductor connection directly from the SW pin to the inductor pad on the same layer.
Use a solid ground plane on layer 2 directly under the device. Stitch the exposed pad to this plane with a dense array of thermal vias (0.3 mm drill, 1.0 mm pitch). TI’s EVM (TPS546D24AEVM-1PH) demonstrates a 4‑layer stackup that keeps junction temperatures below 100 °C at 40 A with 200 LFM airflow.

PMBus and AVS routing

The PMBus clock and data lines (SCL, SDA) are open‑drain; place 2.2 kΩ pull‑up resistors near the TPS546D24A. Route them away from the SW node and inductor.
The AVS pin can accept a PWM signal directly from the FPGA. If you’re using I²C‑based AVS, the same SCL/SDA lines can be shared, but verify that the FPGA’s I²C master supports clock stretching. TI’s Fusion Digital Power Designer software makes initial configuration and debug straightforward, even without a dedicated USB‑to‑GPIO adapter—an FTDI cable or any MCU with I²C will work.

Sequencing for Ultrascale+

Drive the TPS546D24A’s EN pin from an upstream regulator’s power‑good signal, or from a system sequencer. Set the soft‑start time to 2 ms to 5 ms via PMBus to avoid inrush current tripping overcurrent protection.
Use the TPS546D24A’s PGOOD output to enable the VCCAUX regulator. This guarantees VCCINT is stable before VCCAUX ramps, satisfying the Ultrascale+ requirement. Xilinx UG583 provides detailed sequencing diagrams; the TPS546D24A fits directly into the recommended power‑up order.

Sourcing and lead times
As of mid‑2025, standard lead times for the TPS546D24A are 8–12 weeks through TI’s authorized distribution channel. For prototypes, Digi‑Key and Mouser typically stock the device in single‑unit quantities. For production volumes, Arrow and Avnet can provide scheduled deliveries and competitive pricing. If your BOM mixes many TI parts, IC‑Online is another reliable source for consolidated procurement. Always buy from authorized distributors to avoid counterfeit devices—a 40 A POL with integrated FETs is a prime target for gray‑market relabeling.

Layout Do’s	Layout Don’ts	Why It Matters
Place input caps within 2 mm of VIN/PGND pins	Route input power through long traces	Minimizes input loop inductance and voltage ringing
Use a solid ground plane on layer 2	Split the ground plane under the converter	Provides a low‑impedance return path for switching currents
Stitch thermal pad with ≥25 vias	Use a single large via or no thermal vias	Keeps junction temperature below 100 °C at 40 A
Route PMBus signals as a differential pair	Run PMBus parallel to SW node	Prevents noise coupling into digital telemetry
Follow Xilinx UG583 sequencing with PGOOD chaining	Enable all rails simultaneously	Avoids latch‑up and ensures proper FPGA configuration

Recommendations derived from TI TPS546D24AEVM-1PH user guide and Xilinx UG583.

TPS546D24A Design FAQ: Questions from the Lab and Procurement

Q: Can I parallel two TPS546D24A modules to supply 80A?

Yes, the device supports current sharing via the SYNC and ISHARE pins. Up to four TPS546D24A converters can be stacked to deliver 160 A, with one device acting as the master and the others as slaves. The entire stack appears as a single PMBus address, so you can monitor total current and adjust the output voltage with one command. Phase interleaving reduces input and output ripple, and the D‑CAP4 control ensures balanced current sharing without external sense resistors.

Q: How do I use the AVS interface to trim VOUT for Ultrascale+ SmartVID?

The AVS pin accepts either a PWM signal or an I²C command from the FPGA. In PWM mode, the duty cycle encodes the desired voltage offset from a nominal value stored in the TPS546D24A’s non‑volatile memory. In I²C mode, the FPGA sends a digital code that directly sets the output voltage with 2.5 mV resolution. The converter updates its reference within a few microseconds, so you can scale VCCINT dynamically as the FPGA’s process monitor adjusts the optimal voltage. No external DAC or level shifter is needed.

Q: What is the thermal performance at 40A with 12V input and 0.85V output?

With a 4‑layer board, 1 oz copper, and 200 LFM airflow, the junction temperature typically stays below 100 °C at 40 A load, 25 °C ambient. The exposed thermal pad and the device’s power stack construction spread heat evenly, avoiding hot spots. TI’s EVM user guide includes derating curves that show the maximum ambient temperature for a given airflow. If your enclosure has limited airflow, you can lower the switching frequency to 500 kHz to reduce switching losses, or use two modules in parallel to share the current.

Q: What are the typical lead times and authorized sources for the TPS546D24A?

Lead times fluctuate with market demand, but as of mid‑2025, standard delivery is 8–12 weeks. For prototypes, Digi‑Key and Mouser carry stock and ship same‑day. For production quantities, Arrow and Avnet offer volume pricing and can hold buffer stock. Always source from TI’s authorized distributors to guarantee authentic parts; the integrated FETs and PMBus engine make counterfeits both attractive to bad actors and dangerous to your design.

Q: Is there a reference design specifically for Xilinx Ultrascale+?

TI provides the TPS546D24AEVM-1PH evaluation board, which you can use as a starting point. The Xilinx Power Management Wiki (accessible through the Xilinx support portal) lists the TPS546D24A as a recommended POL for Ultrascale+ VCCINT rails, and the Ultrascale+ Power Management Tool includes it in the default BOM. Additionally, TI’s reference design library contains several schematics that pair the TPS546D24A with other TI power stages to form a complete Ultrascale+ power tree.

Q: Can I configure PMBus settings without a USB‑to‑GPIO adapter?

Absolutely. TI’s Fusion Digital Power Designer software works with any standard I²C master. You can connect an FTDI USB‑to‑I²C cable (part number C232HM‑DDHSL‑0) or use a microcontroller on your board to bridge USB and I²C. The device also supports offline configuration: you can program all PMBus settings into the TPS546D24A’s non‑volatile memory during manufacturing, and the converter will boot with those settings without any bus traffic. Many distributors offer pre‑programming services, so your boards arrive ready to power up.

The TPS546D24A brings together the current capability, transient performance, and digital telemetry that modern Ultrascale+ designs demand, all in a footprint that leaves room for the rest of your high‑speed circuitry. For prototypes and low‑volume builds, Digi‑Key and Mouser keep the part on the shelf. When you move to production, Arrow and Avnet can lock in lead times and pricing. If your BOM spans multiple semiconductor vendors, IC‑Online can consolidate procurement and simplify logistics. With the reference designs and tools available from TI and Xilinx, you can go from schematic to a working 40 A VCCINT rail faster than ever.