Bob Smith Termination: Circuit Analysis, Layout Rules, and Common Mistakes

Bob Smith termination is in every Ethernet schematic. Here's the complete technical breakdown — component values, impedance analysis, chassis ground vs signal ground, and layout rules.
Circuit Topology
Transformer center taps:

CT_PRI ──── 75Ω ──┐
CT_SEC ──── 75Ω ──┴── CTAP_NODE ──── 1000pF ──── CHASSIS_GND

For 1000BASE-T (4 pairs):

CT_PAIR1 ──── 75Ω ──┐
CT_PAIR2 ──── 75Ω ──┤
CT_PAIR3 ──── 75Ω ──┼── CTAP_NODE ──── 1000pF ──── CHASSIS_GND
CT_PAIR4 ──── 75Ω ──┘
Impedance Analysis: Why 1000pF
import math

C = 1000e-12 # 1000 pF

frequencies = [1e6, 10e6, 30e6, 100e6, 300e6]

print(f"{'Frequency':>12} | {'Zc (Ω)':>10} | {'Note'}")
print("-" * 50)
for f in frequencies:
Zc = 1 / (2 * math.pi * f * C)
note = ""
if f <= 1e6: note = "High Z — DC/LF isolation maintained"
if f >= 30e6: note = "Low Z — effective common-mode bypass"
if f >= 100e6: note = "Near-short — excellent at cable radiation freq"
print(f"{f/1e6:>10.0f}MHz | {Zc:>10.2f} | {note}")

Output:

1MHz | 159.15 | High Z — DC/LF isolation maintained

10MHz | 15.92 |

30MHz | 5.31 | Low Z — effective common-mode bypass

100MHz | 1.59 | Near-short — excellent at cable radiation freq

300MHz | 0.53 | Near-short — excellent at cable radiation freq

Chassis GND vs Signal GND: Critical Difference
CORRECT: CT → 75Ω → CTAP → 1000pF → CHASSIS_GND
✅ Common-mode discharges to chassis (large, clean plane)
✅ No coupling to PHY reference ground
✅ ESD energy absorbed by chassis
✅ Radiated emissions reduced

WRONG: CT → 75Ω → CTAP → 1000pF → SIGNAL_GND (DGND)
❌ Common-mode injects noise into PHY reference ground
❌ Common-mode → differential-mode conversion at PHY input
❌ Radiated emissions may INCREASE
❌ ESD stresses PHY ground reference
ESD Discharge Path Analysis
ESD pulse characteristics:
Rise time: ~1 ns (IEC 61000-4-2 Contact discharge)
Spectral content: significant energy to ~300 MHz

At 300 MHz, Zc of 1000pF ≈ 0.53Ω

Discharge path comparison at ESD frequencies:
Via Bob Smith 1000pF to chassis: ~0.53Ω + trace ← ESD prefers this path
Via transformer winding to PHY: hundreds of Ω ← ESD avoids this path

→ Bob Smith network provides first-stage ESD diversion
→ TVS diode handles residual large-energy events
PCB Layout Rules
Rule Target Why
─────────────────────────────────────────────────────────────────────
Trace: CT pin to 75Ω < 5mm 1mm ≈ 1nH; 10nH = 18.8Ω @ 300MHz
Trace: common node to 1000pF < 3mm Same inductance concern
Chassis ground pour Under transformer Low-impedance reference plane
Star ground point 1 controlled only Avoid ground loops
75Ω resistor placement Adjacent to CT pins Minimize series inductance
1000pF capacitor type C0G/NP0 preferred Stable at HF, low ESR/ESL
Common Implementation Mistakes
Mistake Consequence
──────────────────────────────────────────────────────────────────────
Cap to signal GND instead of chassis Noise injection into PHY
Missing center taps (10/100 ref for GbE) 2 of 4 pairs unterminated → EMC fail
Long traces to 75Ω resistors High series inductance → HF bypassing fails
No chassis ground pour No low-Z return path for common-mode
Cap omitted (only 75Ω to GND) DC ground loop possible; no HF bypass
75Ω omitted (only cap to chassis) No resistive termination; resonances possible
Values: Standard vs Variations
Standard (IEEE 802.3 reference):
75Ω + 1000pF to chassis GND

Acceptable variations:
49.9Ω or 51Ω (lower impedance, application-specific)
2× 1000pF parallel = 2000pF (lower Zc at lower frequencies)

• TVS diode in parallel with cap (enhanced ESD clamping)

Not recommended:
0Ω (no resistor): removes damping, can cause resonance
Signal GND connection: as above
Source
Voohu Technology (www.voohuele.com) — 1CT:1CT network transformers with center taps accessible on both windings. 50pcs MOQ, DHL 3–5 days.